[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
		clocks = <&tegra_car 132>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};
	
	tegra_ac97: ac97 {
		compatible = "nvidia,tegra20-ac97";
		reg = <0x70002000 0x200>;
		interrupts = <0 81 0x04>;
		nvidia,dma-request-selector = <&apbdma 12>;
		clocks = <&tegra_car 3>;
		status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <0 85 0x04>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	iommu {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	phy1: usb-phy@c5000400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000400 0x3c00>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy2: usb-phy@c5004400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004400 0x3c00>;
		phy_type = "ulpi";
		clocks = <&tegra_car 94>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy3: usb-phy@c5008400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008400 0x3C00>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
b6551bb9 LD	7	aliases {
	8	serial0 = &uarta;
	9	serial1 = &uartb;
	10	serial2 = &uartc;
	11	serial3 = &uartd;
	12	serial4 = &uarte;
	13	};
	14
ed821f07 TR	15	host1x {
	16	compatible = "nvidia,tegra20-host1x", "simple-bus";
	17	reg = <0x50000000 0x00024000>;
	18	interrupts = <0 65 0x04 /* mpcore syncpt */
	19	0 67 0x04>; /* mpcore general */
8d8b43da	20	clocks = <&tegra_car 28>;
ed821f07 TR	21
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	ranges = <0x54000000 0x54000000 0x04000000>;
	26
	27	mpe {
	28	compatible = "nvidia,tegra20-mpe";
	29	reg = <0x54040000 0x00040000>;
	30	interrupts = <0 68 0x04>;
8d8b43da	31	clocks = <&tegra_car 60>;
ed821f07 TR	32	};
	33
	34	vi {
	35	compatible = "nvidia,tegra20-vi";
	36	reg = <0x54080000 0x00040000>;
	37	interrupts = <0 69 0x04>;
8d8b43da	38	clocks = <&tegra_car 100>;
ed821f07 TR	39	};
	40
	41	epp {
	42	compatible = "nvidia,tegra20-epp";
	43	reg = <0x540c0000 0x00040000>;
	44	interrupts = <0 70 0x04>;
8d8b43da	45	clocks = <&tegra_car 19>;
ed821f07 TR	46	};
	47
	48	isp {
	49	compatible = "nvidia,tegra20-isp";
	50	reg = <0x54100000 0x00040000>;
	51	interrupts = <0 71 0x04>;
8d8b43da	52	clocks = <&tegra_car 23>;
ed821f07 TR	53	};
	54
	55	gr2d {
	56	compatible = "nvidia,tegra20-gr2d";
	57	reg = <0x54140000 0x00040000>;
	58	interrupts = <0 72 0x04>;
8d8b43da	59	clocks = <&tegra_car 21>;
ed821f07 TR	60	};
	61
	62	gr3d {
	63	compatible = "nvidia,tegra20-gr3d";
	64	reg = <0x54180000 0x00040000>;
8d8b43da	65	clocks = <&tegra_car 24>;
ed821f07 TR	66	};
	67
	68	dc@54200000 {
	69	compatible = "nvidia,tegra20-dc";
	70	reg = <0x54200000 0x00040000>;
	71	interrupts = <0 73 0x04>;
8d8b43da PG	72	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	73	clock-names = "disp1", "parent";
ed821f07 TR	74
	75	rgb {
	76	status = "disabled";
	77	};
	78	};
	79
	80	dc@54240000 {
	81	compatible = "nvidia,tegra20-dc";
	82	reg = <0x54240000 0x00040000>;
	83	interrupts = <0 74 0x04>;
8d8b43da PG	84	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	85	clock-names = "disp2", "parent";
ed821f07 TR	86
	87	rgb {
	88	status = "disabled";
	89	};
	90	};
	91
	92	hdmi {
	93	compatible = "nvidia,tegra20-hdmi";
	94	reg = <0x54280000 0x00040000>;
	95	interrupts = <0 75 0x04>;
8d8b43da PG	96	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	97	clock-names = "hdmi", "parent";
ed821f07 TR	98	status = "disabled";
	99	};
	100
	101	tvo {
	102	compatible = "nvidia,tegra20-tvo";
	103	reg = <0x542c0000 0x00040000>;
	104	interrupts = <0 76 0x04>;
8d8b43da	105	clocks = <&tegra_car 102>;
ed821f07 TR	106	status = "disabled";
	107	};
	108
	109	dsi {
	110	compatible = "nvidia,tegra20-dsi";
	111	reg = <0x54300000 0x00040000>;
8d8b43da	112	clocks = <&tegra_car 48>;
ed821f07 TR	113	status = "disabled";
	114	};
	115	};
	116
73368ba0 SW	117	timer@50004600 {
	118	compatible = "arm,cortex-a9-twd-timer";
	119	reg = <0x50040600 0x20>;
	120	interrupts = <1 13 0x304>;
ed3ced37	121	clocks = <&tegra_car 132>;
73368ba0 SW	122	};
73368ba0 SW	123
f9eb26a4	124	intc: interrupt-controller {
0d4f7479	125	compatible = "arm,cortex-a9-gic";
5ff48887 SW	126	reg = <0x50041000 0x1000
5ff48887 SW	127	0x50040100 0x0100>;
2eaab06e SW	128	interrupt-controller;
2eaab06e SW	129	#interrupt-cells = <3>;
8e267f3d GL	130	};
8e267f3d GL	131
bb2c1de9 SW	132	cache-controller {
	133	compatible = "arm,pl310-cache";
	134	reg = <0x50043000 0x1000>;
	135	arm,data-latency = <5 5 2>;
	136	arm,tag-latency = <4 4 2>;
	137	cache-unified;
	138	cache-level = <2>;
	139	};
	140
2f2b7fb2 SW	141	timer@60005000 {
	142	compatible = "nvidia,tegra20-timer";
	143	reg = <0x60005000 0x60>;
	144	interrupts = <0 0 0x04
	145	0 1 0x04
	146	0 41 0x04
	147	0 42 0x04>;
	148	};
	149
270f8ce3 SW	150	tegra_car: clock {
	151	compatible = "nvidia,tegra20-car";
	152	reg = <0x60006000 0x1000>;
	153	#clock-cells = <1>;
	154	};
	155
f9eb26a4	156	apbdma: dma {
8051b75a SW	157	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	158	reg = <0x6000a000 0x1200>;
95decf84 SW	159	interrupts = <0 104 0x04
	160	0 105 0x04
	161	0 106 0x04
	162	0 107 0x04
	163	0 108 0x04
	164	0 109 0x04
	165	0 110 0x04
	166	0 111 0x04
	167	0 112 0x04
	168	0 113 0x04
	169	0 114 0x04
	170	0 115 0x04
	171	0 116 0x04
	172	0 117 0x04
	173	0 118 0x04
	174	0 119 0x04>;
8d8b43da	175	clocks = <&tegra_car 34>;
8051b75a SW	176	};
8051b75a SW	177
c04abb3a SW	178	ahb {
	179	compatible = "nvidia,tegra20-ahb";
	180	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	181	};
8e267f3d GL	182
f9eb26a4	183	gpio: gpio {
8e267f3d	184	compatible = "nvidia,tegra20-gpio";
95decf84 SW	185	reg = <0x6000d000 0x1000>;
	186	interrupts = <0 32 0x04
	187	0 33 0x04
	188	0 34 0x04
	189	0 35 0x04
	190	0 55 0x04
	191	0 87 0x04
	192	0 89 0x04>;
8e267f3d GL	193	#gpio-cells = <2>;
8e267f3d GL	194	gpio-controller;
6f74dc9b SW	195	#interrupt-cells = <2>;
6f74dc9b SW	196	interrupt-controller;
8e267f3d GL	197	};
8e267f3d GL	198
f9eb26a4	199	pinmux: pinmux {
f62f548c	200	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	201	reg = <0x70000014 0x10 /* Tri-state registers */
	202	0x70000080 0x20 /* Mux registers */
	203	0x700000a0 0x14 /* Pull-up/down registers */
	204	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	205	};
f62f548c SW	206
c04abb3a SW	207	das {
	208	compatible = "nvidia,tegra20-das";
	209	reg = <0x70000c00 0x80>;
	210	};
0698ed19 LS	211
	212	tegra_ac97: ac97 {
	213	compatible = "nvidia,tegra20-ac97";
	214	reg = <0x70002000 0x200>;
	215	interrupts = <0 81 0x04>;
	216	nvidia,dma-request-selector = <&apbdma 12>;
	217	clocks = <&tegra_car 3>;
	218	status = "disabled";
	219	};
c04abb3a SW	220
	221	tegra_i2s1: i2s@70002800 {
	222	compatible = "nvidia,tegra20-i2s";
	223	reg = <0x70002800 0x200>;
	224	interrupts = <0 13 0x04>;
	225	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	226	clocks = <&tegra_car 11>;
223ef78d	227	status = "disabled";
c04abb3a SW	228	};
	229
	230	tegra_i2s2: i2s@70002a00 {
	231	compatible = "nvidia,tegra20-i2s";
	232	reg = <0x70002a00 0x200>;
	233	interrupts = <0 3 0x04>;
	234	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	235	clocks = <&tegra_car 18>;
223ef78d	236	status = "disabled";
c04abb3a SW	237	};
c04abb3a SW	238
b6551bb9 LD	239	/*
	240	* There are two serial driver i.e. 8250 based simple serial
	241	* driver and APB DMA based serial driver for higher baudrate
	242	* and performace. To enable the 8250 based driver, the compatible
	243	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	244	* driver, the comptible is "nvidia,tegra20-hsuart".
	245	*/
	246	uarta: serial@70006000 {
8e267f3d GL	247	compatible = "nvidia,tegra20-uart";
	248	reg = <0x70006000 0x40>;
	249	reg-shift = <2>;
95decf84	250	interrupts = <0 36 0x04>;
b6551bb9	251	nvidia,dma-request-selector = <&apbdma 8>;
8d8b43da	252	clocks = <&tegra_car 6>;
223ef78d	253	status = "disabled";
8e267f3d GL	254	};
8e267f3d GL	255
b6551bb9	256	uartb: serial@70006040 {
8e267f3d GL	257	compatible = "nvidia,tegra20-uart";
	258	reg = <0x70006040 0x40>;
	259	reg-shift = <2>;
95decf84	260	interrupts = <0 37 0x04>;
b6551bb9	261	nvidia,dma-request-selector = <&apbdma 9>;
8d8b43da	262	clocks = <&tegra_car 96>;
223ef78d	263	status = "disabled";
8e267f3d GL	264	};
8e267f3d GL	265
b6551bb9	266	uartc: serial@70006200 {
8e267f3d GL	267	compatible = "nvidia,tegra20-uart";
	268	reg = <0x70006200 0x100>;
	269	reg-shift = <2>;
95decf84	270	interrupts = <0 46 0x04>;
b6551bb9	271	nvidia,dma-request-selector = <&apbdma 10>;
8d8b43da	272	clocks = <&tegra_car 55>;
223ef78d	273	status = "disabled";
8e267f3d GL	274	};
8e267f3d GL	275
b6551bb9	276	uartd: serial@70006300 {
8e267f3d GL	277	compatible = "nvidia,tegra20-uart";
	278	reg = <0x70006300 0x100>;
	279	reg-shift = <2>;
95decf84	280	interrupts = <0 90 0x04>;
b6551bb9	281	nvidia,dma-request-selector = <&apbdma 19>;
8d8b43da	282	clocks = <&tegra_car 65>;
223ef78d	283	status = "disabled";
8e267f3d GL	284	};
8e267f3d GL	285
b6551bb9	286	uarte: serial@70006400 {
8e267f3d GL	287	compatible = "nvidia,tegra20-uart";
	288	reg = <0x70006400 0x100>;
	289	reg-shift = <2>;
95decf84	290	interrupts = <0 91 0x04>;
b6551bb9	291	nvidia,dma-request-selector = <&apbdma 20>;
8d8b43da	292	clocks = <&tegra_car 66>;
223ef78d	293	status = "disabled";
8e267f3d GL	294	};
8e267f3d GL	295
2b8b15da	296	pwm: pwm {
140fd977 TR	297	compatible = "nvidia,tegra20-pwm";
	298	reg = <0x7000a000 0x100>;
	299	#pwm-cells = <2>;
8d8b43da	300	clocks = <&tegra_car 17>;
140fd977 TR	301	};
140fd977 TR	302
380e04ac SW	303	rtc {
	304	compatible = "nvidia,tegra20-rtc";
	305	reg = <0x7000e000 0x100>;
	306	interrupts = <0 2 0x04>;
	307	};
	308
c04abb3a	309	i2c@7000c000 {
c04abb3a SW	310	compatible = "nvidia,tegra20-i2c";
	311	reg = <0x7000c000 0x100>;
	312	interrupts = <0 38 0x04>;
2eaab06e SW	313	#address-cells = <1>;
2eaab06e SW	314	#size-cells = <0>;
8d8b43da PG	315	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	316	clock-names = "div-clk", "fast-clk";
223ef78d	317	status = "disabled";
0c6700ab OJ	318	};
0c6700ab OJ	319
fa98a114 LD	320	spi@7000c380 {
	321	compatible = "nvidia,tegra20-sflash";
	322	reg = <0x7000c380 0x80>;
	323	interrupts = <0 39 0x04>;
	324	nvidia,dma-request-selector = <&apbdma 11>;
	325	#address-cells = <1>;
	326	#size-cells = <0>;
8d8b43da	327	clocks = <&tegra_car 43>;
fa98a114 LD	328	status = "disabled";
	329	};
	330
c04abb3a	331	i2c@7000c400 {
c04abb3a SW	332	compatible = "nvidia,tegra20-i2c";
	333	reg = <0x7000c400 0x100>;
	334	interrupts = <0 84 0x04>;
2eaab06e SW	335	#address-cells = <1>;
2eaab06e SW	336	#size-cells = <0>;
8d8b43da PG	337	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	338	clock-names = "div-clk", "fast-clk";
223ef78d	339	status = "disabled";
8e267f3d GL	340	};
8e267f3d GL	341
c04abb3a	342	i2c@7000c500 {
c04abb3a SW	343	compatible = "nvidia,tegra20-i2c";
	344	reg = <0x7000c500 0x100>;
	345	interrupts = <0 92 0x04>;
2eaab06e SW	346	#address-cells = <1>;
2eaab06e SW	347	#size-cells = <0>;
8d8b43da PG	348	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	349	clock-names = "div-clk", "fast-clk";
223ef78d	350	status = "disabled";
8e267f3d GL	351	};
8e267f3d GL	352
c04abb3a	353	i2c@7000d000 {
c04abb3a SW	354	compatible = "nvidia,tegra20-i2c-dvc";
	355	reg = <0x7000d000 0x200>;
	356	interrupts = <0 53 0x04>;
2eaab06e SW	357	#address-cells = <1>;
2eaab06e SW	358	#size-cells = <0>;
8d8b43da PG	359	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	360	clock-names = "div-clk", "fast-clk";
223ef78d	361	status = "disabled";
8e267f3d GL	362	};
8e267f3d GL	363
a86b0db3 LD	364	spi@7000d400 {
	365	compatible = "nvidia,tegra20-slink";
	366	reg = <0x7000d400 0x200>;
	367	interrupts = <0 59 0x04>;
	368	nvidia,dma-request-selector = <&apbdma 15>;
	369	#address-cells = <1>;
	370	#size-cells = <0>;
8d8b43da	371	clocks = <&tegra_car 41>;
a86b0db3 LD	372	status = "disabled";
	373	};
	374
	375	spi@7000d600 {
	376	compatible = "nvidia,tegra20-slink";
	377	reg = <0x7000d600 0x200>;
	378	interrupts = <0 82 0x04>;
	379	nvidia,dma-request-selector = <&apbdma 16>;
	380	#address-cells = <1>;
	381	#size-cells = <0>;
8d8b43da	382	clocks = <&tegra_car 44>;
a86b0db3 LD	383	status = "disabled";
	384	};
	385
	386	spi@7000d800 {
	387	compatible = "nvidia,tegra20-slink";
57471c8d	388	reg = <0x7000d800 0x200>;
a86b0db3 LD	389	interrupts = <0 83 0x04>;
	390	nvidia,dma-request-selector = <&apbdma 17>;
	391	#address-cells = <1>;
	392	#size-cells = <0>;
8d8b43da	393	clocks = <&tegra_car 46>;
a86b0db3 LD	394	status = "disabled";
	395	};
	396
	397	spi@7000da00 {
	398	compatible = "nvidia,tegra20-slink";
	399	reg = <0x7000da00 0x200>;
	400	interrupts = <0 93 0x04>;
	401	nvidia,dma-request-selector = <&apbdma 18>;
	402	#address-cells = <1>;
	403	#size-cells = <0>;
8d8b43da	404	clocks = <&tegra_car 68>;
a86b0db3 LD	405	status = "disabled";
	406	};
	407
699ed4b9 LD	408	kbc {
	409	compatible = "nvidia,tegra20-kbc";
	410	reg = <0x7000e200 0x100>;
	411	interrupts = <0 85 0x04>;
	412	clocks = <&tegra_car 36>;
	413	status = "disabled";
	414	};
	415
c04abb3a SW	416	pmc {
	417	compatible = "nvidia,tegra20-pmc";
	418	reg = <0x7000e400 0x400>;
	419	};
	420
bbfc33bd	421	memory-controller@7000f000 {
c04abb3a SW	422	compatible = "nvidia,tegra20-mc";
	423	reg = <0x7000f000 0x024
	424	0x7000f03c 0x3c4>;
	425	interrupts = <0 77 0x04>;
	426	};
	427
109269e8	428	iommu {
c04abb3a SW	429	compatible = "nvidia,tegra20-gart";
	430	reg = <0x7000f024 0x00000018 /* controller registers */
	431	0x58000000 0x02000000>; /* GART aperture */
	432	};
	433
bbfc33bd	434	memory-controller@7000f400 {
c04abb3a SW	435	compatible = "nvidia,tegra20-emc";
c04abb3a SW	436	reg = <0x7000f400 0x200>;
2eaab06e SW	437	#address-cells = <1>;
2eaab06e SW	438	#size-cells = <0>;
8e267f3d	439	};
c27317c0	440
e374b65c VB	441	phy1: usb-phy@c5000400 {
	442	compatible = "nvidia,tegra20-usb-phy";
	443	reg = <0xc5000400 0x3c00>;
	444	phy_type = "utmi";
	445	nvidia,has-legacy-mode;
540fc9d9 SW	446	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	447	clock-names = "phy", "pll_u";
e374b65c VB	448	};
	449
	450	phy2: usb-phy@c5004400 {
	451	compatible = "nvidia,tegra20-usb-phy";
	452	reg = <0xc5004400 0x3c00>;
	453	phy_type = "ulpi";
540fc9d9 SW	454	clocks = <&tegra_car 94>, <&tegra_car 127>;
540fc9d9 SW	455	clock-names = "phy", "pll_u";
e374b65c VB	456	};
	457
	458	phy3: usb-phy@c5008400 {
	459	compatible = "nvidia,tegra20-usb-phy";
	460	reg = <0xc5008400 0x3C00>;
	461	phy_type = "utmi";
540fc9d9 SW	462	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	463	clock-names = "phy", "pll_u";
e374b65c VB	464	};
e374b65c VB	465
c27317c0 OJ	466	usb@c5000000 {
	467	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	468	reg = <0xc5000000 0x4000>;
95decf84	469	interrupts = <0 20 0x04>;
c27317c0	470	phy_type = "utmi";
ba202f15	471	nvidia,has-legacy-mode;
8d8b43da	472	clocks = <&tegra_car 22>;
b4e07478	473	nvidia,needs-double-reset;
e374b65c	474	nvidia,phy = <&phy1>;
223ef78d	475	status = "disabled";
c27317c0 OJ	476	};
	477
	478	usb@c5004000 {
	479	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	480	reg = <0xc5004000 0x4000>;
95decf84	481	interrupts = <0 21 0x04>;
c27317c0	482	phy_type = "ulpi";
8d8b43da	483	clocks = <&tegra_car 58>;
e374b65c	484	nvidia,phy = <&phy2>;
223ef78d	485	status = "disabled";
c27317c0 OJ	486	};
	487
	488	usb@c5008000 {
	489	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	490	reg = <0xc5008000 0x4000>;
95decf84	491	interrupts = <0 97 0x04>;
c27317c0	492	phy_type = "utmi";
8d8b43da	493	clocks = <&tegra_car 59>;
e374b65c	494	nvidia,phy = <&phy3>;
223ef78d	495	status = "disabled";
c27317c0	496	};
7868a9bc	497
c04abb3a SW	498	sdhci@c8000000 {
	499	compatible = "nvidia,tegra20-sdhci";
	500	reg = <0xc8000000 0x200>;
	501	interrupts = <0 14 0x04>;
8d8b43da	502	clocks = <&tegra_car 14>;
223ef78d	503	status = "disabled";
7868a9bc	504	};
4a82f2b3	505
c04abb3a SW	506	sdhci@c8000200 {
	507	compatible = "nvidia,tegra20-sdhci";
	508	reg = <0xc8000200 0x200>;
	509	interrupts = <0 15 0x04>;
8d8b43da	510	clocks = <&tegra_car 9>;
223ef78d	511	status = "disabled";
4a82f2b3	512	};
6a943e0e	513
c04abb3a SW	514	sdhci@c8000400 {
	515	compatible = "nvidia,tegra20-sdhci";
	516	reg = <0xc8000400 0x200>;
	517	interrupts = <0 19 0x04>;
8d8b43da	518	clocks = <&tegra_car 69>;
223ef78d	519	status = "disabled";
c04abb3a SW	520	};
	521
	522	sdhci@c8000600 {
	523	compatible = "nvidia,tegra20-sdhci";
	524	reg = <0xc8000600 0x200>;
	525	interrupts = <0 31 0x04>;
8d8b43da	526	clocks = <&tegra_car 15>;
223ef78d	527	status = "disabled";
c04abb3a SW	528	};
c04abb3a SW	529
4dd2bd37 HD	530	cpus {
	531	#address-cells = <1>;
	532	#size-cells = <0>;
	533
	534	cpu@0 {
	535	device_type = "cpu";
	536	compatible = "arm,cortex-a9";
	537	reg = <0>;
	538	};
	539
	540	cpu@1 {
	541	device_type = "cpu";
	542	compatible = "arm,cortex-a9";
	543	reg = <1>;
	544	};
	545	};
	546
c04abb3a SW	547	pmu {
	548	compatible = "arm,cortex-a9-pmu";
	549	interrupts = <0 56 0x04
	550	0 57 0x04>;
6a943e0e	551	};
8e267f3d	552	};