[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
	};

	serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
	};

	serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
	};

	serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
	};

	serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
	};

	serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
	};

	i2c@7000c000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
	};

	i2c@7000c400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
	};

	i2c@7000c500 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
	};

	i2c@7000d000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	mc {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	gart {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	emc {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
f9eb26a4	7	intc: interrupt-controller {
0d4f7479	8	compatible = "arm,cortex-a9-gic";
8e267f3d	9	interrupt-controller;
0d4f7479	10	#interrupt-cells = <3>;
5ff48887 SW	11	reg = <0x50041000 0x1000
5ff48887 SW	12	0x50040100 0x0100>;
8e267f3d GL	13	};
8e267f3d GL	14
f9eb26a4	15	apbdma: dma {
8051b75a SW	16	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	17	reg = <0x6000a000 0x1200>;
95decf84 SW	18	interrupts = <0 104 0x04
	19	0 105 0x04
	20	0 106 0x04
	21	0 107 0x04
	22	0 108 0x04
	23	0 109 0x04
	24	0 110 0x04
	25	0 111 0x04
	26	0 112 0x04
	27	0 113 0x04
	28	0 114 0x04
	29	0 115 0x04
	30	0 116 0x04
	31	0 117 0x04
	32	0 118 0x04
	33	0 119 0x04>;
8051b75a SW	34	};
8051b75a SW	35
c04abb3a SW	36	ahb {
	37	compatible = "nvidia,tegra20-ahb";
	38	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	39	};
8e267f3d GL	40
f9eb26a4	41	gpio: gpio {
8e267f3d	42	compatible = "nvidia,tegra20-gpio";
95decf84 SW	43	reg = <0x6000d000 0x1000>;
	44	interrupts = <0 32 0x04
	45	0 33 0x04
	46	0 34 0x04
	47	0 35 0x04
	48	0 55 0x04
	49	0 87 0x04
	50	0 89 0x04>;
8e267f3d GL	51	#gpio-cells = <2>;
8e267f3d GL	52	gpio-controller;
6f74dc9b SW	53	#interrupt-cells = <2>;
6f74dc9b SW	54	interrupt-controller;
8e267f3d GL	55	};
8e267f3d GL	56
f9eb26a4	57	pinmux: pinmux {
f62f548c	58	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	59	reg = <0x70000014 0x10 /* Tri-state registers */
	60	0x70000080 0x20 /* Mux registers */
	61	0x700000a0 0x14 /* Pull-up/down registers */
	62	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	63	};
f62f548c SW	64
c04abb3a SW	65	das {
	66	compatible = "nvidia,tegra20-das";
	67	reg = <0x70000c00 0x80>;
	68	};
	69
	70	tegra_i2s1: i2s@70002800 {
	71	compatible = "nvidia,tegra20-i2s";
	72	reg = <0x70002800 0x200>;
	73	interrupts = <0 13 0x04>;
	74	nvidia,dma-request-selector = <&apbdma 2>;
	75	};
	76
	77	tegra_i2s2: i2s@70002a00 {
	78	compatible = "nvidia,tegra20-i2s";
	79	reg = <0x70002a00 0x200>;
	80	interrupts = <0 3 0x04>;
	81	nvidia,dma-request-selector = <&apbdma 1>;
	82	};
	83
8e267f3d GL	84	serial@70006000 {
	85	compatible = "nvidia,tegra20-uart";
	86	reg = <0x70006000 0x40>;
	87	reg-shift = <2>;
95decf84	88	interrupts = <0 36 0x04>;
8e267f3d GL	89	};
	90
	91	serial@70006040 {
	92	compatible = "nvidia,tegra20-uart";
	93	reg = <0x70006040 0x40>;
	94	reg-shift = <2>;
95decf84	95	interrupts = <0 37 0x04>;
8e267f3d GL	96	};
	97
	98	serial@70006200 {
	99	compatible = "nvidia,tegra20-uart";
	100	reg = <0x70006200 0x100>;
	101	reg-shift = <2>;
95decf84	102	interrupts = <0 46 0x04>;
8e267f3d GL	103	};
	104
	105	serial@70006300 {
	106	compatible = "nvidia,tegra20-uart";
	107	reg = <0x70006300 0x100>;
	108	reg-shift = <2>;
95decf84	109	interrupts = <0 90 0x04>;
8e267f3d GL	110	};
	111
	112	serial@70006400 {
	113	compatible = "nvidia,tegra20-uart";
	114	reg = <0x70006400 0x100>;
	115	reg-shift = <2>;
95decf84	116	interrupts = <0 91 0x04>;
8e267f3d GL	117	};
8e267f3d GL	118
c04abb3a	119	i2c@7000c000 {
0c6700ab OJ	120	#address-cells = <1>;
0c6700ab OJ	121	#size-cells = <0>;
c04abb3a SW	122	compatible = "nvidia,tegra20-i2c";
	123	reg = <0x7000c000 0x100>;
	124	interrupts = <0 38 0x04>;
0c6700ab OJ	125	};
0c6700ab OJ	126
c04abb3a SW	127	i2c@7000c400 {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	compatible = "nvidia,tegra20-i2c";
	131	reg = <0x7000c400 0x100>;
	132	interrupts = <0 84 0x04>;
8e267f3d GL	133	};
8e267f3d GL	134
c04abb3a SW	135	i2c@7000c500 {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	compatible = "nvidia,tegra20-i2c";
	139	reg = <0x7000c500 0x100>;
	140	interrupts = <0 92 0x04>;
8e267f3d GL	141	};
8e267f3d GL	142
c04abb3a SW	143	i2c@7000d000 {
	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146	compatible = "nvidia,tegra20-i2c-dvc";
	147	reg = <0x7000d000 0x200>;
	148	interrupts = <0 53 0x04>;
8e267f3d GL	149	};
8e267f3d GL	150
c04abb3a SW	151	pmc {
	152	compatible = "nvidia,tegra20-pmc";
	153	reg = <0x7000e400 0x400>;
	154	};
	155
	156	mc {
	157	compatible = "nvidia,tegra20-mc";
	158	reg = <0x7000f000 0x024
	159	0x7000f03c 0x3c4>;
	160	interrupts = <0 77 0x04>;
	161	};
	162
	163	gart {
	164	compatible = "nvidia,tegra20-gart";
	165	reg = <0x7000f024 0x00000018 /* controller registers */
	166	0x58000000 0x02000000>; /* GART aperture */
	167	};
	168
	169	emc {
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172	compatible = "nvidia,tegra20-emc";
	173	reg = <0x7000f400 0x200>;
8e267f3d	174	};
c27317c0 OJ	175
	176	usb@c5000000 {
	177	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	178	reg = <0xc5000000 0x4000>;
95decf84	179	interrupts = <0 20 0x04>;
c27317c0	180	phy_type = "utmi";
ba202f15	181	nvidia,has-legacy-mode;
c27317c0 OJ	182	};
	183
	184	usb@c5004000 {
	185	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	186	reg = <0xc5004000 0x4000>;
95decf84	187	interrupts = <0 21 0x04>;
c27317c0 OJ	188	phy_type = "ulpi";
	189	};
	190
	191	usb@c5008000 {
	192	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	193	reg = <0xc5008000 0x4000>;
95decf84	194	interrupts = <0 97 0x04>;
c27317c0 OJ	195	phy_type = "utmi";
c27317c0 OJ	196	};
7868a9bc	197
c04abb3a SW	198	sdhci@c8000000 {
	199	compatible = "nvidia,tegra20-sdhci";
	200	reg = <0xc8000000 0x200>;
	201	interrupts = <0 14 0x04>;
7868a9bc	202	};
4a82f2b3	203
c04abb3a SW	204	sdhci@c8000200 {
	205	compatible = "nvidia,tegra20-sdhci";
	206	reg = <0xc8000200 0x200>;
	207	interrupts = <0 15 0x04>;
4a82f2b3	208	};
6a943e0e	209
c04abb3a SW	210	sdhci@c8000400 {
	211	compatible = "nvidia,tegra20-sdhci";
	212	reg = <0xc8000400 0x200>;
	213	interrupts = <0 19 0x04>;
	214	};
	215
	216	sdhci@c8000600 {
	217	compatible = "nvidia,tegra20-sdhci";
	218	reg = <0xc8000600 0x200>;
	219	interrupts = <0 31 0x04>;
	220	};
	221
	222	pmu {
	223	compatible = "arm,cortex-a9-pmu";
	224	interrupts = <0 56 0x04
	225	0 57 0x04>;
6a943e0e	226	};
8e267f3d	227	};