[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
	};

	cache-controller@50043000 {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	gart {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	phy1: usb-phy@c5000400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000400 0x3c00>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy2: usb-phy@c5004400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004400 0x3c00>;
		phy_type = "ulpi";
		clocks = <&tegra_car 94>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy3: usb-phy@c5008400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008400 0x3C00>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
b6551bb9 LD	7	aliases {
	8	serial0 = &uarta;
	9	serial1 = &uartb;
	10	serial2 = &uartc;
	11	serial3 = &uartd;
	12	serial4 = &uarte;
	13	};
	14
ed821f07 TR	15	host1x {
	16	compatible = "nvidia,tegra20-host1x", "simple-bus";
	17	reg = <0x50000000 0x00024000>;
	18	interrupts = <0 65 0x04 /* mpcore syncpt */
	19	0 67 0x04>; /* mpcore general */
8d8b43da	20	clocks = <&tegra_car 28>;
ed821f07 TR	21
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	ranges = <0x54000000 0x54000000 0x04000000>;
	26
	27	mpe {
	28	compatible = "nvidia,tegra20-mpe";
	29	reg = <0x54040000 0x00040000>;
	30	interrupts = <0 68 0x04>;
8d8b43da	31	clocks = <&tegra_car 60>;
ed821f07 TR	32	};
	33
	34	vi {
	35	compatible = "nvidia,tegra20-vi";
	36	reg = <0x54080000 0x00040000>;
	37	interrupts = <0 69 0x04>;
8d8b43da	38	clocks = <&tegra_car 100>;
ed821f07 TR	39	};
	40
	41	epp {
	42	compatible = "nvidia,tegra20-epp";
	43	reg = <0x540c0000 0x00040000>;
	44	interrupts = <0 70 0x04>;
8d8b43da	45	clocks = <&tegra_car 19>;
ed821f07 TR	46	};
	47
	48	isp {
	49	compatible = "nvidia,tegra20-isp";
	50	reg = <0x54100000 0x00040000>;
	51	interrupts = <0 71 0x04>;
8d8b43da	52	clocks = <&tegra_car 23>;
ed821f07 TR	53	};
	54
	55	gr2d {
	56	compatible = "nvidia,tegra20-gr2d";
	57	reg = <0x54140000 0x00040000>;
	58	interrupts = <0 72 0x04>;
8d8b43da	59	clocks = <&tegra_car 21>;
ed821f07 TR	60	};
	61
	62	gr3d {
	63	compatible = "nvidia,tegra20-gr3d";
	64	reg = <0x54180000 0x00040000>;
8d8b43da	65	clocks = <&tegra_car 24>;
ed821f07 TR	66	};
	67
	68	dc@54200000 {
	69	compatible = "nvidia,tegra20-dc";
	70	reg = <0x54200000 0x00040000>;
	71	interrupts = <0 73 0x04>;
8d8b43da PG	72	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	73	clock-names = "disp1", "parent";
ed821f07 TR	74
	75	rgb {
	76	status = "disabled";
	77	};
	78	};
	79
	80	dc@54240000 {
	81	compatible = "nvidia,tegra20-dc";
	82	reg = <0x54240000 0x00040000>;
	83	interrupts = <0 74 0x04>;
8d8b43da PG	84	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	85	clock-names = "disp2", "parent";
ed821f07 TR	86
	87	rgb {
	88	status = "disabled";
	89	};
	90	};
	91
	92	hdmi {
	93	compatible = "nvidia,tegra20-hdmi";
	94	reg = <0x54280000 0x00040000>;
	95	interrupts = <0 75 0x04>;
8d8b43da PG	96	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	97	clock-names = "hdmi", "parent";
ed821f07 TR	98	status = "disabled";
	99	};
	100
	101	tvo {
	102	compatible = "nvidia,tegra20-tvo";
	103	reg = <0x542c0000 0x00040000>;
	104	interrupts = <0 76 0x04>;
8d8b43da	105	clocks = <&tegra_car 102>;
ed821f07 TR	106	status = "disabled";
	107	};
	108
	109	dsi {
	110	compatible = "nvidia,tegra20-dsi";
	111	reg = <0x54300000 0x00040000>;
8d8b43da	112	clocks = <&tegra_car 48>;
ed821f07 TR	113	status = "disabled";
	114	};
	115	};
	116
73368ba0 SW	117	timer@50004600 {
	118	compatible = "arm,cortex-a9-twd-timer";
	119	reg = <0x50040600 0x20>;
	120	interrupts = <1 13 0x304>;
	121	};
	122
5ab134ad JL	123	cache-controller@50043000 {
	124	compatible = "arm,pl310-cache";
	125	reg = <0x50043000 0x1000>;
	126	arm,data-latency = <5 5 2>;
	127	arm,tag-latency = <4 4 2>;
	128	cache-unified;
	129	cache-level = <2>;
	130	};
	131
f9eb26a4	132	intc: interrupt-controller {
0d4f7479	133	compatible = "arm,cortex-a9-gic";
5ff48887 SW	134	reg = <0x50041000 0x1000
5ff48887 SW	135	0x50040100 0x0100>;
2eaab06e SW	136	interrupt-controller;
2eaab06e SW	137	#interrupt-cells = <3>;
8e267f3d GL	138	};
8e267f3d GL	139
2f2b7fb2 SW	140	timer@60005000 {
	141	compatible = "nvidia,tegra20-timer";
	142	reg = <0x60005000 0x60>;
	143	interrupts = <0 0 0x04
	144	0 1 0x04
	145	0 41 0x04
	146	0 42 0x04>;
	147	};
	148
270f8ce3 SW	149	tegra_car: clock {
	150	compatible = "nvidia,tegra20-car";
	151	reg = <0x60006000 0x1000>;
	152	#clock-cells = <1>;
	153	};
	154
f9eb26a4	155	apbdma: dma {
8051b75a SW	156	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	157	reg = <0x6000a000 0x1200>;
95decf84 SW	158	interrupts = <0 104 0x04
	159	0 105 0x04
	160	0 106 0x04
	161	0 107 0x04
	162	0 108 0x04
	163	0 109 0x04
	164	0 110 0x04
	165	0 111 0x04
	166	0 112 0x04
	167	0 113 0x04
	168	0 114 0x04
	169	0 115 0x04
	170	0 116 0x04
	171	0 117 0x04
	172	0 118 0x04
	173	0 119 0x04>;
8d8b43da	174	clocks = <&tegra_car 34>;
8051b75a SW	175	};
8051b75a SW	176
c04abb3a SW	177	ahb {
	178	compatible = "nvidia,tegra20-ahb";
	179	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	180	};
8e267f3d GL	181
f9eb26a4	182	gpio: gpio {
8e267f3d	183	compatible = "nvidia,tegra20-gpio";
95decf84 SW	184	reg = <0x6000d000 0x1000>;
	185	interrupts = <0 32 0x04
	186	0 33 0x04
	187	0 34 0x04
	188	0 35 0x04
	189	0 55 0x04
	190	0 87 0x04
	191	0 89 0x04>;
8e267f3d GL	192	#gpio-cells = <2>;
8e267f3d GL	193	gpio-controller;
6f74dc9b SW	194	#interrupt-cells = <2>;
6f74dc9b SW	195	interrupt-controller;
8e267f3d GL	196	};
8e267f3d GL	197
f9eb26a4	198	pinmux: pinmux {
f62f548c	199	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	200	reg = <0x70000014 0x10 /* Tri-state registers */
	201	0x70000080 0x20 /* Mux registers */
	202	0x700000a0 0x14 /* Pull-up/down registers */
	203	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	204	};
f62f548c SW	205
c04abb3a SW	206	das {
	207	compatible = "nvidia,tegra20-das";
	208	reg = <0x70000c00 0x80>;
	209	};
	210
	211	tegra_i2s1: i2s@70002800 {
	212	compatible = "nvidia,tegra20-i2s";
	213	reg = <0x70002800 0x200>;
	214	interrupts = <0 13 0x04>;
	215	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	216	clocks = <&tegra_car 11>;
223ef78d	217	status = "disabled";
c04abb3a SW	218	};
	219
	220	tegra_i2s2: i2s@70002a00 {
	221	compatible = "nvidia,tegra20-i2s";
	222	reg = <0x70002a00 0x200>;
	223	interrupts = <0 3 0x04>;
	224	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	225	clocks = <&tegra_car 18>;
223ef78d	226	status = "disabled";
c04abb3a SW	227	};
c04abb3a SW	228
b6551bb9 LD	229	/*
	230	* There are two serial driver i.e. 8250 based simple serial
	231	* driver and APB DMA based serial driver for higher baudrate
	232	* and performace. To enable the 8250 based driver, the compatible
	233	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	234	* driver, the comptible is "nvidia,tegra20-hsuart".
	235	*/
	236	uarta: serial@70006000 {
8e267f3d GL	237	compatible = "nvidia,tegra20-uart";
	238	reg = <0x70006000 0x40>;
	239	reg-shift = <2>;
95decf84	240	interrupts = <0 36 0x04>;
b6551bb9	241	nvidia,dma-request-selector = <&apbdma 8>;
8d8b43da	242	clocks = <&tegra_car 6>;
223ef78d	243	status = "disabled";
8e267f3d GL	244	};
8e267f3d GL	245
b6551bb9	246	uartb: serial@70006040 {
8e267f3d GL	247	compatible = "nvidia,tegra20-uart";
	248	reg = <0x70006040 0x40>;
	249	reg-shift = <2>;
95decf84	250	interrupts = <0 37 0x04>;
b6551bb9	251	nvidia,dma-request-selector = <&apbdma 9>;
8d8b43da	252	clocks = <&tegra_car 96>;
223ef78d	253	status = "disabled";
8e267f3d GL	254	};
8e267f3d GL	255
b6551bb9	256	uartc: serial@70006200 {
8e267f3d GL	257	compatible = "nvidia,tegra20-uart";
	258	reg = <0x70006200 0x100>;
	259	reg-shift = <2>;
95decf84	260	interrupts = <0 46 0x04>;
b6551bb9	261	nvidia,dma-request-selector = <&apbdma 10>;
8d8b43da	262	clocks = <&tegra_car 55>;
223ef78d	263	status = "disabled";
8e267f3d GL	264	};
8e267f3d GL	265
b6551bb9	266	uartd: serial@70006300 {
8e267f3d GL	267	compatible = "nvidia,tegra20-uart";
	268	reg = <0x70006300 0x100>;
	269	reg-shift = <2>;
95decf84	270	interrupts = <0 90 0x04>;
b6551bb9	271	nvidia,dma-request-selector = <&apbdma 19>;
8d8b43da	272	clocks = <&tegra_car 65>;
223ef78d	273	status = "disabled";
8e267f3d GL	274	};
8e267f3d GL	275
b6551bb9	276	uarte: serial@70006400 {
8e267f3d GL	277	compatible = "nvidia,tegra20-uart";
	278	reg = <0x70006400 0x100>;
	279	reg-shift = <2>;
95decf84	280	interrupts = <0 91 0x04>;
b6551bb9	281	nvidia,dma-request-selector = <&apbdma 20>;
8d8b43da	282	clocks = <&tegra_car 66>;
223ef78d	283	status = "disabled";
8e267f3d GL	284	};
8e267f3d GL	285
2b8b15da	286	pwm: pwm {
140fd977 TR	287	compatible = "nvidia,tegra20-pwm";
	288	reg = <0x7000a000 0x100>;
	289	#pwm-cells = <2>;
8d8b43da	290	clocks = <&tegra_car 17>;
140fd977 TR	291	};
140fd977 TR	292
380e04ac SW	293	rtc {
	294	compatible = "nvidia,tegra20-rtc";
	295	reg = <0x7000e000 0x100>;
	296	interrupts = <0 2 0x04>;
	297	};
	298
c04abb3a	299	i2c@7000c000 {
c04abb3a SW	300	compatible = "nvidia,tegra20-i2c";
	301	reg = <0x7000c000 0x100>;
	302	interrupts = <0 38 0x04>;
2eaab06e SW	303	#address-cells = <1>;
2eaab06e SW	304	#size-cells = <0>;
8d8b43da PG	305	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	306	clock-names = "div-clk", "fast-clk";
223ef78d	307	status = "disabled";
0c6700ab OJ	308	};
0c6700ab OJ	309
fa98a114 LD	310	spi@7000c380 {
	311	compatible = "nvidia,tegra20-sflash";
	312	reg = <0x7000c380 0x80>;
	313	interrupts = <0 39 0x04>;
	314	nvidia,dma-request-selector = <&apbdma 11>;
	315	#address-cells = <1>;
	316	#size-cells = <0>;
8d8b43da	317	clocks = <&tegra_car 43>;
fa98a114 LD	318	status = "disabled";
	319	};
	320
c04abb3a	321	i2c@7000c400 {
c04abb3a SW	322	compatible = "nvidia,tegra20-i2c";
	323	reg = <0x7000c400 0x100>;
	324	interrupts = <0 84 0x04>;
2eaab06e SW	325	#address-cells = <1>;
2eaab06e SW	326	#size-cells = <0>;
8d8b43da PG	327	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	328	clock-names = "div-clk", "fast-clk";
223ef78d	329	status = "disabled";
8e267f3d GL	330	};
8e267f3d GL	331
c04abb3a	332	i2c@7000c500 {
c04abb3a SW	333	compatible = "nvidia,tegra20-i2c";
	334	reg = <0x7000c500 0x100>;
	335	interrupts = <0 92 0x04>;
2eaab06e SW	336	#address-cells = <1>;
2eaab06e SW	337	#size-cells = <0>;
8d8b43da PG	338	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	339	clock-names = "div-clk", "fast-clk";
223ef78d	340	status = "disabled";
8e267f3d GL	341	};
8e267f3d GL	342
c04abb3a	343	i2c@7000d000 {
c04abb3a SW	344	compatible = "nvidia,tegra20-i2c-dvc";
	345	reg = <0x7000d000 0x200>;
	346	interrupts = <0 53 0x04>;
2eaab06e SW	347	#address-cells = <1>;
2eaab06e SW	348	#size-cells = <0>;
8d8b43da PG	349	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	350	clock-names = "div-clk", "fast-clk";
223ef78d	351	status = "disabled";
8e267f3d GL	352	};
8e267f3d GL	353
a86b0db3 LD	354	spi@7000d400 {
	355	compatible = "nvidia,tegra20-slink";
	356	reg = <0x7000d400 0x200>;
	357	interrupts = <0 59 0x04>;
	358	nvidia,dma-request-selector = <&apbdma 15>;
	359	#address-cells = <1>;
	360	#size-cells = <0>;
8d8b43da	361	clocks = <&tegra_car 41>;
a86b0db3 LD	362	status = "disabled";
	363	};
	364
	365	spi@7000d600 {
	366	compatible = "nvidia,tegra20-slink";
	367	reg = <0x7000d600 0x200>;
	368	interrupts = <0 82 0x04>;
	369	nvidia,dma-request-selector = <&apbdma 16>;
	370	#address-cells = <1>;
	371	#size-cells = <0>;
8d8b43da	372	clocks = <&tegra_car 44>;
a86b0db3 LD	373	status = "disabled";
	374	};
	375
	376	spi@7000d800 {
	377	compatible = "nvidia,tegra20-slink";
	378	reg = <0x7000d480 0x200>;
	379	interrupts = <0 83 0x04>;
	380	nvidia,dma-request-selector = <&apbdma 17>;
	381	#address-cells = <1>;
	382	#size-cells = <0>;
8d8b43da	383	clocks = <&tegra_car 46>;
a86b0db3 LD	384	status = "disabled";
	385	};
	386
	387	spi@7000da00 {
	388	compatible = "nvidia,tegra20-slink";
	389	reg = <0x7000da00 0x200>;
	390	interrupts = <0 93 0x04>;
	391	nvidia,dma-request-selector = <&apbdma 18>;
	392	#address-cells = <1>;
	393	#size-cells = <0>;
8d8b43da	394	clocks = <&tegra_car 68>;
a86b0db3 LD	395	status = "disabled";
	396	};
	397
c04abb3a SW	398	pmc {
	399	compatible = "nvidia,tegra20-pmc";
	400	reg = <0x7000e400 0x400>;
	401	};
	402
bbfc33bd	403	memory-controller@7000f000 {
c04abb3a SW	404	compatible = "nvidia,tegra20-mc";
	405	reg = <0x7000f000 0x024
	406	0x7000f03c 0x3c4>;
	407	interrupts = <0 77 0x04>;
	408	};
	409
	410	gart {
	411	compatible = "nvidia,tegra20-gart";
	412	reg = <0x7000f024 0x00000018 /* controller registers */
	413	0x58000000 0x02000000>; /* GART aperture */
	414	};
	415
bbfc33bd	416	memory-controller@7000f400 {
c04abb3a SW	417	compatible = "nvidia,tegra20-emc";
c04abb3a SW	418	reg = <0x7000f400 0x200>;
2eaab06e SW	419	#address-cells = <1>;
2eaab06e SW	420	#size-cells = <0>;
8e267f3d	421	};
c27317c0	422
e374b65c VB	423	phy1: usb-phy@c5000400 {
	424	compatible = "nvidia,tegra20-usb-phy";
	425	reg = <0xc5000400 0x3c00>;
	426	phy_type = "utmi";
	427	nvidia,has-legacy-mode;
540fc9d9 SW	428	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	429	clock-names = "phy", "pll_u";
e374b65c VB	430	};
	431
	432	phy2: usb-phy@c5004400 {
	433	compatible = "nvidia,tegra20-usb-phy";
	434	reg = <0xc5004400 0x3c00>;
	435	phy_type = "ulpi";
540fc9d9 SW	436	clocks = <&tegra_car 94>, <&tegra_car 127>;
540fc9d9 SW	437	clock-names = "phy", "pll_u";
e374b65c VB	438	};
	439
	440	phy3: usb-phy@c5008400 {
	441	compatible = "nvidia,tegra20-usb-phy";
	442	reg = <0xc5008400 0x3C00>;
	443	phy_type = "utmi";
540fc9d9 SW	444	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	445	clock-names = "phy", "pll_u";
e374b65c VB	446	};
e374b65c VB	447
c27317c0 OJ	448	usb@c5000000 {
	449	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	450	reg = <0xc5000000 0x4000>;
95decf84	451	interrupts = <0 20 0x04>;
c27317c0	452	phy_type = "utmi";
ba202f15	453	nvidia,has-legacy-mode;
8d8b43da	454	clocks = <&tegra_car 22>;
b4e07478	455	nvidia,needs-double-reset;
e374b65c	456	nvidia,phy = <&phy1>;
223ef78d	457	status = "disabled";
c27317c0 OJ	458	};
	459
	460	usb@c5004000 {
	461	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	462	reg = <0xc5004000 0x4000>;
95decf84	463	interrupts = <0 21 0x04>;
c27317c0	464	phy_type = "ulpi";
8d8b43da	465	clocks = <&tegra_car 58>;
e374b65c	466	nvidia,phy = <&phy2>;
223ef78d	467	status = "disabled";
c27317c0 OJ	468	};
	469
	470	usb@c5008000 {
	471	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	472	reg = <0xc5008000 0x4000>;
95decf84	473	interrupts = <0 97 0x04>;
c27317c0	474	phy_type = "utmi";
8d8b43da	475	clocks = <&tegra_car 59>;
e374b65c	476	nvidia,phy = <&phy3>;
223ef78d	477	status = "disabled";
c27317c0	478	};
7868a9bc	479
c04abb3a SW	480	sdhci@c8000000 {
	481	compatible = "nvidia,tegra20-sdhci";
	482	reg = <0xc8000000 0x200>;
	483	interrupts = <0 14 0x04>;
8d8b43da	484	clocks = <&tegra_car 14>;
223ef78d	485	status = "disabled";
7868a9bc	486	};
4a82f2b3	487
c04abb3a SW	488	sdhci@c8000200 {
	489	compatible = "nvidia,tegra20-sdhci";
	490	reg = <0xc8000200 0x200>;
	491	interrupts = <0 15 0x04>;
8d8b43da	492	clocks = <&tegra_car 9>;
223ef78d	493	status = "disabled";
4a82f2b3	494	};
6a943e0e	495
c04abb3a SW	496	sdhci@c8000400 {
	497	compatible = "nvidia,tegra20-sdhci";
	498	reg = <0xc8000400 0x200>;
	499	interrupts = <0 19 0x04>;
8d8b43da	500	clocks = <&tegra_car 69>;
223ef78d	501	status = "disabled";
c04abb3a SW	502	};
	503
	504	sdhci@c8000600 {
	505	compatible = "nvidia,tegra20-sdhci";
	506	reg = <0xc8000600 0x200>;
	507	interrupts = <0 31 0x04>;
8d8b43da	508	clocks = <&tegra_car 15>;
223ef78d	509	status = "disabled";
c04abb3a SW	510	};
c04abb3a SW	511
4dd2bd37 HD	512	cpus {
	513	#address-cells = <1>;
	514	#size-cells = <0>;
	515
	516	cpu@0 {
	517	device_type = "cpu";
	518	compatible = "arm,cortex-a9";
	519	reg = <0>;
	520	};
	521
	522	cpu@1 {
	523	device_type = "cpu";
	524	compatible = "arm,cortex-a9";
	525	reg = <1>;
	526	};
	527	};
	528
c04abb3a SW	529	pmu {
	530	compatible = "arm,cortex-a9-pmu";
	531	interrupts = <0 56 0x04
	532	0 57 0x04>;
6a943e0e	533	};
8e267f3d	534	};