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Commit | Line | Data |
---|---|---|
8e267f3d GL |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
4 | compatible = "nvidia,tegra20"; | |
5 | interrupt-parent = <&intc>; | |
6 | ||
f9eb26a4 | 7 | intc: interrupt-controller { |
0d4f7479 | 8 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
9 | reg = <0x50041000 0x1000 |
10 | 0x50040100 0x0100>; | |
2eaab06e SW |
11 | interrupt-controller; |
12 | #interrupt-cells = <3>; | |
8e267f3d GL |
13 | }; |
14 | ||
f9eb26a4 | 15 | apbdma: dma { |
8051b75a SW |
16 | compatible = "nvidia,tegra20-apbdma"; |
17 | reg = <0x6000a000 0x1200>; | |
95decf84 SW |
18 | interrupts = <0 104 0x04 |
19 | 0 105 0x04 | |
20 | 0 106 0x04 | |
21 | 0 107 0x04 | |
22 | 0 108 0x04 | |
23 | 0 109 0x04 | |
24 | 0 110 0x04 | |
25 | 0 111 0x04 | |
26 | 0 112 0x04 | |
27 | 0 113 0x04 | |
28 | 0 114 0x04 | |
29 | 0 115 0x04 | |
30 | 0 116 0x04 | |
31 | 0 117 0x04 | |
32 | 0 118 0x04 | |
33 | 0 119 0x04>; | |
8051b75a SW |
34 | }; |
35 | ||
c04abb3a SW |
36 | ahb { |
37 | compatible = "nvidia,tegra20-ahb"; | |
38 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | |
8e267f3d GL |
39 | }; |
40 | ||
f9eb26a4 | 41 | gpio: gpio { |
8e267f3d | 42 | compatible = "nvidia,tegra20-gpio"; |
95decf84 SW |
43 | reg = <0x6000d000 0x1000>; |
44 | interrupts = <0 32 0x04 | |
45 | 0 33 0x04 | |
46 | 0 34 0x04 | |
47 | 0 35 0x04 | |
48 | 0 55 0x04 | |
49 | 0 87 0x04 | |
50 | 0 89 0x04>; | |
8e267f3d GL |
51 | #gpio-cells = <2>; |
52 | gpio-controller; | |
6f74dc9b SW |
53 | #interrupt-cells = <2>; |
54 | interrupt-controller; | |
8e267f3d GL |
55 | }; |
56 | ||
f9eb26a4 | 57 | pinmux: pinmux { |
f62f548c | 58 | compatible = "nvidia,tegra20-pinmux"; |
95decf84 SW |
59 | reg = <0x70000014 0x10 /* Tri-state registers */ |
60 | 0x70000080 0x20 /* Mux registers */ | |
61 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
62 | 0x70000868 0xa8>; /* Pad control registers */ | |
f62f548c SW |
63 | }; |
64 | ||
c04abb3a SW |
65 | das { |
66 | compatible = "nvidia,tegra20-das"; | |
67 | reg = <0x70000c00 0x80>; | |
68 | }; | |
69 | ||
70 | tegra_i2s1: i2s@70002800 { | |
71 | compatible = "nvidia,tegra20-i2s"; | |
72 | reg = <0x70002800 0x200>; | |
73 | interrupts = <0 13 0x04>; | |
74 | nvidia,dma-request-selector = <&apbdma 2>; | |
2a5fdc9a | 75 | status = "disable"; |
c04abb3a SW |
76 | }; |
77 | ||
78 | tegra_i2s2: i2s@70002a00 { | |
79 | compatible = "nvidia,tegra20-i2s"; | |
80 | reg = <0x70002a00 0x200>; | |
81 | interrupts = <0 3 0x04>; | |
82 | nvidia,dma-request-selector = <&apbdma 1>; | |
2a5fdc9a | 83 | status = "disable"; |
c04abb3a SW |
84 | }; |
85 | ||
8e267f3d GL |
86 | serial@70006000 { |
87 | compatible = "nvidia,tegra20-uart"; | |
88 | reg = <0x70006000 0x40>; | |
89 | reg-shift = <2>; | |
95decf84 | 90 | interrupts = <0 36 0x04>; |
2a5fdc9a | 91 | status = "disable"; |
8e267f3d GL |
92 | }; |
93 | ||
94 | serial@70006040 { | |
95 | compatible = "nvidia,tegra20-uart"; | |
96 | reg = <0x70006040 0x40>; | |
97 | reg-shift = <2>; | |
95decf84 | 98 | interrupts = <0 37 0x04>; |
2a5fdc9a | 99 | status = "disable"; |
8e267f3d GL |
100 | }; |
101 | ||
102 | serial@70006200 { | |
103 | compatible = "nvidia,tegra20-uart"; | |
104 | reg = <0x70006200 0x100>; | |
105 | reg-shift = <2>; | |
95decf84 | 106 | interrupts = <0 46 0x04>; |
2a5fdc9a | 107 | status = "disable"; |
8e267f3d GL |
108 | }; |
109 | ||
110 | serial@70006300 { | |
111 | compatible = "nvidia,tegra20-uart"; | |
112 | reg = <0x70006300 0x100>; | |
113 | reg-shift = <2>; | |
95decf84 | 114 | interrupts = <0 90 0x04>; |
2a5fdc9a | 115 | status = "disable"; |
8e267f3d GL |
116 | }; |
117 | ||
118 | serial@70006400 { | |
119 | compatible = "nvidia,tegra20-uart"; | |
120 | reg = <0x70006400 0x100>; | |
121 | reg-shift = <2>; | |
95decf84 | 122 | interrupts = <0 91 0x04>; |
2a5fdc9a | 123 | status = "disable"; |
8e267f3d GL |
124 | }; |
125 | ||
c04abb3a | 126 | i2c@7000c000 { |
c04abb3a SW |
127 | compatible = "nvidia,tegra20-i2c"; |
128 | reg = <0x7000c000 0x100>; | |
129 | interrupts = <0 38 0x04>; | |
2eaab06e SW |
130 | #address-cells = <1>; |
131 | #size-cells = <0>; | |
2a5fdc9a | 132 | status = "disable"; |
0c6700ab OJ |
133 | }; |
134 | ||
c04abb3a | 135 | i2c@7000c400 { |
c04abb3a SW |
136 | compatible = "nvidia,tegra20-i2c"; |
137 | reg = <0x7000c400 0x100>; | |
138 | interrupts = <0 84 0x04>; | |
2eaab06e SW |
139 | #address-cells = <1>; |
140 | #size-cells = <0>; | |
2a5fdc9a | 141 | status = "disable"; |
8e267f3d GL |
142 | }; |
143 | ||
c04abb3a | 144 | i2c@7000c500 { |
c04abb3a SW |
145 | compatible = "nvidia,tegra20-i2c"; |
146 | reg = <0x7000c500 0x100>; | |
147 | interrupts = <0 92 0x04>; | |
2eaab06e SW |
148 | #address-cells = <1>; |
149 | #size-cells = <0>; | |
2a5fdc9a | 150 | status = "disable"; |
8e267f3d GL |
151 | }; |
152 | ||
c04abb3a | 153 | i2c@7000d000 { |
c04abb3a SW |
154 | compatible = "nvidia,tegra20-i2c-dvc"; |
155 | reg = <0x7000d000 0x200>; | |
156 | interrupts = <0 53 0x04>; | |
2eaab06e SW |
157 | #address-cells = <1>; |
158 | #size-cells = <0>; | |
2a5fdc9a | 159 | status = "disable"; |
8e267f3d GL |
160 | }; |
161 | ||
c04abb3a SW |
162 | pmc { |
163 | compatible = "nvidia,tegra20-pmc"; | |
164 | reg = <0x7000e400 0x400>; | |
165 | }; | |
166 | ||
167 | mc { | |
168 | compatible = "nvidia,tegra20-mc"; | |
169 | reg = <0x7000f000 0x024 | |
170 | 0x7000f03c 0x3c4>; | |
171 | interrupts = <0 77 0x04>; | |
172 | }; | |
173 | ||
174 | gart { | |
175 | compatible = "nvidia,tegra20-gart"; | |
176 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
177 | 0x58000000 0x02000000>; /* GART aperture */ | |
178 | }; | |
179 | ||
180 | emc { | |
c04abb3a SW |
181 | compatible = "nvidia,tegra20-emc"; |
182 | reg = <0x7000f400 0x200>; | |
2eaab06e SW |
183 | #address-cells = <1>; |
184 | #size-cells = <0>; | |
8e267f3d | 185 | }; |
c27317c0 OJ |
186 | |
187 | usb@c5000000 { | |
188 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
189 | reg = <0xc5000000 0x4000>; | |
95decf84 | 190 | interrupts = <0 20 0x04>; |
c27317c0 | 191 | phy_type = "utmi"; |
ba202f15 | 192 | nvidia,has-legacy-mode; |
2a5fdc9a | 193 | status = "disable"; |
c27317c0 OJ |
194 | }; |
195 | ||
196 | usb@c5004000 { | |
197 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
198 | reg = <0xc5004000 0x4000>; | |
95decf84 | 199 | interrupts = <0 21 0x04>; |
c27317c0 | 200 | phy_type = "ulpi"; |
2a5fdc9a | 201 | status = "disable"; |
c27317c0 OJ |
202 | }; |
203 | ||
204 | usb@c5008000 { | |
205 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
206 | reg = <0xc5008000 0x4000>; | |
95decf84 | 207 | interrupts = <0 97 0x04>; |
c27317c0 | 208 | phy_type = "utmi"; |
2a5fdc9a | 209 | status = "disable"; |
c27317c0 | 210 | }; |
7868a9bc | 211 | |
c04abb3a SW |
212 | sdhci@c8000000 { |
213 | compatible = "nvidia,tegra20-sdhci"; | |
214 | reg = <0xc8000000 0x200>; | |
215 | interrupts = <0 14 0x04>; | |
2a5fdc9a | 216 | status = "disable"; |
7868a9bc | 217 | }; |
4a82f2b3 | 218 | |
c04abb3a SW |
219 | sdhci@c8000200 { |
220 | compatible = "nvidia,tegra20-sdhci"; | |
221 | reg = <0xc8000200 0x200>; | |
222 | interrupts = <0 15 0x04>; | |
2a5fdc9a | 223 | status = "disable"; |
4a82f2b3 | 224 | }; |
6a943e0e | 225 | |
c04abb3a SW |
226 | sdhci@c8000400 { |
227 | compatible = "nvidia,tegra20-sdhci"; | |
228 | reg = <0xc8000400 0x200>; | |
229 | interrupts = <0 19 0x04>; | |
2a5fdc9a | 230 | status = "disable"; |
c04abb3a SW |
231 | }; |
232 | ||
233 | sdhci@c8000600 { | |
234 | compatible = "nvidia,tegra20-sdhci"; | |
235 | reg = <0xc8000600 0x200>; | |
236 | interrupts = <0 31 0x04>; | |
2a5fdc9a | 237 | status = "disable"; |
c04abb3a SW |
238 | }; |
239 | ||
240 | pmu { | |
241 | compatible = "arm,cortex-a9-pmu"; | |
242 | interrupts = <0 56 0x04 | |
243 | 0 57 0x04>; | |
6a943e0e | 244 | }; |
8e267f3d | 245 | }; |