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ARM: tegra: document use of standard DMA DT bindings
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
885a8cfa 1#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 4
1bd0bd49 5#include "skeleton.dtsi"
8e267f3d
GL		 6
7/ {
8 compatible = "nvidia,tegra20";
9 interrupt-parent = <&intc>;
10
b6551bb9
LD		 11 aliases {
12 serial0 = &uarta;
13 serial1 = &uartb;
14 serial2 = &uartc;
15 serial3 = &uartd;
16 serial4 = &uarte;
17 };
18
ed821f07
TR		 19 host1x {
20 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>;
6cecf916
SW		 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
ed821f07
TR		 25
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 ranges = <0x54000000 0x54000000 0x04000000>;
30
31 mpe {
32 compatible = "nvidia,tegra20-mpe";
33 reg = <0x54040000 0x00040000>;
6cecf916 34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 35 clocks = <&tegra_car TEGRA20_CLK_MPE>;
ed821f07
TR		 36 };
37
38 vi {
39 compatible = "nvidia,tegra20-vi";
40 reg = <0x54080000 0x00040000>;
6cecf916 41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 42 clocks = <&tegra_car TEGRA20_CLK_VI>;
ed821f07
TR		 43 };
44
45 epp {
46 compatible = "nvidia,tegra20-epp";
47 reg = <0x540c0000 0x00040000>;
6cecf916 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
ed821f07
TR		 50 };
51
52 isp {
53 compatible = "nvidia,tegra20-isp";
54 reg = <0x54100000 0x00040000>;
6cecf916 55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 56 clocks = <&tegra_car TEGRA20_CLK_ISP>;
ed821f07
TR		 57 };
58
59 gr2d {
60 compatible = "nvidia,tegra20-gr2d";
61 reg = <0x54140000 0x00040000>;
6cecf916 62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 63 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
ed821f07
TR		 64 };
65
66 gr3d {
67 compatible = "nvidia,tegra20-gr3d";
68 reg = <0x54180000 0x00040000>;
885a8cfa 69 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
ed821f07
TR		 70 };
71
72 dc@54200000 {
73 compatible = "nvidia,tegra20-dc";
74 reg = <0x54200000 0x00040000>;
6cecf916 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 76 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 78 clock-names = "dc", "parent";
ed821f07
TR		 79
80 rgb {
81 status = "disabled";
82 };
83 };
84
85 dc@54240000 {
86 compatible = "nvidia,tegra20-dc";
87 reg = <0x54240000 0x00040000>;
6cecf916 88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 89 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 91 clock-names = "dc", "parent";
ed821f07
TR		 92
93 rgb {
94 status = "disabled";
95 };
96 };
97
98 hdmi {
99 compatible = "nvidia,tegra20-hdmi";
100 reg = <0x54280000 0x00040000>;
6cecf916 101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 102 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 104 clock-names = "hdmi", "parent";
ed821f07
TR		 105 status = "disabled";
106 };
107
108 tvo {
109 compatible = "nvidia,tegra20-tvo";
110 reg = <0x542c0000 0x00040000>;
6cecf916 111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 112 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 113 status = "disabled";
114 };
115
116 dsi {
117 compatible = "nvidia,tegra20-dsi";
118 reg = <0x54300000 0x00040000>;
885a8cfa 119 clocks = <&tegra_car TEGRA20_CLK_DSI>;
ed821f07
TR		 120 status = "disabled";
121 };
122 };
123
73368ba0
SW		 124 timer@50004600 {
125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x50040600 0x20>;
6cecf916
SW		 127 interrupts = <GIC_PPI 13
128 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa 129 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 130 };
131
f9eb26a4 132 intc: interrupt-controller {
0d4f7479 133 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 134 reg = <0x50041000 0x1000
135 0x50040100 0x0100>;
2eaab06e
SW		 136 interrupt-controller;
137 #interrupt-cells = <3>;
8e267f3d
GL		 138 };
139
bb2c1de9
SW		 140 cache-controller {
141 compatible = "arm,pl310-cache";
142 reg = <0x50043000 0x1000>;
143 arm,data-latency = <5 5 2>;
144 arm,tag-latency = <4 4 2>;
145 cache-unified;
146 cache-level = <2>;
147 };
148
2f2b7fb2
SW		 149 timer@60005000 {
150 compatible = "nvidia,tegra20-timer";
151 reg = <0x60005000 0x60>;
6cecf916
SW		 152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 156 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 157 };
158
270f8ce3
SW		 159 tegra_car: clock {
160 compatible = "nvidia,tegra20-car";
161 reg = <0x60006000 0x1000>;
162 #clock-cells = <1>;
163 };
164
f9eb26a4 165 apbdma: dma {
8051b75a
SW		 166 compatible = "nvidia,tegra20-apbdma";
167 reg = <0x6000a000 0x1200>;
6cecf916
SW		 168 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
8051b75a
SW		 185 };
186
c04abb3a
SW		 187 ahb {
188 compatible = "nvidia,tegra20-ahb";
189 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 190 };
191
f9eb26a4 192 gpio: gpio {
8e267f3d 193 compatible = "nvidia,tegra20-gpio";
95decf84 194 reg = <0x6000d000 0x1000>;
6cecf916
SW		 195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 202 #gpio-cells = <2>;
203 gpio-controller;
6f74dc9b
SW		 204 #interrupt-cells = <2>;
205 interrupt-controller;
8e267f3d
GL		 206 };
207
f9eb26a4 208 pinmux: pinmux {
f62f548c 209 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 210 reg = <0x70000014 0x10 /* Tri-state registers */
211 0x70000080 0x20 /* Mux registers */
212 0x700000a0 0x14 /* Pull-up/down registers */
213 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 214 };
215
c04abb3a
SW		 216 das {
217 compatible = "nvidia,tegra20-das";
218 reg = <0x70000c00 0x80>;
219 };
fc5c306b 220
0698ed19
LS		 221 tegra_ac97: ac97 {
222 compatible = "nvidia,tegra20-ac97";
223 reg = <0x70002000 0x200>;
6cecf916 224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0698ed19 225 nvidia,dma-request-selector = <&apbdma 12>;
885a8cfa 226 clocks = <&tegra_car TEGRA20_CLK_AC97>;
0698ed19
LS		 227 status = "disabled";
228 };
c04abb3a
SW		 229
230 tegra_i2s1: i2s@70002800 {
231 compatible = "nvidia,tegra20-i2s";
232 reg = <0x70002800 0x200>;
6cecf916 233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 234 nvidia,dma-request-selector = <&apbdma 2>;
885a8cfa 235 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
223ef78d 236 status = "disabled";
c04abb3a
SW		 237 };
238
239 tegra_i2s2: i2s@70002a00 {
240 compatible = "nvidia,tegra20-i2s";
241 reg = <0x70002a00 0x200>;
6cecf916 242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 243 nvidia,dma-request-selector = <&apbdma 1>;
885a8cfa 244 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
223ef78d 245 status = "disabled";
c04abb3a
SW		 246 };
247
b6551bb9
LD		 248 /*
249 * There are two serial driver i.e. 8250 based simple serial
250 * driver and APB DMA based serial driver for higher baudrate
251 * and performace. To enable the 8250 based driver, the compatible
252 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
253 * driver, the comptible is "nvidia,tegra20-hsuart".
254 */
255 uarta: serial@70006000 {
8e267f3d
GL		 256 compatible = "nvidia,tegra20-uart";
257 reg = <0x70006000 0x40>;
258 reg-shift = <2>;
6cecf916 259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 260 nvidia,dma-request-selector = <&apbdma 8>;
885a8cfa 261 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
223ef78d 262 status = "disabled";
8e267f3d
GL		 263 };
264
b6551bb9 265 uartb: serial@70006040 {
8e267f3d
GL		 266 compatible = "nvidia,tegra20-uart";
267 reg = <0x70006040 0x40>;
268 reg-shift = <2>;
6cecf916 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 270 nvidia,dma-request-selector = <&apbdma 9>;
885a8cfa 271 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
223ef78d 272 status = "disabled";
8e267f3d
GL		 273 };
274
b6551bb9 275 uartc: serial@70006200 {
8e267f3d
GL		 276 compatible = "nvidia,tegra20-uart";
277 reg = <0x70006200 0x100>;
278 reg-shift = <2>;
6cecf916 279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 280 nvidia,dma-request-selector = <&apbdma 10>;
885a8cfa 281 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
223ef78d 282 status = "disabled";
8e267f3d
GL		 283 };
284
b6551bb9 285 uartd: serial@70006300 {
8e267f3d
GL		 286 compatible = "nvidia,tegra20-uart";
287 reg = <0x70006300 0x100>;
288 reg-shift = <2>;
6cecf916 289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 290 nvidia,dma-request-selector = <&apbdma 19>;
885a8cfa 291 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
223ef78d 292 status = "disabled";
8e267f3d
GL		 293 };
294
b6551bb9 295 uarte: serial@70006400 {
8e267f3d
GL		 296 compatible = "nvidia,tegra20-uart";
297 reg = <0x70006400 0x100>;
298 reg-shift = <2>;
6cecf916 299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 300 nvidia,dma-request-selector = <&apbdma 20>;
885a8cfa 301 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
223ef78d 302 status = "disabled";
8e267f3d
GL		 303 };
304
2b8b15da 305 pwm: pwm {
140fd977
TR		 306 compatible = "nvidia,tegra20-pwm";
307 reg = <0x7000a000 0x100>;
308 #pwm-cells = <2>;
885a8cfa 309 clocks = <&tegra_car TEGRA20_CLK_PWM>;
b69cd984 310 status = "disabled";
140fd977
TR		 311 };
312
380e04ac
SW		 313 rtc {
314 compatible = "nvidia,tegra20-rtc";
315 reg = <0x7000e000 0x100>;
6cecf916 316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 317 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 318 };
319
c04abb3a 320 i2c@7000c000 {
c04abb3a
SW		 321 compatible = "nvidia,tegra20-i2c";
322 reg = <0x7000c000 0x100>;
6cecf916 323 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 324 #address-cells = <1>;
325 #size-cells = <0>;
885a8cfa
HD		 326 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 328 clock-names = "div-clk", "fast-clk";
223ef78d 329 status = "disabled";
0c6700ab
OJ		 330 };
331
fa98a114
LD		 332 spi@7000c380 {
333 compatible = "nvidia,tegra20-sflash";
334 reg = <0x7000c380 0x80>;
6cecf916 335 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 336 nvidia,dma-request-selector = <&apbdma 11>;
337 #address-cells = <1>;
338 #size-cells = <0>;
885a8cfa 339 clocks = <&tegra_car TEGRA20_CLK_SPI>;
fa98a114
LD		 340 status = "disabled";
341 };
342
c04abb3a 343 i2c@7000c400 {
c04abb3a
SW		 344 compatible = "nvidia,tegra20-i2c";
345 reg = <0x7000c400 0x100>;
6cecf916 346 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 347 #address-cells = <1>;
348 #size-cells = <0>;
885a8cfa
HD		 349 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 351 clock-names = "div-clk", "fast-clk";
223ef78d 352 status = "disabled";
8e267f3d
GL		 353 };
354
c04abb3a 355 i2c@7000c500 {
c04abb3a
SW		 356 compatible = "nvidia,tegra20-i2c";
357 reg = <0x7000c500 0x100>;
6cecf916 358 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 359 #address-cells = <1>;
360 #size-cells = <0>;
885a8cfa
HD		 361 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 363 clock-names = "div-clk", "fast-clk";
223ef78d 364 status = "disabled";
8e267f3d
GL		 365 };
366
c04abb3a 367 i2c@7000d000 {
c04abb3a
SW		 368 compatible = "nvidia,tegra20-i2c-dvc";
369 reg = <0x7000d000 0x200>;
6cecf916 370 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 371 #address-cells = <1>;
372 #size-cells = <0>;
885a8cfa
HD		 373 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 375 clock-names = "div-clk", "fast-clk";
223ef78d 376 status = "disabled";
8e267f3d
GL		 377 };
378
a86b0db3
LD		 379 spi@7000d400 {
380 compatible = "nvidia,tegra20-slink";
381 reg = <0x7000d400 0x200>;
6cecf916 382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 383 nvidia,dma-request-selector = <&apbdma 15>;
384 #address-cells = <1>;
385 #size-cells = <0>;
885a8cfa 386 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
a86b0db3
LD		 387 status = "disabled";
388 };
389
390 spi@7000d600 {
391 compatible = "nvidia,tegra20-slink";
392 reg = <0x7000d600 0x200>;
6cecf916 393 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 394 nvidia,dma-request-selector = <&apbdma 16>;
395 #address-cells = <1>;
396 #size-cells = <0>;
885a8cfa 397 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
a86b0db3
LD		 398 status = "disabled";
399 };
400
401 spi@7000d800 {
402 compatible = "nvidia,tegra20-slink";
57471c8d 403 reg = <0x7000d800 0x200>;
6cecf916 404 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 405 nvidia,dma-request-selector = <&apbdma 17>;
406 #address-cells = <1>;
407 #size-cells = <0>;
885a8cfa 408 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
a86b0db3
LD		 409 status = "disabled";
410 };
411
412 spi@7000da00 {
413 compatible = "nvidia,tegra20-slink";
414 reg = <0x7000da00 0x200>;
6cecf916 415 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 416 nvidia,dma-request-selector = <&apbdma 18>;
417 #address-cells = <1>;
418 #size-cells = <0>;
885a8cfa 419 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
a86b0db3
LD		 420 status = "disabled";
421 };
422
699ed4b9
LD		 423 kbc {
424 compatible = "nvidia,tegra20-kbc";
425 reg = <0x7000e200 0x100>;
6cecf916 426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 427 clocks = <&tegra_car TEGRA20_CLK_KBC>;
699ed4b9
LD		 428 status = "disabled";
429 };
430
c04abb3a
SW		 431 pmc {
432 compatible = "nvidia,tegra20-pmc";
433 reg = <0x7000e400 0x400>;
885a8cfa 434 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 435 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 436 };
437
bbfc33bd 438 memory-controller@7000f000 {
c04abb3a
SW		 439 compatible = "nvidia,tegra20-mc";
440 reg = <0x7000f000 0x024
441 0x7000f03c 0x3c4>;
6cecf916 442 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 443 };
444
109269e8 445 iommu {
c04abb3a
SW		 446 compatible = "nvidia,tegra20-gart";
447 reg = <0x7000f024 0x00000018 /* controller registers */
448 0x58000000 0x02000000>; /* GART aperture */
449 };
450
bbfc33bd 451 memory-controller@7000f400 {
c04abb3a
SW		 452 compatible = "nvidia,tegra20-emc";
453 reg = <0x7000f400 0x200>;
2eaab06e
SW		 454 #address-cells = <1>;
455 #size-cells = <0>;
8e267f3d 456 };
c27317c0 457
1b62b611
TR		 458 pcie-controller {
459 compatible = "nvidia,tegra20-pcie";
460 device_type = "pci";
461 reg = <0x80003000 0x00000800 /* PADS registers */
462 0x80003800 0x00000200 /* AFI registers */
463 0x90000000 0x10000000>; /* configuration space */
464 reg-names = "pads", "afi", "cs";
465 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
466 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
467 interrupt-names = "intr", "msi";
468
469 bus-range = <0x00 0xff>;
470 #address-cells = <3>;
471 #size-cells = <2>;
472
473 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
474 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
475 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 476 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
477 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 478
479 clocks = <&tegra_car TEGRA20_CLK_PEX>,
480 <&tegra_car TEGRA20_CLK_AFI>,
481 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
482 <&tegra_car TEGRA20_CLK_PLL_E>;
483 clock-names = "pex", "afi", "pcie_xclk", "pll_e";
484 status = "disabled";
485
486 pci@1,0 {
487 device_type = "pci";
488 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
489 reg = <0x000800 0 0 0 0>;
490 status = "disabled";
491
492 #address-cells = <3>;
493 #size-cells = <2>;
494 ranges;
495
496 nvidia,num-lanes = <2>;
497 };
498
499 pci@2,0 {
500 device_type = "pci";
501 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
502 reg = <0x001000 0 0 0 0>;
503 status = "disabled";
504
505 #address-cells = <3>;
506 #size-cells = <2>;
507 ranges;
508
509 nvidia,num-lanes = <2>;
510 };
511 };
512
c27317c0
OJ		 513 usb@c5000000 {
514 compatible = "nvidia,tegra20-ehci", "usb-ehci";
515 reg = <0xc5000000 0x4000>;
6cecf916 516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 517 phy_type = "utmi";
ba202f15 518 nvidia,has-legacy-mode;
885a8cfa 519 clocks = <&tegra_car TEGRA20_CLK_USBD>;
b4e07478 520 nvidia,needs-double-reset;
e374b65c 521 nvidia,phy = <&phy1>;
223ef78d 522 status = "disabled";
c27317c0
OJ		 523 };
524
4c94c8b5 525 phy1: usb-phy@c5000000 {
5d324410 526 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 527 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 528 phy_type = "utmi";
885a8cfa
HD		 529 clocks = <&tegra_car TEGRA20_CLK_USBD>,
530 <&tegra_car TEGRA20_CLK_PLL_U>,
531 <&tegra_car TEGRA20_CLK_CLK_M>,
532 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 533 clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410 534 nvidia,has-legacy-mode;
c49667e5
MP		 535 nvidia,hssync-start-delay = <9>;
536 nvidia,idle-wait-delay = <17>;
537 nvidia,elastic-limit = <16>;
538 nvidia,term-range-adj = <6>;
539 nvidia,xcvr-setup = <9>;
540 nvidia,xcvr-lsfslew = <1>;
541 nvidia,xcvr-lsrslew = <1>;
4c94c8b5 542 status = "disabled";
5d324410
SW		 543 };
544
c27317c0
OJ		 545 usb@c5004000 {
546 compatible = "nvidia,tegra20-ehci", "usb-ehci";
547 reg = <0xc5004000 0x4000>;
6cecf916 548 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 549 phy_type = "ulpi";
885a8cfa 550 clocks = <&tegra_car TEGRA20_CLK_USB2>;
e374b65c 551 nvidia,phy = <&phy2>;
223ef78d 552 status = "disabled";
c27317c0
OJ		 553 };
554
4c94c8b5 555 phy2: usb-phy@c5004000 {
5d324410 556 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 557 reg = <0xc5004000 0x4000>;
5d324410 558 phy_type = "ulpi";
885a8cfa
HD		 559 clocks = <&tegra_car TEGRA20_CLK_USB2>,
560 <&tegra_car TEGRA20_CLK_PLL_U>,
561 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5
VB		 562 clock-names = "reg", "pll_u", "ulpi-link";
563 status = "disabled";
5d324410
SW		 564 };
565
c27317c0
OJ		 566 usb@c5008000 {
567 compatible = "nvidia,tegra20-ehci", "usb-ehci";
568 reg = <0xc5008000 0x4000>;
6cecf916 569 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 570 phy_type = "utmi";
885a8cfa 571 clocks = <&tegra_car TEGRA20_CLK_USB3>;
e374b65c 572 nvidia,phy = <&phy3>;
223ef78d 573 status = "disabled";
c27317c0 574 };
7868a9bc 575
4c94c8b5 576 phy3: usb-phy@c5008000 {
5d324410 577 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 578 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 579 phy_type = "utmi";
885a8cfa
HD		 580 clocks = <&tegra_car TEGRA20_CLK_USB3>,
581 <&tegra_car TEGRA20_CLK_PLL_U>,
582 <&tegra_car TEGRA20_CLK_CLK_M>,
583 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 584 clock-names = "reg", "pll_u", "timer", "utmi-pads";
c49667e5
MP		 585 nvidia,hssync-start-delay = <9>;
586 nvidia,idle-wait-delay = <17>;
587 nvidia,elastic-limit = <16>;
588 nvidia,term-range-adj = <6>;
589 nvidia,xcvr-setup = <9>;
590 nvidia,xcvr-lsfslew = <2>;
591 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 592 status = "disabled";
5d324410
SW		 593 };
594
c04abb3a
SW		 595 sdhci@c8000000 {
596 compatible = "nvidia,tegra20-sdhci";
597 reg = <0xc8000000 0x200>;
6cecf916 598 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 599 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
223ef78d 600 status = "disabled";
7868a9bc 601 };
4a82f2b3 602
c04abb3a
SW		 603 sdhci@c8000200 {
604 compatible = "nvidia,tegra20-sdhci";
605 reg = <0xc8000200 0x200>;
6cecf916 606 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 607 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
223ef78d 608 status = "disabled";
4a82f2b3 609 };
6a943e0e 610
c04abb3a
SW		 611 sdhci@c8000400 {
612 compatible = "nvidia,tegra20-sdhci";
613 reg = <0xc8000400 0x200>;
6cecf916 614 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 615 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
223ef78d 616 status = "disabled";
c04abb3a
SW		 617 };
618
619 sdhci@c8000600 {
620 compatible = "nvidia,tegra20-sdhci";
621 reg = <0xc8000600 0x200>;
6cecf916 622 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 623 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
223ef78d 624 status = "disabled";
c04abb3a
SW		 625 };
626
4dd2bd37
HD		 627 cpus {
628 #address-cells = <1>;
629 #size-cells = <0>;
630
631 cpu@0 {
632 device_type = "cpu";
633 compatible = "arm,cortex-a9";
634 reg = <0>;
635 };
636
637 cpu@1 {
638 device_type = "cpu";
639 compatible = "arm,cortex-a9";
640 reg = <1>;
641 };
642 };
643
c04abb3a
SW		 644 pmu {
645 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 646 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 648 };
8e267f3d 649};
Ubuntu Eoan Linux kernel mirror