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ARM: tegra: apalis_t30: reorder host1x/hdmi properties
[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / tegra30-apalis.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
6d0a067f
MZ		 2#include "tegra30.dtsi"
3
4/*
a5e27206
MZ		 5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
7 * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
6d0a067f
MZ		 8 */
9/ {
10 model = "Toradex Apalis T30";
11 compatible = "toradex,apalis_t30", "nvidia,tegra30";
12
48299769
KK		 13 memory@80000000 {
14 reg = <0x80000000 0x40000000>;
f48ba1ae
KK		 15 };
16
508d690e 17 pcie@3000 {
7890d785 18 status = "okay";
b607b19a 19 avdd-pexa-supply = <&vdd2_reg>;
b607b19a 20 avdd-pexb-supply = <&vdd2_reg>;
b607b19a
MZ		 21 avdd-pex-pll-supply = <&vdd2_reg>;
22 avdd-plle-supply = <&ldo6_reg>;
b607b19a 23 hvdd-pex-supply = <&sys_3v3_reg>;
4f6b07a2
MZ		 24 vddio-pex-ctl-supply = <&sys_3v3_reg>;
25 vdd-pexa-supply = <&vdd2_reg>;
26 vdd-pexb-supply = <&vdd2_reg>;
6d0a067f 27
7890d785 28 /* Apalis type specific */
6d0a067f
MZ		 29 pci@1,0 {
30 nvidia,num-lanes = <4>;
31 };
32
7890d785 33 /* Apalis PCIe */
6d0a067f
MZ		 34 pci@2,0 {
35 nvidia,num-lanes = <1>;
36 };
37
7890d785 38 /* I210/I211 Gigabit Ethernet Controller (on-module) */
6d0a067f 39 pci@3,0 {
7890d785 40 status = "okay";
6d0a067f 41 nvidia,num-lanes = <1>;
2c87441c
MZ		 42 pcie@0 {
43 reg = <0 0 0 0 0>;
44 local-mac-address = [00 00 00 00 00 00];
45 };
6d0a067f
MZ		 46 };
47 };
48
49 host1x@50000000 {
50 hdmi@54280000 {
a772d28d 51 nvidia,ddc-i2c-bus = <&hdmiddc>;
6d0a067f
MZ		 52 nvidia,hpd-gpio =
53 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
a772d28d
MZ		 54 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
55 vdd-supply = <&avdd_hdmi_3v3_reg>;
6d0a067f
MZ		 56 };
57 };
58
59 pinmux@70000868 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&state_default>;
62
63 state_default: pinmux {
8948e746
MZ		 64 /* Analogue Audio (On-module) */
65 clk1_out_pw4 {
66 nvidia,pins = "clk1_out_pw4";
67 nvidia,function = "extperiph1";
68 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
69 nvidia,tristate = <TEGRA_PIN_DISABLE>;
70 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
71 };
72 dap3_fs_pp0 {
73 nvidia,pins = "dap3_fs_pp0",
74 "dap3_sclk_pp3",
75 "dap3_din_pp1",
76 "dap3_dout_pp2";
77 nvidia,function = "i2s2";
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81
6d0a067f
MZ		 82 /* Apalis BKL1_ON */
83 pv2 {
84 nvidia,pins = "pv2";
85 nvidia,function = "rsvd4";
86 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
87 nvidia,tristate = <TEGRA_PIN_DISABLE>;
88 };
89
90 /* Apalis BKL1_PWM */
91 uart3_rts_n_pc0 {
40699b92 92 nvidia,pins = "uart3_rts_n_pc0";
6d0a067f
MZ		 93 nvidia,function = "pwm0";
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 };
97 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
98 uart3_cts_n_pa1 {
40699b92 99 nvidia,pins = "uart3_cts_n_pa1";
0f44de6c 100 nvidia,function = "rsvd2";
6d0a067f
MZ		 101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 };
104
105 /* Apalis CAN1 on SPI6 */
106 spi2_cs0_n_px3 {
40699b92
TR		 107 nvidia,pins = "spi2_cs0_n_px3",
108 "spi2_miso_px1",
109 "spi2_mosi_px0",
110 "spi2_sck_px2";
6d0a067f
MZ		 111 nvidia,function = "spi6";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 };
115 /* CAN_INT1 */
116 spi2_cs1_n_pw2 {
117 nvidia,pins = "spi2_cs1_n_pw2";
118 nvidia,function = "spi3";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122 };
123
124 /* Apalis CAN2 on SPI4 */
125 gmi_a16_pj7 {
40699b92
TR		 126 nvidia,pins = "gmi_a16_pj7",
127 "gmi_a17_pb0",
128 "gmi_a18_pb1",
129 "gmi_a19_pk7";
6d0a067f
MZ		 130 nvidia,function = "spi4";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
700253e7 133 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
6d0a067f
MZ		 134 };
135 /* CAN_INT2 */
136 spi2_cs2_n_pw3 {
137 nvidia,pins = "spi2_cs2_n_pw3";
138 nvidia,function = "spi3";
139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142 };
143
4399f40b
MZ		 144 /* Apalis Digital Audio */
145 clk1_req_pee2 {
40699b92 146 nvidia,pins = "clk1_req_pee2";
4399f40b
MZ		 147 nvidia,function = "hda";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 };
151 clk2_out_pw5 {
152 nvidia,pins = "clk2_out_pw5";
153 nvidia,function = "extperiph2";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
157 };
158 dap1_fs_pn0 {
40699b92
TR		 159 nvidia,pins = "dap1_fs_pn0",
160 "dap1_din_pn1",
161 "dap1_dout_pn2",
162 "dap1_sclk_pn3";
4399f40b
MZ		 163 nvidia,function = "hda";
164 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165 nvidia,tristate = <TEGRA_PIN_DISABLE>;
166 };
167
6d0a067f
MZ		 168 /* Apalis I2C3 */
169 cam_i2c_scl_pbb1 {
170 nvidia,pins = "cam_i2c_scl_pbb1",
171 "cam_i2c_sda_pbb2";
172 nvidia,function = "i2c3";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
176 nvidia,lock = <TEGRA_PIN_DISABLE>;
177 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
178 };
179
180 /* Apalis MMC1 */
181 sdmmc3_clk_pa6 {
1c997fe4 182 nvidia,pins = "sdmmc3_clk_pa6";
6d0a067f
MZ		 183 nvidia,function = "sdmmc3";
184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 };
187 sdmmc3_dat0_pb7 {
1c997fe4
MZ		 188 nvidia,pins = "sdmmc3_cmd_pa7",
189 "sdmmc3_dat0_pb7",
40699b92
TR		 190 "sdmmc3_dat1_pb6",
191 "sdmmc3_dat2_pb5",
192 "sdmmc3_dat3_pb4",
193 "sdmmc3_dat4_pd1",
194 "sdmmc3_dat5_pd0",
195 "sdmmc3_dat6_pd3",
196 "sdmmc3_dat7_pd4";
6d0a067f
MZ		 197 nvidia,function = "sdmmc3";
198 nvidia,pull = <TEGRA_PIN_PULL_UP>;
199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
200 };
201 /* Apalis MMC1_CD# */
202 pv3 {
203 nvidia,pins = "pv3";
204 nvidia,function = "rsvd2";
055c0107 205 nvidia,pull = <TEGRA_PIN_PULL_UP>;
6d0a067f
MZ		 206 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208 };
209
210 /* Apalis PWM1 */
0f44de6c 211 pu6 {
40699b92 212 nvidia,pins = "pu6";
6d0a067f
MZ		 213 nvidia,function = "pwm3";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 };
217
218 /* Apalis PWM2 */
0f44de6c 219 pu5 {
40699b92 220 nvidia,pins = "pu5";
6d0a067f
MZ		 221 nvidia,function = "pwm2";
222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 nvidia,tristate = <TEGRA_PIN_DISABLE>;
224 };
225
226 /* Apalis PWM3 */
0f44de6c 227 pu4 {
40699b92 228 nvidia,pins = "pu4";
6d0a067f
MZ		 229 nvidia,function = "pwm1";
230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 };
233
234 /* Apalis PWM4 */
0f44de6c 235 pu3 {
40699b92 236 nvidia,pins = "pu3";
6d0a067f
MZ		 237 nvidia,function = "pwm0";
238 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239 nvidia,tristate = <TEGRA_PIN_DISABLE>;
240 };
241
242 /* Apalis RESET_MOCI# */
243 gmi_rst_n_pi4 {
244 nvidia,pins = "gmi_rst_n_pi4";
245 nvidia,function = "gmi";
246 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247 nvidia,tristate = <TEGRA_PIN_DISABLE>;
248 };
249
250 /* Apalis SD1 */
251 sdmmc1_clk_pz0 {
252 nvidia,pins = "sdmmc1_clk_pz0";
253 nvidia,function = "sdmmc1";
254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 sdmmc1_cmd_pz1 {
40699b92
TR		 258 nvidia,pins = "sdmmc1_cmd_pz1",
259 "sdmmc1_dat0_py7",
260 "sdmmc1_dat1_py6",
261 "sdmmc1_dat2_py5",
262 "sdmmc1_dat3_py4";
6d0a067f
MZ		 263 nvidia,function = "sdmmc1";
264 nvidia,pull = <TEGRA_PIN_PULL_UP>;
265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
266 };
267 /* Apalis SD1_CD# */
268 clk2_req_pcc5 {
269 nvidia,pins = "clk2_req_pcc5";
270 nvidia,function = "rsvd2";
055c0107 271 nvidia,pull = <TEGRA_PIN_PULL_UP>;
6d0a067f
MZ		 272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
274 };
275
276 /* Apalis SPI1 */
277 spi1_sck_px5 {
40699b92
TR		 278 nvidia,pins = "spi1_sck_px5",
279 "spi1_mosi_px4",
280 "spi1_miso_px7",
281 "spi1_cs0_n_px6";
6d0a067f
MZ		 282 nvidia,function = "spi1";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 };
286
287 /* Apalis SPI2 */
288 lcd_sck_pz4 {
40699b92
TR		 289 nvidia,pins = "lcd_sck_pz4",
290 "lcd_sdout_pn5",
291 "lcd_sdin_pz2",
292 "lcd_cs0_n_pn4";
6d0a067f
MZ		 293 nvidia,function = "spi5";
294 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
297
298 /* Apalis UART1 */
299 ulpi_data0 {
40699b92
TR		 300 nvidia,pins = "ulpi_data0_po1",
301 "ulpi_data1_po2",
302 "ulpi_data2_po3",
303 "ulpi_data3_po4",
304 "ulpi_data4_po5",
305 "ulpi_data5_po6",
306 "ulpi_data6_po7",
307 "ulpi_data7_po0";
6d0a067f
MZ		 308 nvidia,function = "uarta";
309 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 };
312
313 /* Apalis UART2 */
314 ulpi_clk_py0 {
40699b92
TR		 315 nvidia,pins = "ulpi_clk_py0",
316 "ulpi_dir_py1",
317 "ulpi_nxt_py2",
318 "ulpi_stp_py3";
6d0a067f
MZ		 319 nvidia,function = "uartd";
320 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
321 nvidia,tristate = <TEGRA_PIN_DISABLE>;
322 };
323
324 /* Apalis UART3 */
325 uart2_rxd_pc3 {
40699b92
TR		 326 nvidia,pins = "uart2_rxd_pc3",
327 "uart2_txd_pc2";
6d0a067f
MZ		 328 nvidia,function = "uartb";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_DISABLE>;
331 };
332
333 /* Apalis UART4 */
334 uart3_rxd_pw7 {
40699b92
TR		 335 nvidia,pins = "uart3_rxd_pw7",
336 "uart3_txd_pw6";
6d0a067f
MZ		 337 nvidia,function = "uartc";
338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>;
340 };
341
342 /* Apalis USBO1_EN */
343 gen2_i2c_scl_pt5 {
344 nvidia,pins = "gen2_i2c_scl_pt5";
345 nvidia,function = "rsvd4";
346 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
347 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 };
350
351 /* Apalis USBO1_OC# */
352 gen2_i2c_sda_pt6 {
353 nvidia,pins = "gen2_i2c_sda_pt6";
354 nvidia,function = "rsvd4";
355 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
356 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
359 };
360
361 /* Apalis WAKE1_MICO */
362 pv1 {
363 nvidia,pins = "pv1";
364 nvidia,function = "rsvd1";
365 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
366 nvidia,tristate = <TEGRA_PIN_DISABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368 };
369
370 /* eMMC (On-module) */
371 sdmmc4_clk_pcc4 {
40699b92
TR		 372 nvidia,pins = "sdmmc4_clk_pcc4",
373 "sdmmc4_rst_n_pcc3";
6d0a067f
MZ		 374 nvidia,function = "sdmmc4";
375 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
376 nvidia,tristate = <TEGRA_PIN_DISABLE>;
377 };
378 sdmmc4_dat0_paa0 {
40699b92
TR		 379 nvidia,pins = "sdmmc4_dat0_paa0",
380 "sdmmc4_dat1_paa1",
381 "sdmmc4_dat2_paa2",
382 "sdmmc4_dat3_paa3",
383 "sdmmc4_dat4_paa4",
384 "sdmmc4_dat5_paa5",
385 "sdmmc4_dat6_paa6",
386 "sdmmc4_dat7_paa7";
6d0a067f
MZ		 387 nvidia,function = "sdmmc4";
388 nvidia,pull = <TEGRA_PIN_PULL_UP>;
389 nvidia,tristate = <TEGRA_PIN_DISABLE>;
390 };
391
392 /* LVDS Transceiver Configuration */
393 pbb0 {
40699b92
TR		 394 nvidia,pins = "pbb0",
395 "pbb7",
396 "pcc1",
397 "pcc2";
6d0a067f
MZ		 398 nvidia,function = "rsvd2";
399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402 nvidia,lock = <TEGRA_PIN_DISABLE>;
403 };
404 pbb3 {
40699b92
TR		 405 nvidia,pins = "pbb3",
406 "pbb4",
407 "pbb5",
408 "pbb6";
6d0a067f
MZ		 409 nvidia,function = "displayb";
410 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
411 nvidia,tristate = <TEGRA_PIN_DISABLE>;
412 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
413 nvidia,lock = <TEGRA_PIN_DISABLE>;
414 };
415
416 /* Power I2C (On-module) */
417 pwr_i2c_scl_pz6 {
418 nvidia,pins = "pwr_i2c_scl_pz6",
419 "pwr_i2c_sda_pz7";
420 nvidia,function = "i2cpwr";
421 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
422 nvidia,tristate = <TEGRA_PIN_DISABLE>;
423 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
424 nvidia,lock = <TEGRA_PIN_DISABLE>;
425 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
426 };
427
428 /*
429 * THERMD_ALERT#, unlatched I2C address pin of LM95245
430 * temperature sensor therefore requires disabling for
431 * now
432 */
433 lcd_dc1_pd2 {
434 nvidia,pins = "lcd_dc1_pd2";
435 nvidia,function = "rsvd3";
436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
437 nvidia,tristate = <TEGRA_PIN_DISABLE>;
438 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
439 };
440
441 /* TOUCH_PEN_INT# */
442 pv0 {
443 nvidia,pins = "pv0";
444 nvidia,function = "rsvd1";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
448 };
449 };
450 };
451
452 hdmiddc: i2c@7000c700 {
1c3389e6 453 clock-frequency = <10000>;
6d0a067f
MZ		 454 };
455
456 /*
457 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
458 * touch screen controller
459 */
460 i2c@7000d000 {
461 status = "okay";
462 clock-frequency = <100000>;
463
8948e746
MZ		 464 /* SGTL5000 audio codec */
465 sgtl5000: codec@a {
466 compatible = "fsl,sgtl5000";
467 reg = <0x0a>;
468 VDDA-supply = <&sys_3v3_reg>;
469 VDDIO-supply = <&sys_3v3_reg>;
470 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
471 };
472
6d0a067f
MZ		 473 pmic: tps65911@2d {
474 compatible = "ti,tps65911";
475 reg = <0x2d>;
476
477 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
478 #interrupt-cells = <2>;
479 interrupt-controller;
480
481 ti,system-power-controller;
482
483 #gpio-cells = <2>;
484 gpio-controller;
485
486 vcc1-supply = <&sys_3v3_reg>;
487 vcc2-supply = <&sys_3v3_reg>;
488 vcc3-supply = <&vio_reg>;
489 vcc4-supply = <&sys_3v3_reg>;
490 vcc5-supply = <&sys_3v3_reg>;
491 vcc6-supply = <&vio_reg>;
caa9eac5 492 vcc7-supply = <&charge_pump_5v0_reg>;
6d0a067f
MZ		 493 vccio-supply = <&sys_3v3_reg>;
494
495 regulators {
496 /* SW1: +V1.35_VDDIO_DDR */
497 vdd1_reg: vdd1 {
498 regulator-name = "vddio_ddr_1v35";
499 regulator-min-microvolt = <1350000>;
500 regulator-max-microvolt = <1350000>;
501 regulator-always-on;
502 };
503
504 /* SW2: +V1.05 */
505 vdd2_reg: vdd2 {
506 regulator-name =
507 "vdd_pexa,vdd_pexb,vdd_sata";
508 regulator-min-microvolt = <1050000>;
509 regulator-max-microvolt = <1050000>;
510 };
511
512 /* SW CTRL: +V1.0_VDD_CPU */
513 vddctrl_reg: vddctrl {
514 regulator-name = "vdd_cpu,vdd_sys";
515 regulator-min-microvolt = <1150000>;
516 regulator-max-microvolt = <1150000>;
517 regulator-always-on;
518 };
519
520 /* SWIO: +V1.8 */
521 vio_reg: vio {
522 regulator-name = "vdd_1v8_gen";
523 regulator-min-microvolt = <1800000>;
524 regulator-max-microvolt = <1800000>;
525 regulator-always-on;
526 };
527
528 /* LDO1: unused */
529
530 /*
531 * EN_+V3.3 switching via FET:
532 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
533 * see also v3_3 fixed supply
534 */
535 ldo2_reg: ldo2 {
536 regulator-name = "en_3v3";
537 regulator-min-microvolt = <3300000>;
538 regulator-max-microvolt = <3300000>;
539 regulator-always-on;
540 };
541
542 /* +V1.2_CSI */
543 ldo3_reg: ldo3 {
544 regulator-name =
545 "avdd_dsi_csi,pwrdet_mipi";
546 regulator-min-microvolt = <1200000>;
547 regulator-max-microvolt = <1200000>;
548 };
549
550 /* +V1.2_VDD_RTC */
551 ldo4_reg: ldo4 {
552 regulator-name = "vdd_rtc";
553 regulator-min-microvolt = <1200000>;
554 regulator-max-microvolt = <1200000>;
555 regulator-always-on;
556 };
557
558 /*
559 * +V2.8_AVDD_VDAC:
560 * only required for analog RGB
561 */
562 ldo5_reg: ldo5 {
563 regulator-name = "avdd_vdac";
564 regulator-min-microvolt = <2800000>;
565 regulator-max-microvolt = <2800000>;
566 regulator-always-on;
567 };
568
569 /*
570 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
571 * but LDO6 can't set voltage in 50mV
572 * granularity
573 */
574 ldo6_reg: ldo6 {
575 regulator-name = "avdd_plle";
576 regulator-min-microvolt = <1100000>;
577 regulator-max-microvolt = <1100000>;
578 };
579
580 /* +V1.2_AVDD_PLL */
581 ldo7_reg: ldo7 {
582 regulator-name = "avdd_pll";
583 regulator-min-microvolt = <1200000>;
584 regulator-max-microvolt = <1200000>;
585 regulator-always-on;
586 };
587
588 /* +V1.0_VDD_DDR_HS */
589 ldo8_reg: ldo8 {
590 regulator-name = "vdd_ddr_hs";
591 regulator-min-microvolt = <1000000>;
592 regulator-max-microvolt = <1000000>;
593 regulator-always-on;
594 };
595 };
596 };
597
598 /* STMPE811 touch screen controller */
599 stmpe811@41 {
600 compatible = "st,stmpe811";
6d0a067f
MZ		 601 reg = <0x41>;
602 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
603 interrupt-parent = <&gpio>;
604 interrupt-controller;
605 id = <0>;
606 blocks = <0x5>;
607 irq-trigger = <0x1>;
608
35a21229 609 stmpe_touchscreen {
6d0a067f 610 compatible = "st,stmpe-ts";
6d0a067f
MZ		 611 /* 3.25 MHz ADC clock speed */
612 st,adc-freq = <1>;
613 /* 8 sample average control */
614 st,ave-ctrl = <3>;
615 /* 7 length fractional part in z */
616 st,fraction-z = <7>;
617 /*
618 * 50 mA typical 80 mA max touchscreen drivers
619 * current limit value
620 */
621 st,i-drive = <1>;
622 /* 12-bit ADC */
623 st,mod-12b = <1>;
624 /* internal ADC reference */
625 st,ref-sel = <0>;
626 /* ADC converstion time: 80 clocks */
627 st,sample-time = <4>;
628 /* 1 ms panel driver settling time */
629 st,settling = <3>;
630 /* 5 ms touch detect interrupt delay */
631 st,touch-det-delay = <5>;
632 };
633 };
634
635 /*
636 * LM95245 temperature sensor
637 * Note: OVERT_N directly connected to PMIC PWRDN
638 */
639 temp-sensor@4c {
640 compatible = "national,lm95245";
641 reg = <0x4c>;
642 };
643
644 /* SW: +V1.2_VDD_CORE */
645 tps62362@60 {
646 compatible = "ti,tps62362";
647 reg = <0x60>;
648
649 regulator-name = "tps62362-vout";
650 regulator-min-microvolt = <900000>;
651 regulator-max-microvolt = <1400000>;
652 regulator-boot-on;
653 regulator-always-on;
654 ti,vsel0-state-low;
655 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
656 ti,vsel1-state-low;
657 };
658 };
659
660 /* SPI4: CAN2 */
661 spi@7000da00 {
662 status = "okay";
663 spi-max-frequency = <10000000>;
664
665 can@1 {
666 compatible = "microchip,mcp2515";
667 reg = <1>;
668 clocks = <&clk16m>;
669 interrupt-parent = <&gpio>;
b604ef9c 670 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
6d0a067f
MZ		 671 spi-max-frequency = <10000000>;
672 };
673 };
674
675 /* SPI6: CAN1 */
676 spi@7000de00 {
677 status = "okay";
678 spi-max-frequency = <10000000>;
679
680 can@0 {
681 compatible = "microchip,mcp2515";
682 reg = <0>;
683 clocks = <&clk16m>;
684 interrupt-parent = <&gpio>;
b604ef9c 685 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
6d0a067f
MZ		 686 spi-max-frequency = <10000000>;
687 };
688 };
689
690 pmc@7000e400 {
691 nvidia,invert-interrupt;
692 nvidia,suspend-mode = <1>;
693 nvidia,cpu-pwr-good-time = <5000>;
694 nvidia,cpu-pwr-off-time = <5000>;
695 nvidia,core-pwr-good-time = <3845 3845>;
696 nvidia,core-pwr-off-time = <0>;
697 nvidia,core-power-req-active-high;
698 nvidia,sys-clock-req-active-high;
699 };
700
8948e746
MZ		 701 ahub@70080000 {
702 i2s@70080500 {
703 status = "okay";
704 };
705 };
706
7be74b05 707 /* eMMC */
6d0a067f
MZ		 708 sdhci@78000600 {
709 status = "okay";
710 bus-width = <8>;
711 non-removable;
712 };
713
714 clocks {
715 compatible = "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <0>;
718
719 clk32k_in: clk@0 {
720 compatible = "fixed-clock";
4ec2e601 721 reg = <0>;
6d0a067f
MZ		 722 #clock-cells = <0>;
723 clock-frequency = <32768>;
724 };
4ec2e601 725
6d0a067f
MZ		 726 clk16m: clk@1 {
727 compatible = "fixed-clock";
4ec2e601 728 reg = <1>;
6d0a067f
MZ		 729 #clock-cells = <0>;
730 clock-frequency = <16000000>;
731 clock-output-names = "clk16m";
732 };
733 };
734
735 regulators {
736 compatible = "simple-bus";
737 #address-cells = <1>;
738 #size-cells = <0>;
739
654b7d6a 740 avdd_hdmi_pll_1v8_reg: regulator@100 {
6d0a067f
MZ		 741 compatible = "regulator-fixed";
742 reg = <100>;
654b7d6a
MZ		 743 regulator-name = "+V1.8_AVDD_HDMI_PLL";
744 regulator-min-microvolt = <1800000>;
745 regulator-max-microvolt = <1800000>;
746 enable-active-high;
747 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
748 vin-supply = <&vio_reg>;
749 };
750
751 sys_3v3_reg: regulator@101 {
752 compatible = "regulator-fixed";
753 reg = <101>;
6d0a067f
MZ		 754 regulator-name = "3v3";
755 regulator-min-microvolt = <3300000>;
756 regulator-max-microvolt = <3300000>;
757 regulator-always-on;
758 };
caa9eac5 759
654b7d6a 760 avdd_hdmi_3v3_reg: regulator@102 {
caa9eac5 761 compatible = "regulator-fixed";
654b7d6a
MZ		 762 reg = <102>;
763 regulator-name = "+V3.3_AVDD_HDMI";
764 regulator-min-microvolt = <3300000>;
765 regulator-max-microvolt = <3300000>;
766 enable-active-high;
767 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
768 vin-supply = <&sys_3v3_reg>;
769 };
770
771 charge_pump_5v0_reg: regulator@103 {
772 compatible = "regulator-fixed";
773 reg = <103>;
caa9eac5
MZ		 774 regulator-name = "5v0";
775 regulator-min-microvolt = <5000000>;
776 regulator-max-microvolt = <5000000>;
777 regulator-always-on;
778 };
6d0a067f 779 };
8948e746
MZ		 780
781 sound {
782 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
783 "nvidia,tegra-audio-sgtl5000";
784 nvidia,model = "Toradex Apalis T30";
785 nvidia,audio-routing =
786 "Headphone Jack", "HP_OUT",
787 "LINE_IN", "Line In Jack",
788 "MIC_IN", "Mic Jack";
789 nvidia,i2s-controller = <&tegra_i2s2>;
790 nvidia,audio-codec = <&sgtl5000>;
791 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
792 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
793 <&tegra_car TEGRA30_CLK_EXTERN1>;
794 clock-names = "pll_a", "pll_a_out0", "mclk";
795 };
6d0a067f 796};
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