projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d7df69fe BW |
1 | /dts-v1/; |
| 2 | ||
| 1bd0bd49 | 3 | #include "tegra30.dtsi" |
| d7df69fe BW |
4 | |
| 5 | / { | |
| 6 | model = "NVIDIA Tegra30 Beaver evaluation board"; | |
| 7 | compatible = "nvidia,beaver", "nvidia,tegra30"; | |
| 8 | ||
| 553c0a20 SW |
9 | aliases { |
| 10 | rtc0 = "/i2c@7000d000/tps65911@2d"; | |
| 11 | rtc1 = "/rtc@7000e000"; | |
| c4574aa0 | 12 | serial0 = &uarta; |
| 553c0a20 | 13 | }; |
| f5bbb327 JH |
14 | |
| 15 | chosen { | |
| 16 | stdout-path = "serial0:115200n8"; | |
| 17 | }; | |
| 553c0a20 | 18 | |
| d7df69fe | 19 | memory { |
| 30022bb4 | 20 | reg = <0x80000000 0x7ff00000>; |
| d7df69fe BW |
21 | }; |
| 22 | ||
| 58ecb23f | 23 | pcie-controller@00003000 { |
| bb034cb5 | 24 | status = "okay"; |
| cca8614d TR |
25 | |
| 26 | avdd-pexa-supply = <&ldo1_reg>; | |
| 27 | vdd-pexa-supply = <&ldo1_reg>; | |
| 28 | avdd-pexb-supply = <&ldo1_reg>; | |
| 29 | vdd-pexb-supply = <&ldo1_reg>; | |
| 30 | avdd-pex-pll-supply = <&ldo1_reg>; | |
| 31 | avdd-plle-supply = <&ldo1_reg>; | |
| 32 | vddio-pex-ctl-supply = <&sys_3v3_reg>; | |
| 33 | hvdd-pex-supply = <&sys_3v3_pexs_reg>; | |
| 34 | ||
| bb034cb5 TR |
35 | pci@1,0 { |
| 36 | status = "okay"; | |
| 44fefab4 | 37 | nvidia,num-lanes = <2>; |
| bb034cb5 TR |
38 | }; |
| 39 | ||
| 40 | pci@2,0 { | |
| 44fefab4 | 41 | nvidia,num-lanes = <2>; |
| bb034cb5 TR |
42 | }; |
| 43 | ||
| 44 | pci@3,0 { | |
| 44fefab4 SW |
45 | status = "okay"; |
| 46 | nvidia,num-lanes = <2>; | |
| bb034cb5 TR |
47 | }; |
| 48 | }; | |
| 49 | ||
| 58ecb23f SW |
50 | host1x@50000000 { |
| 51 | hdmi@54280000 { | |
| 9bd80b41 TR |
52 | status = "okay"; |
| 53 | ||
| 597eb8e1 | 54 | hdmi-supply = <&vdd_5v0_hdmi>; |
| 9bd80b41 TR |
55 | vdd-supply = <&sys_3v3_reg>; |
| 56 | pll-supply = <&vio_reg>; | |
| 57 | ||
| 58 | nvidia,hpd-gpio = | |
| 59 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
| 60 | nvidia,ddc-i2c-bus = <&hdmiddc>; | |
| 61 | }; | |
| 62 | }; | |
| 63 | ||
| 58ecb23f | 64 | pinmux@70000868 { |
| d7df69fe BW |
65 | pinctrl-names = "default"; |
| 66 | pinctrl-0 = <&state_default>; | |
| 67 | ||
| 68 | state_default: pinmux { | |
| 3d03203a LS |
69 | clk_32k_out_pa0 { |
| 70 | nvidia,pins = "clk_32k_out_pa0"; | |
| 71 | nvidia,function = "blink"; | |
| 72 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 73 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 74 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 75 | }; | |
| 76 | uart3_cts_n_pa1 { | |
| 77 | nvidia,pins = "uart3_cts_n_pa1"; | |
| 78 | nvidia,function = "uartc"; | |
| 79 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 80 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 81 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 82 | }; | |
| 83 | dap2_fs_pa2 { | |
| 84 | nvidia,pins = "dap2_fs_pa2"; | |
| 85 | nvidia,function = "i2s1"; | |
| 86 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 87 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 88 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 89 | }; | |
| 90 | dap2_sclk_pa3 { | |
| 91 | nvidia,pins = "dap2_sclk_pa3"; | |
| 92 | nvidia,function = "i2s1"; | |
| 93 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 94 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 95 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 96 | }; | |
| 97 | dap2_din_pa4 { | |
| 98 | nvidia,pins = "dap2_din_pa4"; | |
| 99 | nvidia,function = "i2s1"; | |
| 100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 102 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 103 | }; | |
| 104 | dap2_dout_pa5 { | |
| 105 | nvidia,pins = "dap2_dout_pa5"; | |
| 106 | nvidia,function = "i2s1"; | |
| 107 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 109 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 110 | }; | |
| 111 | sdmmc3_clk_pa6 { | |
| 112 | nvidia,pins = "sdmmc3_clk_pa6"; | |
| 113 | nvidia,function = "sdmmc3"; | |
| 114 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 115 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 116 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 117 | }; | |
| 118 | sdmmc3_cmd_pa7 { | |
| 119 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
| 120 | nvidia,function = "sdmmc3"; | |
| 121 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 124 | }; | |
| 125 | gmi_a17_pb0 { | |
| 126 | nvidia,pins = "gmi_a17_pb0"; | |
| 127 | nvidia,function = "spi4"; | |
| 128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 130 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 131 | }; | |
| 132 | gmi_a18_pb1 { | |
| 133 | nvidia,pins = "gmi_a18_pb1"; | |
| 134 | nvidia,function = "spi4"; | |
| 135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 138 | }; | |
| 139 | lcd_pwr0_pb2 { | |
| 140 | nvidia,pins = "lcd_pwr0_pb2"; | |
| 141 | nvidia,function = "displaya"; | |
| 142 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 143 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 144 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 145 | }; | |
| 146 | lcd_pclk_pb3 { | |
| 147 | nvidia,pins = "lcd_pclk_pb3"; | |
| 148 | nvidia,function = "displaya"; | |
| 149 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 150 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 152 | }; | |
| 153 | sdmmc3_dat3_pb4 { | |
| 154 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
| 155 | nvidia,function = "sdmmc3"; | |
| 156 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 157 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 158 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 159 | }; | |
| 160 | sdmmc3_dat2_pb5 { | |
| 161 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
| 162 | nvidia,function = "sdmmc3"; | |
| 163 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 164 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 166 | }; | |
| 167 | sdmmc3_dat1_pb6 { | |
| 168 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
| 169 | nvidia,function = "sdmmc3"; | |
| 170 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 173 | }; | |
| 174 | sdmmc3_dat0_pb7 { | |
| 175 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
| 176 | nvidia,function = "sdmmc3"; | |
| 177 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 179 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 180 | }; | |
| 181 | uart3_rts_n_pc0 { | |
| 182 | nvidia,pins = "uart3_rts_n_pc0"; | |
| 183 | nvidia,function = "uartc"; | |
| 184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 187 | }; | |
| 188 | lcd_pwr1_pc1 { | |
| 189 | nvidia,pins = "lcd_pwr1_pc1"; | |
| 190 | nvidia,function = "displaya"; | |
| 191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 193 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 194 | }; | |
| 195 | uart2_txd_pc2 { | |
| 196 | nvidia,pins = "uart2_txd_pc2"; | |
| 197 | nvidia,function = "uartb"; | |
| 198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 199 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 200 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 201 | }; | |
| 202 | uart2_rxd_pc3 { | |
| 203 | nvidia,pins = "uart2_rxd_pc3"; | |
| 204 | nvidia,function = "uartb"; | |
| 205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 206 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 207 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 208 | }; | |
| 209 | gen1_i2c_scl_pc4 { | |
| 210 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
| 211 | nvidia,function = "i2c1"; | |
| 212 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 213 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 214 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 215 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 216 | }; | |
| 217 | gen1_i2c_sda_pc5 { | |
| 218 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
| 219 | nvidia,function = "i2c1"; | |
| 220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 222 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 223 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 224 | }; | |
| 225 | lcd_pwr2_pc6 { | |
| 226 | nvidia,pins = "lcd_pwr2_pc6"; | |
| 227 | nvidia,function = "displaya"; | |
| 228 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 229 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 230 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 231 | }; | |
| 232 | gmi_wp_n_pc7 { | |
| 233 | nvidia,pins = "gmi_wp_n_pc7"; | |
| 234 | nvidia,function = "gmi"; | |
| 235 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 236 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 237 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 238 | }; | |
| 239 | sdmmc3_dat5_pd0 { | |
| 240 | nvidia,pins = "sdmmc3_dat5_pd0"; | |
| 241 | nvidia,function = "sdmmc3"; | |
| 242 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 244 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 245 | }; | |
| 246 | sdmmc3_dat4_pd1 { | |
| 247 | nvidia,pins = "sdmmc3_dat4_pd1"; | |
| 248 | nvidia,function = "sdmmc3"; | |
| 249 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 250 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 251 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 252 | }; | |
| 253 | lcd_dc1_pd2 { | |
| 254 | nvidia,pins = "lcd_dc1_pd2"; | |
| 255 | nvidia,function = "displaya"; | |
| 256 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 258 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 259 | }; | |
| 260 | sdmmc3_dat6_pd3 { | |
| 261 | nvidia,pins = "sdmmc3_dat6_pd3"; | |
| 262 | nvidia,function = "rsvd1"; | |
| 263 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 265 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 266 | }; | |
| 267 | sdmmc3_dat7_pd4 { | |
| 268 | nvidia,pins = "sdmmc3_dat7_pd4"; | |
| 269 | nvidia,function = "rsvd1"; | |
| 270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 272 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 273 | }; | |
| 274 | vi_d1_pd5 { | |
| 275 | nvidia,pins = "vi_d1_pd5"; | |
| 276 | nvidia,function = "sdmmc2"; | |
| 277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 278 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 279 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 280 | }; | |
| 281 | vi_vsync_pd6 { | |
| 282 | nvidia,pins = "vi_vsync_pd6"; | |
| 283 | nvidia,function = "rsvd1"; | |
| 284 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 286 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 287 | }; | |
| 288 | vi_hsync_pd7 { | |
| 289 | nvidia,pins = "vi_hsync_pd7"; | |
| 290 | nvidia,function = "rsvd1"; | |
| 291 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 292 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 293 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 294 | }; | |
| 295 | lcd_d0_pe0 { | |
| 296 | nvidia,pins = "lcd_d0_pe0"; | |
| 297 | nvidia,function = "displaya"; | |
| 298 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 299 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 300 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 301 | }; | |
| 302 | lcd_d1_pe1 { | |
| 303 | nvidia,pins = "lcd_d1_pe1"; | |
| 304 | nvidia,function = "displaya"; | |
| 305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 306 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 307 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 308 | }; | |
| 309 | lcd_d2_pe2 { | |
| 310 | nvidia,pins = "lcd_d2_pe2"; | |
| 311 | nvidia,function = "displaya"; | |
| 312 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 313 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 314 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 315 | }; | |
| 316 | lcd_d3_pe3 { | |
| 317 | nvidia,pins = "lcd_d3_pe3"; | |
| 318 | nvidia,function = "displaya"; | |
| 319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 321 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 322 | }; | |
| 323 | lcd_d4_pe4 { | |
| 324 | nvidia,pins = "lcd_d4_pe4"; | |
| 325 | nvidia,function = "displaya"; | |
| 326 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 327 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 329 | }; | |
| 330 | lcd_d5_pe5 { | |
| 331 | nvidia,pins = "lcd_d5_pe5"; | |
| 332 | nvidia,function = "displaya"; | |
| 333 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 334 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 335 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 336 | }; | |
| 337 | lcd_d6_pe6 { | |
| 338 | nvidia,pins = "lcd_d6_pe6"; | |
| 339 | nvidia,function = "displaya"; | |
| 340 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 341 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 342 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 343 | }; | |
| 344 | lcd_d7_pe7 { | |
| 345 | nvidia,pins = "lcd_d7_pe7"; | |
| 346 | nvidia,function = "displaya"; | |
| 347 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 349 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 350 | }; | |
| 351 | lcd_d8_pf0 { | |
| 352 | nvidia,pins = "lcd_d8_pf0"; | |
| 353 | nvidia,function = "displaya"; | |
| 354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 355 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 356 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 357 | }; | |
| 358 | lcd_d9_pf1 { | |
| 359 | nvidia,pins = "lcd_d9_pf1"; | |
| 360 | nvidia,function = "displaya"; | |
| 361 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 362 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 363 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 364 | }; | |
| 365 | lcd_d10_pf2 { | |
| 366 | nvidia,pins = "lcd_d10_pf2"; | |
| 367 | nvidia,function = "displaya"; | |
| 368 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 369 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 370 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 371 | }; | |
| 372 | lcd_d11_pf3 { | |
| 373 | nvidia,pins = "lcd_d11_pf3"; | |
| 374 | nvidia,function = "displaya"; | |
| 375 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 376 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 377 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 378 | }; | |
| 379 | lcd_d12_pf4 { | |
| 380 | nvidia,pins = "lcd_d12_pf4"; | |
| 381 | nvidia,function = "displaya"; | |
| 382 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 383 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 384 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 385 | }; | |
| 386 | lcd_d13_pf5 { | |
| 387 | nvidia,pins = "lcd_d13_pf5"; | |
| 388 | nvidia,function = "displaya"; | |
| 389 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 390 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 391 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 392 | }; | |
| 393 | lcd_d14_pf6 { | |
| 394 | nvidia,pins = "lcd_d14_pf6"; | |
| 395 | nvidia,function = "displaya"; | |
| 396 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 397 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 398 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 399 | }; | |
| 400 | lcd_d15_pf7 { | |
| 401 | nvidia,pins = "lcd_d15_pf7"; | |
| 402 | nvidia,function = "displaya"; | |
| 403 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 404 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 405 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 406 | }; | |
| 407 | gmi_ad0_pg0 { | |
| 408 | nvidia,pins = "gmi_ad0_pg0"; | |
| 409 | nvidia,function = "nand"; | |
| 410 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 411 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 412 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 413 | }; | |
| 414 | gmi_ad1_pg1 { | |
| 415 | nvidia,pins = "gmi_ad1_pg1"; | |
| 416 | nvidia,function = "nand"; | |
| 417 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 418 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 419 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 420 | }; | |
| 421 | gmi_ad2_pg2 { | |
| 422 | nvidia,pins = "gmi_ad2_pg2"; | |
| 423 | nvidia,function = "nand"; | |
| 424 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 425 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 426 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 427 | }; | |
| 428 | gmi_ad3_pg3 { | |
| 429 | nvidia,pins = "gmi_ad3_pg3"; | |
| 430 | nvidia,function = "nand"; | |
| 431 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 432 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 433 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 434 | }; | |
| 435 | gmi_ad4_pg4 { | |
| 436 | nvidia,pins = "gmi_ad4_pg4"; | |
| 437 | nvidia,function = "nand"; | |
| 438 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 439 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 440 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 441 | }; | |
| 442 | gmi_ad5_pg5 { | |
| 443 | nvidia,pins = "gmi_ad5_pg5"; | |
| 444 | nvidia,function = "nand"; | |
| 445 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 446 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 447 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 448 | }; | |
| 449 | gmi_ad6_pg6 { | |
| 450 | nvidia,pins = "gmi_ad6_pg6"; | |
| 451 | nvidia,function = "nand"; | |
| 452 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 453 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 454 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 455 | }; | |
| 456 | gmi_ad7_pg7 { | |
| 457 | nvidia,pins = "gmi_ad7_pg7"; | |
| 458 | nvidia,function = "nand"; | |
| 459 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 460 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 461 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 462 | }; | |
| 463 | gmi_ad8_ph0 { | |
| 464 | nvidia,pins = "gmi_ad8_ph0"; | |
| 465 | nvidia,function = "pwm0"; | |
| 466 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 467 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 468 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 469 | }; | |
| 470 | gmi_ad9_ph1 { | |
| 471 | nvidia,pins = "gmi_ad9_ph1"; | |
| 472 | nvidia,function = "pwm1"; | |
| 473 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 474 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 475 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 476 | }; | |
| 477 | gmi_ad10_ph2 { | |
| 478 | nvidia,pins = "gmi_ad10_ph2"; | |
| 479 | nvidia,function = "nand"; | |
| 480 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 481 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 482 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 483 | }; | |
| 484 | gmi_ad11_ph3 { | |
| 485 | nvidia,pins = "gmi_ad11_ph3"; | |
| 486 | nvidia,function = "nand"; | |
| 487 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 488 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 489 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 490 | }; | |
| 491 | gmi_ad12_ph4 { | |
| 492 | nvidia,pins = "gmi_ad12_ph4"; | |
| 493 | nvidia,function = "nand"; | |
| 494 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 497 | }; | |
| 498 | gmi_ad13_ph5 { | |
| 499 | nvidia,pins = "gmi_ad13_ph5"; | |
| 500 | nvidia,function = "nand"; | |
| 501 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 502 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 503 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 504 | }; | |
| 505 | gmi_ad14_ph6 { | |
| 506 | nvidia,pins = "gmi_ad14_ph6"; | |
| 507 | nvidia,function = "nand"; | |
| 508 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 509 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 510 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 511 | }; | |
| 512 | gmi_wr_n_pi0 { | |
| 513 | nvidia,pins = "gmi_wr_n_pi0"; | |
| 514 | nvidia,function = "nand"; | |
| 515 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 516 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 517 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 518 | }; | |
| 519 | gmi_oe_n_pi1 { | |
| 520 | nvidia,pins = "gmi_oe_n_pi1"; | |
| 521 | nvidia,function = "nand"; | |
| 522 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 523 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 524 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 525 | }; | |
| 526 | gmi_dqs_pi2 { | |
| 527 | nvidia,pins = "gmi_dqs_pi2"; | |
| 528 | nvidia,function = "nand"; | |
| 529 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 530 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 531 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 532 | }; | |
| 533 | gmi_iordy_pi5 { | |
| 534 | nvidia,pins = "gmi_iordy_pi5"; | |
| 535 | nvidia,function = "rsvd1"; | |
| 536 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 537 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 538 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 539 | }; | |
| 540 | gmi_cs7_n_pi6 { | |
| 541 | nvidia,pins = "gmi_cs7_n_pi6"; | |
| 542 | nvidia,function = "nand"; | |
| 543 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 544 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 545 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 546 | }; | |
| 547 | gmi_wait_pi7 { | |
| 548 | nvidia,pins = "gmi_wait_pi7"; | |
| 549 | nvidia,function = "nand"; | |
| 550 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 551 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 552 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 553 | }; | |
| 554 | lcd_de_pj1 { | |
| 555 | nvidia,pins = "lcd_de_pj1"; | |
| 556 | nvidia,function = "displaya"; | |
| 557 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 558 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 559 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 560 | }; | |
| 561 | lcd_hsync_pj3 { | |
| 562 | nvidia,pins = "lcd_hsync_pj3"; | |
| 563 | nvidia,function = "displaya"; | |
| 564 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 565 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 566 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 567 | }; | |
| 568 | lcd_vsync_pj4 { | |
| 569 | nvidia,pins = "lcd_vsync_pj4"; | |
| 570 | nvidia,function = "displaya"; | |
| 571 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 572 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 573 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 574 | }; | |
| 575 | uart2_cts_n_pj5 { | |
| 576 | nvidia,pins = "uart2_cts_n_pj5"; | |
| 577 | nvidia,function = "uartb"; | |
| 578 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 579 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 580 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 581 | }; | |
| 582 | uart2_rts_n_pj6 { | |
| 583 | nvidia,pins = "uart2_rts_n_pj6"; | |
| 584 | nvidia,function = "uartb"; | |
| 585 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 586 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 587 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 588 | }; | |
| 589 | gmi_a16_pj7 { | |
| 590 | nvidia,pins = "gmi_a16_pj7"; | |
| 591 | nvidia,function = "spi4"; | |
| 592 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 593 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 594 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 595 | }; | |
| 596 | gmi_adv_n_pk0 { | |
| 597 | nvidia,pins = "gmi_adv_n_pk0"; | |
| 598 | nvidia,function = "nand"; | |
| 599 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 600 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 601 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 602 | }; | |
| 603 | gmi_clk_pk1 { | |
| 604 | nvidia,pins = "gmi_clk_pk1"; | |
| 605 | nvidia,function = "nand"; | |
| 606 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 607 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 608 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 609 | }; | |
| 610 | gmi_cs2_n_pk3 { | |
| 611 | nvidia,pins = "gmi_cs2_n_pk3"; | |
| 612 | nvidia,function = "rsvd1"; | |
| 613 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 614 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 615 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 616 | }; | |
| 617 | gmi_cs3_n_pk4 { | |
| 618 | nvidia,pins = "gmi_cs3_n_pk4"; | |
| 619 | nvidia,function = "nand"; | |
| 620 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 621 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 622 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 623 | }; | |
| 624 | spdif_out_pk5 { | |
| 625 | nvidia,pins = "spdif_out_pk5"; | |
| 626 | nvidia,function = "spdif"; | |
| 627 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 629 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 630 | }; | |
| 631 | spdif_in_pk6 { | |
| 632 | nvidia,pins = "spdif_in_pk6"; | |
| 633 | nvidia,function = "spdif"; | |
| 634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 637 | }; | |
| 638 | gmi_a19_pk7 { | |
| 639 | nvidia,pins = "gmi_a19_pk7"; | |
| 640 | nvidia,function = "spi4"; | |
| 641 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 644 | }; | |
| 645 | vi_d2_pl0 { | |
| 646 | nvidia,pins = "vi_d2_pl0"; | |
| 647 | nvidia,function = "sdmmc2"; | |
| 648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 650 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 651 | }; | |
| 652 | vi_d3_pl1 { | |
| 653 | nvidia,pins = "vi_d3_pl1"; | |
| 654 | nvidia,function = "sdmmc2"; | |
| 655 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 658 | }; | |
| 659 | vi_d4_pl2 { | |
| 660 | nvidia,pins = "vi_d4_pl2"; | |
| 661 | nvidia,function = "vi"; | |
| 662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 664 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 665 | }; | |
| 666 | vi_d5_pl3 { | |
| 667 | nvidia,pins = "vi_d5_pl3"; | |
| 668 | nvidia,function = "sdmmc2"; | |
| 669 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 670 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 671 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 672 | }; | |
| 673 | vi_d6_pl4 { | |
| 674 | nvidia,pins = "vi_d6_pl4"; | |
| 675 | nvidia,function = "vi"; | |
| 676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 678 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 679 | }; | |
| 680 | vi_d7_pl5 { | |
| 681 | nvidia,pins = "vi_d7_pl5"; | |
| 682 | nvidia,function = "sdmmc2"; | |
| 683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 685 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 686 | }; | |
| 687 | vi_d8_pl6 { | |
| 688 | nvidia,pins = "vi_d8_pl6"; | |
| 689 | nvidia,function = "sdmmc2"; | |
| 690 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 691 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 692 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 693 | }; | |
| 694 | vi_d9_pl7 { | |
| 695 | nvidia,pins = "vi_d9_pl7"; | |
| 696 | nvidia,function = "sdmmc2"; | |
| 697 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 699 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 700 | }; | |
| 701 | lcd_d16_pm0 { | |
| 702 | nvidia,pins = "lcd_d16_pm0"; | |
| 703 | nvidia,function = "displaya"; | |
| 704 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 705 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 706 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 707 | }; | |
| 708 | lcd_d17_pm1 { | |
| 709 | nvidia,pins = "lcd_d17_pm1"; | |
| 710 | nvidia,function = "displaya"; | |
| 711 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 712 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 713 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 714 | }; | |
| 715 | lcd_d18_pm2 { | |
| 716 | nvidia,pins = "lcd_d18_pm2"; | |
| 717 | nvidia,function = "displaya"; | |
| 718 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 719 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 720 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 721 | }; | |
| 722 | lcd_d19_pm3 { | |
| 723 | nvidia,pins = "lcd_d19_pm3"; | |
| 724 | nvidia,function = "displaya"; | |
| 725 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 726 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 727 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 728 | }; | |
| 729 | lcd_d20_pm4 { | |
| 730 | nvidia,pins = "lcd_d20_pm4"; | |
| 731 | nvidia,function = "displaya"; | |
| 732 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 733 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 734 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 735 | }; | |
| 736 | lcd_d21_pm5 { | |
| 737 | nvidia,pins = "lcd_d21_pm5"; | |
| 738 | nvidia,function = "displaya"; | |
| 739 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 740 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 741 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 742 | }; | |
| 743 | lcd_d22_pm6 { | |
| 744 | nvidia,pins = "lcd_d22_pm6"; | |
| 745 | nvidia,function = "displaya"; | |
| 746 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 747 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 748 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 749 | }; | |
| 750 | lcd_d23_pm7 { | |
| 751 | nvidia,pins = "lcd_d23_pm7"; | |
| 752 | nvidia,function = "displaya"; | |
| 753 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 754 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 755 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 756 | }; | |
| 757 | dap1_fs_pn0 { | |
| 758 | nvidia,pins = "dap1_fs_pn0"; | |
| 759 | nvidia,function = "i2s0"; | |
| 760 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 761 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 762 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 763 | }; | |
| 764 | dap1_din_pn1 { | |
| 765 | nvidia,pins = "dap1_din_pn1"; | |
| 766 | nvidia,function = "i2s0"; | |
| 767 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 768 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 769 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 770 | }; | |
| 771 | dap1_dout_pn2 { | |
| 772 | nvidia,pins = "dap1_dout_pn2"; | |
| 773 | nvidia,function = "i2s0"; | |
| 774 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 775 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 776 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 777 | }; | |
| 778 | dap1_sclk_pn3 { | |
| 779 | nvidia,pins = "dap1_sclk_pn3"; | |
| 780 | nvidia,function = "i2s0"; | |
| 781 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 782 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 783 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 784 | }; | |
| 785 | lcd_cs0_n_pn4 { | |
| 786 | nvidia,pins = "lcd_cs0_n_pn4"; | |
| 787 | nvidia,function = "displaya"; | |
| 788 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 789 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 790 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 791 | }; | |
| 792 | lcd_sdout_pn5 { | |
| 793 | nvidia,pins = "lcd_sdout_pn5"; | |
| 794 | nvidia,function = "displaya"; | |
| 795 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 796 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 797 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 798 | }; | |
| 799 | lcd_dc0_pn6 { | |
| 800 | nvidia,pins = "lcd_dc0_pn6"; | |
| 801 | nvidia,function = "displaya"; | |
| 802 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 803 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 804 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 805 | }; | |
| 806 | hdmi_int_pn7 { | |
| 807 | nvidia,pins = "hdmi_int_pn7"; | |
| 808 | nvidia,function = "rsvd1"; | |
| 809 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 810 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 811 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 812 | }; | |
| 813 | ulpi_data7_po0 { | |
| 814 | nvidia,pins = "ulpi_data7_po0"; | |
| 815 | nvidia,function = "uarta"; | |
| 816 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 817 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 818 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 819 | }; | |
| 820 | ulpi_data0_po1 { | |
| 821 | nvidia,pins = "ulpi_data0_po1"; | |
| 822 | nvidia,function = "uarta"; | |
| 823 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 824 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 825 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 826 | }; | |
| 827 | ulpi_data1_po2 { | |
| 828 | nvidia,pins = "ulpi_data1_po2"; | |
| 829 | nvidia,function = "uarta"; | |
| 830 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 831 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 832 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 833 | }; | |
| 834 | ulpi_data2_po3 { | |
| 835 | nvidia,pins = "ulpi_data2_po3"; | |
| 836 | nvidia,function = "uarta"; | |
| 837 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 838 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 839 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 840 | }; | |
| 841 | ulpi_data3_po4 { | |
| 842 | nvidia,pins = "ulpi_data3_po4"; | |
| 843 | nvidia,function = "rsvd1"; | |
| 844 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 845 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 846 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 847 | }; | |
| 848 | ulpi_data4_po5 { | |
| 849 | nvidia,pins = "ulpi_data4_po5"; | |
| 850 | nvidia,function = "uarta"; | |
| 851 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 852 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 853 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 854 | }; | |
| 855 | ulpi_data5_po6 { | |
| 856 | nvidia,pins = "ulpi_data5_po6"; | |
| 857 | nvidia,function = "uarta"; | |
| 858 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 859 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 860 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 861 | }; | |
| 862 | ulpi_data6_po7 { | |
| 863 | nvidia,pins = "ulpi_data6_po7"; | |
| 864 | nvidia,function = "uarta"; | |
| 865 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 866 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 867 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 868 | }; | |
| 869 | dap3_fs_pp0 { | |
| 870 | nvidia,pins = "dap3_fs_pp0"; | |
| 871 | nvidia,function = "i2s2"; | |
| 872 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 873 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 874 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 875 | }; | |
| 876 | dap3_din_pp1 { | |
| 877 | nvidia,pins = "dap3_din_pp1"; | |
| 878 | nvidia,function = "i2s2"; | |
| 879 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 880 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 881 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 882 | }; | |
| 883 | dap3_dout_pp2 { | |
| 884 | nvidia,pins = "dap3_dout_pp2"; | |
| 885 | nvidia,function = "i2s2"; | |
| 886 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 887 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 888 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 889 | }; | |
| 890 | dap3_sclk_pp3 { | |
| 891 | nvidia,pins = "dap3_sclk_pp3"; | |
| 892 | nvidia,function = "i2s2"; | |
| 893 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 894 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 895 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 896 | }; | |
| 897 | dap4_fs_pp4 { | |
| 898 | nvidia,pins = "dap4_fs_pp4"; | |
| 899 | nvidia,function = "i2s3"; | |
| 900 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 901 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 902 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 903 | }; | |
| 904 | dap4_din_pp5 { | |
| 905 | nvidia,pins = "dap4_din_pp5"; | |
| 906 | nvidia,function = "i2s3"; | |
| 907 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 908 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 909 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 910 | }; | |
| 911 | dap4_dout_pp6 { | |
| 912 | nvidia,pins = "dap4_dout_pp6"; | |
| 913 | nvidia,function = "i2s3"; | |
| 914 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 915 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 916 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 917 | }; | |
| 918 | dap4_sclk_pp7 { | |
| 919 | nvidia,pins = "dap4_sclk_pp7"; | |
| 920 | nvidia,function = "i2s3"; | |
| 921 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 922 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 923 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 924 | }; | |
| 925 | kb_col0_pq0 { | |
| 926 | nvidia,pins = "kb_col0_pq0"; | |
| 927 | nvidia,function = "kbc"; | |
| 928 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 929 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 930 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 931 | }; | |
| 932 | kb_col1_pq1 { | |
| 933 | nvidia,pins = "kb_col1_pq1"; | |
| 934 | nvidia,function = "kbc"; | |
| 935 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 936 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 937 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 938 | }; | |
| 939 | kb_col2_pq2 { | |
| 940 | nvidia,pins = "kb_col2_pq2"; | |
| 941 | nvidia,function = "kbc"; | |
| 942 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 943 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 944 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 945 | }; | |
| 946 | kb_col3_pq3 { | |
| 947 | nvidia,pins = "kb_col3_pq3"; | |
| 948 | nvidia,function = "kbc"; | |
| 949 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 950 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 951 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 952 | }; | |
| 953 | kb_col4_pq4 { | |
| 954 | nvidia,pins = "kb_col4_pq4"; | |
| 955 | nvidia,function = "kbc"; | |
| 956 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 957 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 958 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 959 | }; | |
| 960 | kb_col5_pq5 { | |
| 961 | nvidia,pins = "kb_col5_pq5"; | |
| 962 | nvidia,function = "kbc"; | |
| 963 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 964 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 965 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 966 | }; | |
| 967 | kb_col6_pq6 { | |
| 968 | nvidia,pins = "kb_col6_pq6"; | |
| 969 | nvidia,function = "kbc"; | |
| 970 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 971 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 972 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 973 | }; | |
| 974 | kb_col7_pq7 { | |
| 975 | nvidia,pins = "kb_col7_pq7"; | |
| 976 | nvidia,function = "kbc"; | |
| 977 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 978 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 979 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 980 | }; | |
| 981 | kb_row0_pr0 { | |
| 982 | nvidia,pins = "kb_row0_pr0"; | |
| 983 | nvidia,function = "kbc"; | |
| 984 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 985 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 986 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 987 | }; | |
| 988 | kb_row1_pr1 { | |
| 989 | nvidia,pins = "kb_row1_pr1"; | |
| 990 | nvidia,function = "kbc"; | |
| 991 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 992 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 993 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 994 | }; | |
| 995 | kb_row2_pr2 { | |
| 996 | nvidia,pins = "kb_row2_pr2"; | |
| 997 | nvidia,function = "kbc"; | |
| 998 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 999 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1000 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1001 | }; | |
| 1002 | kb_row3_pr3 { | |
| 1003 | nvidia,pins = "kb_row3_pr3"; | |
| 1004 | nvidia,function = "kbc"; | |
| 1005 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1006 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1007 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1008 | }; | |
| 1009 | kb_row4_pr4 { | |
| 1010 | nvidia,pins = "kb_row4_pr4"; | |
| 1011 | nvidia,function = "kbc"; | |
| 1012 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1013 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1014 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1015 | }; | |
| 1016 | kb_row5_pr5 { | |
| 1017 | nvidia,pins = "kb_row5_pr5"; | |
| 1018 | nvidia,function = "kbc"; | |
| 1019 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1020 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1021 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1022 | }; | |
| 1023 | kb_row6_pr6 { | |
| 1024 | nvidia,pins = "kb_row6_pr6"; | |
| 1025 | nvidia,function = "kbc"; | |
| 1026 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1027 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1028 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1029 | }; | |
| 1030 | kb_row7_pr7 { | |
| 1031 | nvidia,pins = "kb_row7_pr7"; | |
| 1032 | nvidia,function = "kbc"; | |
| 1033 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1034 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1035 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1036 | }; | |
| 1037 | kb_row8_ps0 { | |
| 1038 | nvidia,pins = "kb_row8_ps0"; | |
| 1039 | nvidia,function = "kbc"; | |
| 1040 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1041 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1042 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1043 | }; | |
| 1044 | kb_row9_ps1 { | |
| 1045 | nvidia,pins = "kb_row9_ps1"; | |
| 1046 | nvidia,function = "kbc"; | |
| 1047 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1048 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1049 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1050 | }; | |
| 1051 | kb_row10_ps2 { | |
| 1052 | nvidia,pins = "kb_row10_ps2"; | |
| 1053 | nvidia,function = "kbc"; | |
| 1054 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1055 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1056 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1057 | }; | |
| 1058 | kb_row11_ps3 { | |
| 1059 | nvidia,pins = "kb_row11_ps3"; | |
| 1060 | nvidia,function = "kbc"; | |
| 1061 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1062 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1063 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1064 | }; | |
| 1065 | kb_row12_ps4 { | |
| 1066 | nvidia,pins = "kb_row12_ps4"; | |
| 1067 | nvidia,function = "kbc"; | |
| 1068 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1069 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1070 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1071 | }; | |
| 1072 | kb_row13_ps5 { | |
| 1073 | nvidia,pins = "kb_row13_ps5"; | |
| 1074 | nvidia,function = "kbc"; | |
| 1075 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1076 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1077 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1078 | }; | |
| 1079 | kb_row14_ps6 { | |
| 1080 | nvidia,pins = "kb_row14_ps6"; | |
| 1081 | nvidia,function = "kbc"; | |
| 1082 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1083 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1084 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1085 | }; | |
| 1086 | kb_row15_ps7 { | |
| 1087 | nvidia,pins = "kb_row15_ps7"; | |
| 1088 | nvidia,function = "kbc"; | |
| 1089 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1090 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1091 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1092 | }; | |
| 1093 | vi_pclk_pt0 { | |
| 1094 | nvidia,pins = "vi_pclk_pt0"; | |
| 1095 | nvidia,function = "rsvd1"; | |
| 1096 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1097 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1098 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1099 | }; | |
| 1100 | vi_mclk_pt1 { | |
| 1101 | nvidia,pins = "vi_mclk_pt1"; | |
| 1102 | nvidia,function = "vi"; | |
| 1103 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1105 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1106 | }; | |
| 1107 | vi_d10_pt2 { | |
| 1108 | nvidia,pins = "vi_d10_pt2"; | |
| 1109 | nvidia,function = "rsvd1"; | |
| 1110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1113 | }; | |
| 1114 | vi_d11_pt3 { | |
| 1115 | nvidia,pins = "vi_d11_pt3"; | |
| 1116 | nvidia,function = "rsvd1"; | |
| 1117 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1119 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1120 | }; | |
| 1121 | vi_d0_pt4 { | |
| 1122 | nvidia,pins = "vi_d0_pt4"; | |
| 1123 | nvidia,function = "rsvd1"; | |
| 1124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1127 | }; | |
| 1128 | gen2_i2c_scl_pt5 { | |
| 1129 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
| 1130 | nvidia,function = "i2c2"; | |
| 1131 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1132 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1133 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1134 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1135 | }; | |
| 1136 | gen2_i2c_sda_pt6 { | |
| 1137 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
| 1138 | nvidia,function = "i2c2"; | |
| 1139 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1140 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1141 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1142 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1143 | }; | |
| 1144 | sdmmc4_cmd_pt7 { | |
| 1145 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
| 1146 | nvidia,function = "sdmmc4"; | |
| 1147 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1150 | }; | |
| 1151 | pu0 { | |
| 1152 | nvidia,pins = "pu0"; | |
| 1153 | nvidia,function = "rsvd1"; | |
| 1154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1157 | }; | |
| 1158 | pu1 { | |
| 1159 | nvidia,pins = "pu1"; | |
| 1160 | nvidia,function = "rsvd1"; | |
| 1161 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1162 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1163 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1164 | }; | |
| 1165 | pu2 { | |
| 1166 | nvidia,pins = "pu2"; | |
| 1167 | nvidia,function = "rsvd1"; | |
| 1168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1171 | }; | |
| 1172 | pu3 { | |
| 1173 | nvidia,pins = "pu3"; | |
| 1174 | nvidia,function = "rsvd1"; | |
| 1175 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1176 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1177 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1178 | }; | |
| 1179 | pu4 { | |
| 1180 | nvidia,pins = "pu4"; | |
| 1181 | nvidia,function = "pwm1"; | |
| 1182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1185 | }; | |
| 1186 | pu5 { | |
| 1187 | nvidia,pins = "pu5"; | |
| 1188 | nvidia,function = "pwm2"; | |
| 1189 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1190 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1191 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1192 | }; | |
| 1193 | pu6 { | |
| 1194 | nvidia,pins = "pu6"; | |
| 1195 | nvidia,function = "rsvd1"; | |
| 1196 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1197 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1198 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1199 | }; | |
| 1200 | jtag_rtck_pu7 { | |
| 1201 | nvidia,pins = "jtag_rtck_pu7"; | |
| 1202 | nvidia,function = "rtck"; | |
| 1203 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1204 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1205 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1206 | }; | |
| 1207 | pv0 { | |
| 1208 | nvidia,pins = "pv0"; | |
| 1209 | nvidia,function = "rsvd1"; | |
| 1210 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1212 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1213 | }; | |
| 1214 | pv2 { | |
| 1215 | nvidia,pins = "pv2"; | |
| 1216 | nvidia,function = "owr"; | |
| 1217 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1218 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1219 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1220 | }; | |
| 1221 | pv3 { | |
| 1222 | nvidia,pins = "pv3"; | |
| 1223 | nvidia,function = "rsvd1"; | |
| 1224 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1227 | }; | |
| 1228 | ddc_scl_pv4 { | |
| 1229 | nvidia,pins = "ddc_scl_pv4"; | |
| 1230 | nvidia,function = "i2c4"; | |
| 1231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1234 | }; | |
| 1235 | ddc_sda_pv5 { | |
| 1236 | nvidia,pins = "ddc_sda_pv5"; | |
| 1237 | nvidia,function = "i2c4"; | |
| 1238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1241 | }; | |
| 1242 | crt_hsync_pv6 { | |
| 1243 | nvidia,pins = "crt_hsync_pv6"; | |
| 1244 | nvidia,function = "crt"; | |
| 1245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1247 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1248 | }; | |
| 1249 | crt_vsync_pv7 { | |
| 1250 | nvidia,pins = "crt_vsync_pv7"; | |
| 1251 | nvidia,function = "crt"; | |
| 1252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1254 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1255 | }; | |
| 1256 | lcd_cs1_n_pw0 { | |
| 1257 | nvidia,pins = "lcd_cs1_n_pw0"; | |
| 1258 | nvidia,function = "displaya"; | |
| 1259 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1260 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1261 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1262 | }; | |
| 1263 | lcd_m1_pw1 { | |
| 1264 | nvidia,pins = "lcd_m1_pw1"; | |
| 1265 | nvidia,function = "displaya"; | |
| 1266 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1269 | }; | |
| 1270 | spi2_cs1_n_pw2 { | |
| 1271 | nvidia,pins = "spi2_cs1_n_pw2"; | |
| 1272 | nvidia,function = "spi2"; | |
| 1273 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1275 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1276 | }; | |
| 1277 | clk1_out_pw4 { | |
| 1278 | nvidia,pins = "clk1_out_pw4"; | |
| 1279 | nvidia,function = "extperiph1"; | |
| 1280 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1281 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1282 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1283 | }; | |
| 1284 | clk2_out_pw5 { | |
| 1285 | nvidia,pins = "clk2_out_pw5"; | |
| 1286 | nvidia,function = "extperiph2"; | |
| 1287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1289 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1290 | }; | |
| 1291 | uart3_txd_pw6 { | |
| 1292 | nvidia,pins = "uart3_txd_pw6"; | |
| 1293 | nvidia,function = "uartc"; | |
| 1294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1296 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1297 | }; | |
| 1298 | uart3_rxd_pw7 { | |
| 1299 | nvidia,pins = "uart3_rxd_pw7"; | |
| 1300 | nvidia,function = "uartc"; | |
| 1301 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1302 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1303 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1304 | }; | |
| 1305 | spi2_sck_px2 { | |
| 1306 | nvidia,pins = "spi2_sck_px2"; | |
| 1307 | nvidia,function = "gmi"; | |
| 1308 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1311 | }; | |
| 1312 | spi1_mosi_px4 { | |
| 1313 | nvidia,pins = "spi1_mosi_px4"; | |
| 1314 | nvidia,function = "spi1"; | |
| 1315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1316 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1318 | }; | |
| 1319 | spi1_sck_px5 { | |
| 1320 | nvidia,pins = "spi1_sck_px5"; | |
| 1321 | nvidia,function = "spi1"; | |
| 1322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1324 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1325 | }; | |
| 1326 | spi1_cs0_n_px6 { | |
| 1327 | nvidia,pins = "spi1_cs0_n_px6"; | |
| 1328 | nvidia,function = "spi1"; | |
| 1329 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1331 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1332 | }; | |
| 1333 | spi1_miso_px7 { | |
| 1334 | nvidia,pins = "spi1_miso_px7"; | |
| 1335 | nvidia,function = "spi1"; | |
| 1336 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1337 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1338 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1339 | }; | |
| 1340 | ulpi_clk_py0 { | |
| 1341 | nvidia,pins = "ulpi_clk_py0"; | |
| 1342 | nvidia,function = "uartd"; | |
| 1343 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1344 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1345 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1346 | }; | |
| 1347 | ulpi_dir_py1 { | |
| 1348 | nvidia,pins = "ulpi_dir_py1"; | |
| 1349 | nvidia,function = "uartd"; | |
| 1350 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1351 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1352 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1353 | }; | |
| 1354 | ulpi_nxt_py2 { | |
| 1355 | nvidia,pins = "ulpi_nxt_py2"; | |
| 1356 | nvidia,function = "uartd"; | |
| 1357 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1358 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1359 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1360 | }; | |
| 1361 | ulpi_stp_py3 { | |
| 1362 | nvidia,pins = "ulpi_stp_py3"; | |
| 1363 | nvidia,function = "uartd"; | |
| 1364 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1365 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1366 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1367 | }; | |
| 1368 | sdmmc1_dat3_py4 { | |
| 1369 | nvidia,pins = "sdmmc1_dat3_py4"; | |
| 1370 | nvidia,function = "sdmmc1"; | |
| 1371 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1374 | }; | |
| 1375 | sdmmc1_dat2_py5 { | |
| 1376 | nvidia,pins = "sdmmc1_dat2_py5"; | |
| 1377 | nvidia,function = "sdmmc1"; | |
| 1378 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1380 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1381 | }; | |
| 1382 | sdmmc1_dat1_py6 { | |
| 1383 | nvidia,pins = "sdmmc1_dat1_py6"; | |
| 1384 | nvidia,function = "sdmmc1"; | |
| 1385 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1387 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1388 | }; | |
| 1389 | sdmmc1_dat0_py7 { | |
| 1390 | nvidia,pins = "sdmmc1_dat0_py7"; | |
| 1391 | nvidia,function = "sdmmc1"; | |
| 1392 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1394 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1395 | }; | |
| d7df69fe BW |
1396 | sdmmc1_clk_pz0 { |
| 1397 | nvidia,pins = "sdmmc1_clk_pz0"; | |
| 1398 | nvidia,function = "sdmmc1"; | |
| a47c662a LD |
1399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a | 1401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| d7df69fe BW |
1402 | }; |
| 1403 | sdmmc1_cmd_pz1 { | |
| 3d03203a | 1404 | nvidia,pins = "sdmmc1_cmd_pz1"; |
| d7df69fe | 1405 | nvidia,function = "sdmmc1"; |
| a47c662a LD |
1406 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1407 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a | 1408 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| d7df69fe | 1409 | }; |
| 3d03203a LS |
1410 | lcd_sdin_pz2 { |
| 1411 | nvidia,pins = "lcd_sdin_pz2"; | |
| 1412 | nvidia,function = "displaya"; | |
| a47c662a LD |
1413 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1414 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a | 1415 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| d7df69fe | 1416 | }; |
| 3d03203a LS |
1417 | lcd_wr_n_pz3 { |
| 1418 | nvidia,pins = "lcd_wr_n_pz3"; | |
| 1419 | nvidia,function = "displaya"; | |
| 1420 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| a47c662a | 1421 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 3d03203a | 1422 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| d7df69fe | 1423 | }; |
| 3d03203a LS |
1424 | lcd_sck_pz4 { |
| 1425 | nvidia,pins = "lcd_sck_pz4"; | |
| 1426 | nvidia,function = "displaya"; | |
| 1427 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1428 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1429 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1430 | }; | |
| 1431 | sys_clk_req_pz5 { | |
| 1432 | nvidia,pins = "sys_clk_req_pz5"; | |
| 1433 | nvidia,function = "sysclk"; | |
| a47c662a LD |
1434 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1435 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a LS |
1436 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1437 | }; | |
| 1438 | pwr_i2c_scl_pz6 { | |
| 1439 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
| 1440 | nvidia,function = "i2cpwr"; | |
| 1441 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1442 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1443 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1444 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1445 | }; | |
| 1446 | pwr_i2c_sda_pz7 { | |
| 1447 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
| 1448 | nvidia,function = "i2cpwr"; | |
| 1449 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1451 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1452 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| d7df69fe BW |
1453 | }; |
| 1454 | sdmmc4_dat0_paa0 { | |
| 3d03203a | 1455 | nvidia,pins = "sdmmc4_dat0_paa0"; |
| d7df69fe | 1456 | nvidia,function = "sdmmc4"; |
| a47c662a LD |
1457 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1458 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a | 1459 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| d7df69fe | 1460 | }; |
| 3d03203a LS |
1461 | sdmmc4_dat1_paa1 { |
| 1462 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
| 1463 | nvidia,function = "sdmmc4"; | |
| 1464 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1465 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1466 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1467 | }; | |
| 1468 | sdmmc4_dat2_paa2 { | |
| 1469 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
| 1470 | nvidia,function = "sdmmc4"; | |
| 1471 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1472 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1473 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1474 | }; | |
| 1475 | sdmmc4_dat3_paa3 { | |
| 1476 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
| 1477 | nvidia,function = "sdmmc4"; | |
| 1478 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1479 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1481 | }; | |
| 1482 | sdmmc4_dat4_paa4 { | |
| 1483 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
| 1484 | nvidia,function = "sdmmc4"; | |
| 1485 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1486 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1487 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1488 | }; | |
| 1489 | sdmmc4_dat5_paa5 { | |
| 1490 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
| 1491 | nvidia,function = "sdmmc4"; | |
| 1492 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1493 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1494 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1495 | }; | |
| 1496 | sdmmc4_dat6_paa6 { | |
| 1497 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
| 1498 | nvidia,function = "sdmmc4"; | |
| 1499 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1500 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1501 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1502 | }; | |
| 1503 | sdmmc4_dat7_paa7 { | |
| 1504 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
| 1505 | nvidia,function = "sdmmc4"; | |
| 1506 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1507 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1508 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1509 | }; | |
| 1510 | pbb0 { | |
| 1511 | nvidia,pins = "pbb0"; | |
| 1512 | nvidia,function = "rsvd1"; | |
| 1513 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1514 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1515 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1516 | }; | |
| 1517 | cam_i2c_scl_pbb1 { | |
| 1518 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
| 1519 | nvidia,function = "i2c3"; | |
| 1520 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1521 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1522 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1523 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1524 | }; | |
| 1525 | cam_i2c_sda_pbb2 { | |
| 1526 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
| 1527 | nvidia,function = "i2c3"; | |
| 1528 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1529 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1530 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1531 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1532 | }; | |
| 1533 | pbb3 { | |
| 1534 | nvidia,pins = "pbb3"; | |
| 1535 | nvidia,function = "vgp3"; | |
| 1536 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1537 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1538 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1539 | }; | |
| 1540 | pbb4 { | |
| 1541 | nvidia,pins = "pbb4"; | |
| 1542 | nvidia,function = "vgp4"; | |
| 1543 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1544 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1545 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1546 | }; | |
| 1547 | pbb5 { | |
| 1548 | nvidia,pins = "pbb5"; | |
| 1549 | nvidia,function = "vgp5"; | |
| 1550 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1551 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1552 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1553 | }; | |
| 1554 | pbb6 { | |
| 1555 | nvidia,pins = "pbb6"; | |
| 1556 | nvidia,function = "vgp6"; | |
| 1557 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1558 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1559 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1560 | }; | |
| 1561 | pbb7 { | |
| 1562 | nvidia,pins = "pbb7"; | |
| 1563 | nvidia,function = "i2s4"; | |
| 1564 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1565 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1566 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1567 | }; | |
| 1568 | cam_mclk_pcc0 { | |
| 1569 | nvidia,pins = "cam_mclk_pcc0"; | |
| 1570 | nvidia,function = "vi_alt3"; | |
| 1571 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1572 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1573 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1574 | }; | |
| 1575 | pcc1 { | |
| 1576 | nvidia,pins = "pcc1"; | |
| 1577 | nvidia,function = "rsvd1"; | |
| 1578 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1579 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1580 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1581 | }; | |
| 1582 | pcc2 { | |
| 1583 | nvidia,pins = "pcc2"; | |
| 1584 | nvidia,function = "i2s4"; | |
| 1585 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1586 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1587 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1588 | }; | |
| 1589 | sdmmc4_rst_n_pcc3 { | |
| 1590 | nvidia,pins = "sdmmc4_rst_n_pcc3"; | |
| 1591 | nvidia,function = "sdmmc4"; | |
| 1592 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1593 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1594 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1595 | }; | |
| 1596 | sdmmc4_clk_pcc4 { | |
| 1597 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
| 1598 | nvidia,function = "sdmmc4"; | |
| 1599 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1600 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1601 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1602 | }; | |
| 1603 | clk2_req_pcc5 { | |
| 1604 | nvidia,pins = "clk2_req_pcc5"; | |
| 1605 | nvidia,function = "dap"; | |
| 1606 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1607 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1608 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1609 | }; | |
| 1610 | pex_l2_rst_n_pcc6 { | |
| 1611 | nvidia,pins = "pex_l2_rst_n_pcc6"; | |
| 1612 | nvidia,function = "pcie"; | |
| 1613 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1614 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1615 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1616 | }; | |
| 1617 | pex_l2_clkreq_n_pcc7 { | |
| 1618 | nvidia,pins = "pex_l2_clkreq_n_pcc7"; | |
| 1619 | nvidia,function = "pcie"; | |
| 1620 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1623 | }; | |
| 1624 | pex_l0_prsnt_n_pdd0 { | |
| 1625 | nvidia,pins = "pex_l0_prsnt_n_pdd0"; | |
| 1626 | nvidia,function = "pcie"; | |
| 1627 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1629 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1630 | }; | |
| 1631 | pex_l0_rst_n_pdd1 { | |
| 1632 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
| 1633 | nvidia,function = "pcie"; | |
| 1634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1636 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1637 | }; | |
| 1638 | pex_l0_clkreq_n_pdd2 { | |
| 1639 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
| 1640 | nvidia,function = "pcie"; | |
| a47c662a LD |
1641 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 3d03203a LS |
1643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1644 | }; | |
| 1645 | pex_wake_n_pdd3 { | |
| 1646 | nvidia,pins = "pex_wake_n_pdd3"; | |
| 1647 | nvidia,function = "pcie"; | |
| 1648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1650 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| d7df69fe | 1651 | }; |
| cc34c9f7 | 1652 | pex_l1_prsnt_n_pdd4 { |
| 3d03203a LS |
1653 | nvidia,pins = "pex_l1_prsnt_n_pdd4"; |
| 1654 | nvidia,function = "pcie"; | |
| 1655 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1658 | }; | |
| 1659 | pex_l1_rst_n_pdd5 { | |
| 1660 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
| 1661 | nvidia,function = "pcie"; | |
| 1662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1664 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1665 | }; | |
| 1666 | pex_l1_clkreq_n_pdd6 { | |
| 1667 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
| 1668 | nvidia,function = "pcie"; | |
| a47c662a | 1669 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 3d03203a LS |
1670 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1671 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1672 | }; | |
| 1673 | pex_l2_prsnt_n_pdd7 { | |
| 1674 | nvidia,pins = "pex_l2_prsnt_n_pdd7"; | |
| 1675 | nvidia,function = "pcie"; | |
| 1676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1678 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1679 | }; | |
| 1680 | clk3_out_pee0 { | |
| 1681 | nvidia,pins = "clk3_out_pee0"; | |
| 1682 | nvidia,function = "extperiph3"; | |
| 1683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1685 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1686 | }; | |
| 1687 | clk3_req_pee1 { | |
| 1688 | nvidia,pins = "clk3_req_pee1"; | |
| 1689 | nvidia,function = "dev3"; | |
| 1690 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1691 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1692 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1693 | }; | |
| 1694 | clk1_req_pee2 { | |
| 1695 | nvidia,pins = "clk1_req_pee2"; | |
| 1696 | nvidia,function = "dap"; | |
| 1697 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1699 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1700 | }; | |
| 1701 | hdmi_cec_pee3 { | |
| 1702 | nvidia,pins = "hdmi_cec_pee3"; | |
| 1703 | nvidia,function = "cec"; | |
| 1704 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1705 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1706 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1707 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 1708 | }; | |
| 1709 | owr { | |
| 1710 | nvidia,pins = "owr"; | |
| 1711 | nvidia,function = "owr"; | |
| 1712 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1713 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1714 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| cc34c9f7 | 1715 | }; |
| d7df69fe BW |
1716 | sdio3 { |
| 1717 | nvidia,pins = "drive_sdio3"; | |
| a47c662a LD |
1718 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 1719 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| d7df69fe BW |
1720 | nvidia,pull-down-strength = <46>; |
| 1721 | nvidia,pull-up-strength = <42>; | |
| 1722 | nvidia,slew-rate-rising = <1>; | |
| 1723 | nvidia,slew-rate-falling = <1>; | |
| 1724 | }; | |
| cc34c9f7 TT |
1725 | gpv { |
| 1726 | nvidia,pins = "drive_gpv"; | |
| 1727 | nvidia,pull-up-strength = <16>; | |
| 1728 | }; | |
| d7df69fe BW |
1729 | }; |
| 1730 | }; | |
| 1731 | ||
| 1732 | serial@70006000 { | |
| 1733 | status = "okay"; | |
| d7df69fe BW |
1734 | }; |
| 1735 | ||
| 1736 | i2c@7000c000 { | |
| 1737 | status = "okay"; | |
| 1738 | clock-frequency = <100000>; | |
| 1739 | }; | |
| 1740 | ||
| 1741 | i2c@7000c400 { | |
| 1742 | status = "okay"; | |
| 1743 | clock-frequency = <100000>; | |
| 1744 | }; | |
| 1745 | ||
| 1746 | i2c@7000c500 { | |
| 1747 | status = "okay"; | |
| 1748 | clock-frequency = <100000>; | |
| 1749 | }; | |
| 1750 | ||
| 9bd80b41 | 1751 | hdmiddc: i2c@7000c700 { |
| d7df69fe BW |
1752 | status = "okay"; |
| 1753 | clock-frequency = <100000>; | |
| 1754 | }; | |
| 1755 | ||
| 1756 | i2c@7000d000 { | |
| 1757 | status = "okay"; | |
| 1758 | clock-frequency = <100000>; | |
| 1759 | ||
| 58ecb23f | 1760 | rt5640: rt5640@1c { |
| 23037bbd SW |
1761 | compatible = "realtek,rt5640"; |
| 1762 | reg = <0x1c>; | |
| 1763 | interrupt-parent = <&gpio>; | |
| 1764 | interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; | |
| 1765 | realtek,ldo1-en-gpios = | |
| 1766 | <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; | |
| 1767 | }; | |
| 1768 | ||
| d7df69fe BW |
1769 | pmic: tps65911@2d { |
| 1770 | compatible = "ti,tps65911"; | |
| 1771 | reg = <0x2d>; | |
| 1772 | ||
| 6cecf916 | 1773 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| d7df69fe BW |
1774 | #interrupt-cells = <2>; |
| 1775 | interrupt-controller; | |
| 1776 | ||
| 1777 | ti,system-power-controller; | |
| 1778 | ||
| 1779 | #gpio-cells = <2>; | |
| 1780 | gpio-controller; | |
| 1781 | ||
| 1782 | vcc1-supply = <&vdd_5v_in_reg>; | |
| 1783 | vcc2-supply = <&vdd_5v_in_reg>; | |
| 1784 | vcc3-supply = <&vio_reg>; | |
| 1785 | vcc4-supply = <&vdd_5v_in_reg>; | |
| 1786 | vcc5-supply = <&vdd_5v_in_reg>; | |
| 1787 | vcc6-supply = <&vdd2_reg>; | |
| 1788 | vcc7-supply = <&vdd_5v_in_reg>; | |
| 1789 | vccio-supply = <&vdd_5v_in_reg>; | |
| 1790 | ||
| 1791 | regulators { | |
| 1792 | #address-cells = <1>; | |
| 1793 | #size-cells = <0>; | |
| 1794 | ||
| 1795 | vdd1_reg: vdd1 { | |
| 1796 | regulator-name = "vddio_ddr_1v2"; | |
| 1797 | regulator-min-microvolt = <1200000>; | |
| 1798 | regulator-max-microvolt = <1200000>; | |
| 1799 | regulator-always-on; | |
| 1800 | }; | |
| 1801 | ||
| 1802 | vdd2_reg: vdd2 { | |
| 1803 | regulator-name = "vdd_1v5_gen"; | |
| 1804 | regulator-min-microvolt = <1500000>; | |
| 1805 | regulator-max-microvolt = <1500000>; | |
| 1806 | regulator-always-on; | |
| 1807 | }; | |
| 1808 | ||
| 1809 | vddctrl_reg: vddctrl { | |
| 1810 | regulator-name = "vdd_cpu,vdd_sys"; | |
| 1811 | regulator-min-microvolt = <1000000>; | |
| 1812 | regulator-max-microvolt = <1000000>; | |
| 1813 | regulator-always-on; | |
| 1814 | }; | |
| 1815 | ||
| 1816 | vio_reg: vio { | |
| 1817 | regulator-name = "vdd_1v8_gen"; | |
| 1818 | regulator-min-microvolt = <1800000>; | |
| 1819 | regulator-max-microvolt = <1800000>; | |
| 1820 | regulator-always-on; | |
| 1821 | }; | |
| 1822 | ||
| 1823 | ldo1_reg: ldo1 { | |
| 1824 | regulator-name = "vdd_pexa,vdd_pexb"; | |
| 1825 | regulator-min-microvolt = <1050000>; | |
| 1826 | regulator-max-microvolt = <1050000>; | |
| 1827 | }; | |
| 1828 | ||
| 1829 | ldo2_reg: ldo2 { | |
| 1830 | regulator-name = "vdd_sata,avdd_plle"; | |
| 1831 | regulator-min-microvolt = <1050000>; | |
| 1832 | regulator-max-microvolt = <1050000>; | |
| 1833 | }; | |
| 1834 | ||
| 1835 | /* LDO3 is not connected to anything */ | |
| 1836 | ||
| 1837 | ldo4_reg: ldo4 { | |
| 1838 | regulator-name = "vdd_rtc"; | |
| 1839 | regulator-min-microvolt = <1200000>; | |
| 1840 | regulator-max-microvolt = <1200000>; | |
| 1841 | regulator-always-on; | |
| 1842 | }; | |
| 1843 | ||
| 1844 | ldo5_reg: ldo5 { | |
| 1845 | regulator-name = "vddio_sdmmc,avdd_vdac"; | |
| 5eb49534 | 1846 | regulator-min-microvolt = <1800000>; |
| d7df69fe BW |
1847 | regulator-max-microvolt = <3300000>; |
| 1848 | regulator-always-on; | |
| 1849 | }; | |
| 1850 | ||
| 1851 | ldo6_reg: ldo6 { | |
| 1852 | regulator-name = "avdd_dsi_csi,pwrdet_mipi"; | |
| 1853 | regulator-min-microvolt = <1200000>; | |
| 1854 | regulator-max-microvolt = <1200000>; | |
| 1855 | }; | |
| 1856 | ||
| 1857 | ldo7_reg: ldo7 { | |
| 1858 | regulator-name = "vdd_pllm,x,u,a_p_c_s"; | |
| 1859 | regulator-min-microvolt = <1200000>; | |
| 1860 | regulator-max-microvolt = <1200000>; | |
| 1861 | regulator-always-on; | |
| 1862 | }; | |
| 1863 | ||
| 1864 | ldo8_reg: ldo8 { | |
| 1865 | regulator-name = "vdd_ddr_hs"; | |
| 1866 | regulator-min-microvolt = <1000000>; | |
| 1867 | regulator-max-microvolt = <1000000>; | |
| 1868 | regulator-always-on; | |
| 1869 | }; | |
| 1870 | }; | |
| 1871 | }; | |
| 57899053 SW |
1872 | |
| 1873 | tps62361@60 { | |
| 1874 | compatible = "ti,tps62361"; | |
| 1875 | reg = <0x60>; | |
| 1876 | ||
| 1877 | regulator-name = "tps62361-vout"; | |
| 1878 | regulator-min-microvolt = <500000>; | |
| 1879 | regulator-max-microvolt = <1500000>; | |
| 1880 | regulator-boot-on; | |
| 1881 | regulator-always-on; | |
| 1882 | ti,vsel0-state-high; | |
| 1883 | ti,vsel1-state-high; | |
| 1884 | }; | |
| d7df69fe BW |
1885 | }; |
| 1886 | ||
| 1887 | spi@7000da00 { | |
| 1888 | status = "okay"; | |
| 1889 | spi-max-frequency = <25000000>; | |
| 1890 | spi-flash@1 { | |
| 1891 | compatible = "winbond,w25q32"; | |
| 1892 | reg = <1>; | |
| 1893 | spi-max-frequency = <20000000>; | |
| 1894 | }; | |
| 1895 | }; | |
| 1896 | ||
| 58ecb23f | 1897 | pmc@7000e400 { |
| d7df69fe BW |
1898 | status = "okay"; |
| 1899 | nvidia,invert-interrupt; | |
| 47d2d63b | 1900 | nvidia,suspend-mode = <1>; |
| a44a019d JL |
1901 | nvidia,cpu-pwr-good-time = <2000>; |
| 1902 | nvidia,cpu-pwr-off-time = <200>; | |
| 1903 | nvidia,core-pwr-good-time = <3845 3845>; | |
| 1904 | nvidia,core-pwr-off-time = <0>; | |
| 1905 | nvidia,core-power-req-active-high; | |
| 1906 | nvidia,sys-clock-req-active-high; | |
| d7df69fe BW |
1907 | }; |
| 1908 | ||
| 57899053 SW |
1909 | ahub@70080000 { |
| 1910 | i2s@70080400 { | |
| 1911 | status = "okay"; | |
| 1912 | }; | |
| 1913 | }; | |
| 1914 | ||
| d7df69fe BW |
1915 | sdhci@78000000 { |
| 1916 | status = "okay"; | |
| 5eb49534 | 1917 | vqmmc-supply = <&ldo5_reg>; |
| 3325f1bc SW |
1918 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 1919 | wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; | |
| 1920 | power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; | |
| d7df69fe BW |
1921 | bus-width = <4>; |
| 1922 | }; | |
| 1923 | ||
| 1924 | sdhci@78000600 { | |
| 1925 | status = "okay"; | |
| 1926 | bus-width = <8>; | |
| 7a2617a6 | 1927 | non-removable; |
| d7df69fe BW |
1928 | }; |
| 1929 | ||
| 4c696500 EB |
1930 | usb@7d004000 { |
| 1931 | status = "okay"; | |
| 1932 | }; | |
| 1933 | ||
| 1934 | phy2: usb-phy@7d004000 { | |
| 1935 | vbus-supply = <&sys_3v3_reg>; | |
| 1936 | status = "okay"; | |
| 1937 | }; | |
| 1938 | ||
| cc34c9f7 TT |
1939 | usb@7d008000 { |
| 1940 | status = "okay"; | |
| 1941 | }; | |
| 1942 | ||
| 1943 | usb-phy@7d008000 { | |
| 1944 | vbus-supply = <&usb3_vbus_reg>; | |
| 1945 | status = "okay"; | |
| 1946 | }; | |
| 1947 | ||
| 7021d122 JL |
1948 | clocks { |
| 1949 | compatible = "simple-bus"; | |
| 1950 | #address-cells = <1>; | |
| 1951 | #size-cells = <0>; | |
| 1952 | ||
| 58ecb23f | 1953 | clk32k_in: clock@0 { |
| 7021d122 | 1954 | compatible = "fixed-clock"; |
| 4ec2e601 | 1955 | reg = <0>; |
| 7021d122 JL |
1956 | #clock-cells = <0>; |
| 1957 | clock-frequency = <32768>; | |
| 1958 | }; | |
| 1959 | }; | |
| 1960 | ||
| 57899053 SW |
1961 | gpio-leds { |
| 1962 | compatible = "gpio-leds"; | |
| 1963 | ||
| 1964 | gpled1 { | |
| 1965 | label = "LED1"; /* CR5A1 (blue) */ | |
| 1966 | gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; | |
| 1967 | }; | |
| 1968 | gpled2 { | |
| 1969 | label = "LED2"; /* CR4A2 (green) */ | |
| 1970 | gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; | |
| 1971 | }; | |
| 1972 | }; | |
| 1973 | ||
| d7df69fe BW |
1974 | regulators { |
| 1975 | compatible = "simple-bus"; | |
| 1976 | #address-cells = <1>; | |
| 1977 | #size-cells = <0>; | |
| 1978 | ||
| 1979 | vdd_5v_in_reg: regulator@0 { | |
| 1980 | compatible = "regulator-fixed"; | |
| 1981 | reg = <0>; | |
| 1982 | regulator-name = "vdd_5v_in"; | |
| 1983 | regulator-min-microvolt = <5000000>; | |
| 1984 | regulator-max-microvolt = <5000000>; | |
| 1985 | regulator-always-on; | |
| 1986 | }; | |
| 1987 | ||
| 1988 | chargepump_5v_reg: regulator@1 { | |
| 1989 | compatible = "regulator-fixed"; | |
| 1990 | reg = <1>; | |
| 1991 | regulator-name = "chargepump_5v"; | |
| 1992 | regulator-min-microvolt = <5000000>; | |
| 1993 | regulator-max-microvolt = <5000000>; | |
| 1994 | regulator-boot-on; | |
| 1995 | regulator-always-on; | |
| 1996 | enable-active-high; | |
| 3325f1bc | 1997 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
1998 | }; |
| 1999 | ||
| 2000 | ddr_reg: regulator@2 { | |
| 2001 | compatible = "regulator-fixed"; | |
| 2002 | reg = <2>; | |
| 2003 | regulator-name = "vdd_ddr"; | |
| 2004 | regulator-min-microvolt = <1500000>; | |
| 2005 | regulator-max-microvolt = <1500000>; | |
| 2006 | regulator-always-on; | |
| 2007 | regulator-boot-on; | |
| 2008 | enable-active-high; | |
| 3325f1bc | 2009 | gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2010 | vin-supply = <&vdd_5v_in_reg>; |
| 2011 | }; | |
| 2012 | ||
| 2013 | vdd_5v_sata_reg: regulator@3 { | |
| 2014 | compatible = "regulator-fixed"; | |
| 2015 | reg = <3>; | |
| 2016 | regulator-name = "vdd_5v_sata"; | |
| 2017 | regulator-min-microvolt = <5000000>; | |
| 2018 | regulator-max-microvolt = <5000000>; | |
| 2019 | regulator-always-on; | |
| 2020 | regulator-boot-on; | |
| 2021 | enable-active-high; | |
| 3325f1bc | 2022 | gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2023 | vin-supply = <&vdd_5v_in_reg>; |
| 2024 | }; | |
| 2025 | ||
| 2026 | usb1_vbus_reg: regulator@4 { | |
| 2027 | compatible = "regulator-fixed"; | |
| 2028 | reg = <4>; | |
| 2029 | regulator-name = "usb1_vbus"; | |
| 2030 | regulator-min-microvolt = <5000000>; | |
| 2031 | regulator-max-microvolt = <5000000>; | |
| 2032 | enable-active-high; | |
| cc34c9f7 | 2033 | gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2034 | gpio-open-drain; |
| 2035 | vin-supply = <&vdd_5v_in_reg>; | |
| 2036 | }; | |
| 2037 | ||
| 2038 | usb3_vbus_reg: regulator@5 { | |
| 2039 | compatible = "regulator-fixed"; | |
| 2040 | reg = <5>; | |
| 2041 | regulator-name = "usb3_vbus"; | |
| 2042 | regulator-min-microvolt = <5000000>; | |
| 2043 | regulator-max-microvolt = <5000000>; | |
| 2044 | enable-active-high; | |
| cc34c9f7 | 2045 | gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2046 | gpio-open-drain; |
| 2047 | vin-supply = <&vdd_5v_in_reg>; | |
| 2048 | }; | |
| 2049 | ||
| 2050 | sys_3v3_reg: regulator@6 { | |
| 2051 | compatible = "regulator-fixed"; | |
| 2052 | reg = <6>; | |
| 2053 | regulator-name = "sys_3v3,vdd_3v3_alw"; | |
| 2054 | regulator-min-microvolt = <3300000>; | |
| 2055 | regulator-max-microvolt = <3300000>; | |
| 2056 | regulator-always-on; | |
| 2057 | regulator-boot-on; | |
| 2058 | enable-active-high; | |
| 3325f1bc | 2059 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2060 | vin-supply = <&vdd_5v_in_reg>; |
| 2061 | }; | |
| 2062 | ||
| 2063 | sys_3v3_pexs_reg: regulator@7 { | |
| 2064 | compatible = "regulator-fixed"; | |
| 2065 | reg = <7>; | |
| 2066 | regulator-name = "sys_3v3_pexs"; | |
| 2067 | regulator-min-microvolt = <3300000>; | |
| 2068 | regulator-max-microvolt = <3300000>; | |
| 2069 | regulator-always-on; | |
| 2070 | regulator-boot-on; | |
| 2071 | enable-active-high; | |
| 3325f1bc | 2072 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
| d7df69fe BW |
2073 | vin-supply = <&sys_3v3_reg>; |
| 2074 | }; | |
| 597eb8e1 TR |
2075 | |
| 2076 | vdd_5v0_hdmi: regulator@8 { | |
| 2077 | compatible = "regulator-fixed"; | |
| 2078 | reg = <8>; | |
| 2079 | regulator-name = "+VDD_5V_HDMI"; | |
| 2080 | regulator-min-microvolt = <5000000>; | |
| 2081 | regulator-max-microvolt = <5000000>; | |
| 2082 | regulator-always-on; | |
| 2083 | regulator-boot-on; | |
| 2084 | vin-supply = <&sys_3v3_reg>; | |
| 2085 | }; | |
| d7df69fe | 2086 | }; |
| b4dd3e0c | 2087 | |
| 23037bbd SW |
2088 | sound { |
| 2089 | compatible = "nvidia,tegra-audio-rt5640-beaver", | |
| 2090 | "nvidia,tegra-audio-rt5640"; | |
| 2091 | nvidia,model = "NVIDIA Tegra Beaver"; | |
| 2092 | ||
| 2093 | nvidia,audio-routing = | |
| 2094 | "Headphones", "HPOR", | |
| ac472284 SW |
2095 | "Headphones", "HPOL", |
| 2096 | "Mic Jack", "MICBIAS1", | |
| 2097 | "IN2P", "Mic Jack"; | |
| 23037bbd SW |
2098 | |
| 2099 | nvidia,i2s-controller = <&tegra_i2s1>; | |
| 2100 | nvidia,audio-codec = <&rt5640>; | |
| 2101 | ||
| 2102 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
| 2103 | ||
| 2104 | clocks = <&tegra_car TEGRA30_CLK_PLL_A>, | |
| 2105 | <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, | |
| 2106 | <&tegra_car TEGRA30_CLK_EXTERN1>; | |
| 2107 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
| 2108 | }; | |
| d7df69fe | 2109 | }; |