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Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
5780c206 2#include <dt-bindings/input/input.h>
1bd0bd49 3#include "tegra30.dtsi"
64c4e9f8 4
640a7af5
LD		 5/**
6 * This file contains common DT entry for all fab version of Cardhu.
7 * There is multiple fab version of Cardhu starting from A01 to A07.
8 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
9 * A02 will have different sets of GPIOs for fixed regulator compare to
10 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
11 * compatible with fab version A04. Based on Cardhu fab version, the
12 * related dts file need to be chosen like for Cardhu fab version A02,
13 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
14 * tegra30-cardhu-a04.dts.
15 * The identification of board is done in two ways, by looking the sticker
16 * on PCB and by reading board id eeprom.
db374069 17 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
640a7af5
LD		 18 * number is the fab version like here it is 002 and hence fab version A02.
19 * The (downstream internal) U-Boot of Cardhu display the board-id as
20 * follows:
21 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
22 * In this Fab version is 02 i.e. A02.
23 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
24 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
25 * wide.
26 */
27
64c4e9f8
PDS		 28/ {
29 model = "NVIDIA Tegra30 Cardhu evaluation board";
30 compatible = "nvidia,cardhu", "nvidia,tegra30";
31
553c0a20 32 aliases {
763fbff2 33 rtc0 = "/i2c@7000d000/tps65911@2d";
553c0a20 34 rtc1 = "/rtc@7000e000";
c4574aa0
OJ		 35 serial0 = &uarta;
36 serial1 = &uartc;
553c0a20
SW		 37 };
38
f5bbb327
JH		 39 chosen {
40 stdout-path = "serial0:115200n8";
41 };
42
48299769 43 memory@80000000 {
95decf84 44 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 45 };
46
508d690e 47 pcie@3000 {
89e7ada4 48 status = "okay";
cca8614d
TR		 49
50 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
51 avdd-pexb-supply = <&ldo1_reg>;
52 vdd-pexb-supply = <&ldo1_reg>;
53 avdd-pex-pll-supply = <&ldo1_reg>;
54 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
55 vddio-pex-ctl-supply = <&sys_3v3_reg>;
56 avdd-plle-supply = <&ldo2_reg>;
57
89e7ada4
JA		 58 pci@1,0 {
59 nvidia,num-lanes = <4>;
60 };
61
62 pci@2,0 {
63 nvidia,num-lanes = <1>;
64 };
65
66 pci@3,0 {
67 status = "okay";
68 nvidia,num-lanes = <1>;
69 };
70 };
71
02b1fea2
TR		 72 host1x@50000000 {
73 dc@54200000 {
74 rgb {
75 status = "okay";
76
77 nvidia,panel = <&panel>;
78 };
79 };
80 };
81
58ecb23f 82 pinmux@70000868 {
e5cbeef0
SW		 83 pinctrl-names = "default";
84 pinctrl-0 = <&state_default>;
85
86 state_default: pinmux {
87 sdmmc1_clk_pz0 {
88 nvidia,pins = "sdmmc1_clk_pz0";
89 nvidia,function = "sdmmc1";
a47c662a
LD		 90 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 92 };
93 sdmmc1_cmd_pz1 {
94 nvidia,pins = "sdmmc1_cmd_pz1",
95 "sdmmc1_dat0_py7",
96 "sdmmc1_dat1_py6",
97 "sdmmc1_dat2_py5",
98 "sdmmc1_dat3_py4";
99 nvidia,function = "sdmmc1";
a47c662a
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 102 };
6fb11131
WN		 103 sdmmc3_clk_pa6 {
104 nvidia,pins = "sdmmc3_clk_pa6";
105 nvidia,function = "sdmmc3";
a47c662a
LD		 106 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 108 };
109 sdmmc3_cmd_pa7 {
110 nvidia,pins = "sdmmc3_cmd_pa7",
111 "sdmmc3_dat0_pb7",
112 "sdmmc3_dat1_pb6",
113 "sdmmc3_dat2_pb5",
114 "sdmmc3_dat3_pb4";
115 nvidia,function = "sdmmc3";
a47c662a
LD		 116 nvidia,pull = <TEGRA_PIN_PULL_UP>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 118 };
e5cbeef0
SW		 119 sdmmc4_clk_pcc4 {
120 nvidia,pins = "sdmmc4_clk_pcc4",
121 "sdmmc4_rst_n_pcc3";
122 nvidia,function = "sdmmc4";
a47c662a
LD		 123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 125 };
126 sdmmc4_dat0_paa0 {
127 nvidia,pins = "sdmmc4_dat0_paa0",
128 "sdmmc4_dat1_paa1",
129 "sdmmc4_dat2_paa2",
130 "sdmmc4_dat3_paa3",
131 "sdmmc4_dat4_paa4",
132 "sdmmc4_dat5_paa5",
133 "sdmmc4_dat6_paa6",
134 "sdmmc4_dat7_paa7";
135 nvidia,function = "sdmmc4";
a47c662a
LD		 136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 138 };
8c6a3852
SW		 139 dap2_fs_pa2 {
140 nvidia,pins = "dap2_fs_pa2",
141 "dap2_sclk_pa3",
142 "dap2_din_pa4",
143 "dap2_dout_pa5";
144 nvidia,function = "i2s1";
a47c662a
LD		 145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 147 };
6fb11131
WN		 148 sdio3 {
149 nvidia,pins = "drive_sdio3";
a47c662a
LD		 150 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
151 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 152 nvidia,pull-down-strength = <46>;
153 nvidia,pull-up-strength = <42>;
a47c662a
LD		 154 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
155 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 156 };
ecfd6c7f
LD		 157 uart3_txd_pw6 {
158 nvidia,pins = "uart3_txd_pw6",
159 "uart3_cts_n_pa1",
160 "uart3_rts_n_pc0",
161 "uart3_rxd_pw7";
162 nvidia,function = "uartc";
a47c662a
LD		 163 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 165 };
e5cbeef0
SW		 166 };
167 };
168
64c4e9f8 169 serial@70006000 {
2a5fdc9a 170 status = "okay";
64c4e9f8
PDS		 171 };
172
ecfd6c7f
LD		 173 serial@70006200 {
174 compatible = "nvidia,tegra30-hsuart";
175 status = "okay";
ecfd6c7f
LD		 176 };
177
02b1fea2
TR		 178 pwm@7000a000 {
179 status = "okay";
180 };
181
182 panelddc: i2c@7000c000 {
2a5fdc9a 183 status = "okay";
64c4e9f8
PDS		 184 clock-frequency = <100000>;
185 };
186
187 i2c@7000c400 {
2a5fdc9a 188 status = "okay";
64c4e9f8
PDS		 189 clock-frequency = <100000>;
190 };
191
192 i2c@7000c500 {
2a5fdc9a 193 status = "okay";
64c4e9f8 194 clock-frequency = <100000>;
b46b0b54
LD		 195
196 /* ALS and Proximity sensor */
197 isl29028@44 {
62981239 198 compatible = "isil,isl29028";
b46b0b54
LD		 199 reg = <0x44>;
200 interrupt-parent = <&gpio>;
6cecf916 201 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 202 };
40431d16
BW		 203
204 i2cmux@70 {
205 compatible = "nxp,pca9546";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <0x70>;
6e181190 209 reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
40431d16 210 };
64c4e9f8
PDS		 211 };
212
213 i2c@7000c700 {
2a5fdc9a 214 status = "okay";
64c4e9f8
PDS		 215 clock-frequency = <100000>;
216 };
217
218 i2c@7000d000 {
2a5fdc9a 219 status = "okay";
64c4e9f8 220 clock-frequency = <100000>;
8c6a3852
SW		 221
222 wm8903: wm8903@1a {
223 compatible = "wlf,wm8903";
224 reg = <0x1a>;
225 interrupt-parent = <&gpio>;
6cecf916 226 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 227
228 gpio-controller;
229 #gpio-cells = <2>;
230
231 micdet-cfg = <0>;
232 micdet-delay = <100>;
233 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
234 };
331da58c 235
167e6279
LD		 236 pmic: tps65911@2d {
237 compatible = "ti,tps65911";
238 reg = <0x2d>;
239
6cecf916 240 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 241 #interrupt-cells = <2>;
242 interrupt-controller;
243
44b12ef7
SW		 244 ti,system-power-controller;
245
167e6279
LD		 246 #gpio-cells = <2>;
247 gpio-controller;
248
249 vcc1-supply = <&vdd_ac_bat_reg>;
250 vcc2-supply = <&vdd_ac_bat_reg>;
251 vcc3-supply = <&vio_reg>;
fa4a9252 252 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 253 vcc5-supply = <&vdd_ac_bat_reg>;
254 vcc6-supply = <&vdd2_reg>;
255 vcc7-supply = <&vdd_ac_bat_reg>;
256 vccio-supply = <&vdd_ac_bat_reg>;
257
258 regulators {
b9c665d7 259 vdd1_reg: vdd1 {
167e6279
LD		 260 regulator-name = "vddio_ddr_1v2";
261 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>;
263 regulator-always-on;
264 };
265
b9c665d7 266 vdd2_reg: vdd2 {
167e6279
LD		 267 regulator-name = "vdd_1v5_gen";
268 regulator-min-microvolt = <1500000>;
269 regulator-max-microvolt = <1500000>;
270 regulator-always-on;
271 };
272
b9c665d7 273 vddctrl_reg: vddctrl {
167e6279
LD		 274 regulator-name = "vdd_cpu,vdd_sys";
275 regulator-min-microvolt = <1000000>;
276 regulator-max-microvolt = <1000000>;
277 regulator-always-on;
278 };
279
b9c665d7 280 vio_reg: vio {
167e6279
LD		 281 regulator-name = "vdd_1v8_gen";
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <1800000>;
284 regulator-always-on;
285 };
286
b9c665d7 287 ldo1_reg: ldo1 {
167e6279
LD		 288 regulator-name = "vdd_pexa,vdd_pexb";
289 regulator-min-microvolt = <1050000>;
290 regulator-max-microvolt = <1050000>;
291 };
292
b9c665d7 293 ldo2_reg: ldo2 {
167e6279
LD		 294 regulator-name = "vdd_sata,avdd_plle";
295 regulator-min-microvolt = <1050000>;
296 regulator-max-microvolt = <1050000>;
297 };
298
299 /* LDO3 is not connected to anything */
300
b9c665d7 301 ldo4_reg: ldo4 {
167e6279
LD		 302 regulator-name = "vdd_rtc";
303 regulator-min-microvolt = <1200000>;
304 regulator-max-microvolt = <1200000>;
305 regulator-always-on;
306 };
307
b9c665d7 308 ldo5_reg: ldo5 {
fa4a9252
LD		 309 regulator-name = "vddio_sdmmc,avdd_vdac";
310 regulator-min-microvolt = <3300000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-always-on;
313 };
314
b9c665d7 315 ldo6_reg: ldo6 {
167e6279
LD		 316 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
317 regulator-min-microvolt = <1200000>;
318 regulator-max-microvolt = <1200000>;
319 };
320
b9c665d7 321 ldo7_reg: ldo7 {
167e6279
LD		 322 regulator-name = "vdd_pllm,x,u,a_p_c_s";
323 regulator-min-microvolt = <1200000>;
324 regulator-max-microvolt = <1200000>;
325 regulator-always-on;
326 };
327
b9c665d7 328 ldo8_reg: ldo8 {
167e6279
LD		 329 regulator-name = "vdd_ddr_hs";
330 regulator-min-microvolt = <1000000>;
331 regulator-max-microvolt = <1000000>;
332 regulator-always-on;
333 };
334 };
335 };
74ecab27 336
7c7de6b0 337 temperature-sensor@4c {
74ecab27
WN		 338 compatible = "onnn,nct1008";
339 reg = <0x4c>;
7c7de6b0 340 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 341 interrupt-parent = <&gpio>;
342 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
343 };
2b8584d5 344
58ecb23f 345 tps62361@60 {
2b8584d5
SW		 346 compatible = "ti,tps62361";
347 reg = <0x60>;
348
349 regulator-name = "tps62361-vout";
350 regulator-min-microvolt = <500000>;
351 regulator-max-microvolt = <1500000>;
352 regulator-boot-on;
353 regulator-always-on;
354 ti,vsel0-state-high;
355 ti,vsel1-state-high;
356 };
64c4e9f8 357 };
850c4c8f 358
c42cb1c3
LD		 359 spi@7000da00 {
360 status = "okay";
361 spi-max-frequency = <25000000>;
362 spi-flash@1 {
de45b787 363 compatible = "winbond,w25q32", "jedec,spi-nor";
c42cb1c3
LD		 364 reg = <1>;
365 spi-max-frequency = <20000000>;
366 };
367 };
368
58ecb23f 369 pmc@7000e400 {
167e6279
LD		 370 status = "okay";
371 nvidia,invert-interrupt;
47d2d63b 372 nvidia,suspend-mode = <1>;
a44a019d
JL		 373 nvidia,cpu-pwr-good-time = <2000>;
374 nvidia,cpu-pwr-off-time = <200>;
375 nvidia,core-pwr-good-time = <3845 3845>;
376 nvidia,core-pwr-off-time = <0>;
377 nvidia,core-power-req-active-high;
378 nvidia,sys-clock-req-active-high;
167e6279
LD		 379 };
380
57899053
SW		 381 ahub@70080000 {
382 i2s@70080400 {
383 status = "okay";
384 };
385 };
386
c04abb3a 387 sdhci@78000000 {
2a5fdc9a 388 status = "okay";
3325f1bc
SW		 389 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
390 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
391 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 392 bus-width = <4>;
c04abb3a
SW		 393 };
394
c04abb3a 395 sdhci@78000600 {
2a5fdc9a 396 status = "okay";
7f217794 397 bus-width = <8>;
7a2617a6 398 non-removable;
c04abb3a
SW		 399 };
400
cc34c9f7
TT		 401 usb@7d008000 {
402 status = "okay";
403 };
404
405 usb-phy@7d008000 {
406 vbus-supply = <&usb3_vbus_reg>;
407 status = "okay";
408 };
409
02b1fea2
TR		 410 backlight: backlight {
411 compatible = "pwm-backlight";
412
413 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
414 power-supply = <&vdd_bl_reg>;
415 pwms = <&pwm 0 5000000>;
416
417 brightness-levels = <0 4 8 16 32 64 128 255>;
418 default-brightness-level = <6>;
419 };
420
7021d122
JL		 421 clocks {
422 compatible = "simple-bus";
423 #address-cells = <1>;
424 #size-cells = <0>;
425
58ecb23f 426 clk32k_in: clock@0 {
7021d122 427 compatible = "fixed-clock";
4ec2e601 428 reg = <0>;
7021d122
JL		 429 #clock-cells = <0>;
430 clock-frequency = <32768>;
431 };
432 };
433
02b1fea2
TR		 434 panel: panel {
435 compatible = "chunghwa,claa101wb01", "simple-panel";
436 ddc-i2c-bus = <&panelddc>;
437
438 power-supply = <&vdd_pnl1_reg>;
439 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
440
441 backlight = <&backlight>;
442 };
443
167e6279
LD		 444 regulators {
445 compatible = "simple-bus";
446 #address-cells = <1>;
447 #size-cells = <0>;
448
449 vdd_ac_bat_reg: regulator@0 {
450 compatible = "regulator-fixed";
451 reg = <0>;
452 regulator-name = "vdd_ac_bat";
453 regulator-min-microvolt = <5000000>;
454 regulator-max-microvolt = <5000000>;
455 regulator-always-on;
456 };
fa4a9252
LD		 457
458 cam_1v8_reg: regulator@1 {
459 compatible = "regulator-fixed";
460 reg = <1>;
461 regulator-name = "cam_1v8";
462 regulator-min-microvolt = <1800000>;
463 regulator-max-microvolt = <1800000>;
464 enable-active-high;
3325f1bc 465 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 466 vin-supply = <&vio_reg>;
467 };
468
469 cp_5v_reg: regulator@2 {
470 compatible = "regulator-fixed";
471 reg = <2>;
472 regulator-name = "cp_5v";
473 regulator-min-microvolt = <5000000>;
474 regulator-max-microvolt = <5000000>;
475 regulator-boot-on;
476 regulator-always-on;
477 enable-active-high;
3325f1bc 478 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 479 };
480
481 emmc_3v3_reg: regulator@3 {
482 compatible = "regulator-fixed";
483 reg = <3>;
484 regulator-name = "emmc_3v3";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 regulator-boot-on;
489 enable-active-high;
3325f1bc 490 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 491 vin-supply = <&sys_3v3_reg>;
492 };
493
494 modem_3v3_reg: regulator@4 {
495 compatible = "regulator-fixed";
496 reg = <4>;
497 regulator-name = "modem_3v3";
498 regulator-min-microvolt = <3300000>;
499 regulator-max-microvolt = <3300000>;
500 enable-active-high;
3325f1bc 501 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 502 };
503
504 pex_hvdd_3v3_reg: regulator@5 {
505 compatible = "regulator-fixed";
506 reg = <5>;
507 regulator-name = "pex_hvdd_3v3";
508 regulator-min-microvolt = <3300000>;
509 regulator-max-microvolt = <3300000>;
510 enable-active-high;
3325f1bc 511 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 512 vin-supply = <&sys_3v3_reg>;
513 };
514
515 vdd_cam1_ldo_reg: regulator@6 {
516 compatible = "regulator-fixed";
517 reg = <6>;
518 regulator-name = "vdd_cam1_ldo";
519 regulator-min-microvolt = <2800000>;
520 regulator-max-microvolt = <2800000>;
521 enable-active-high;
3325f1bc 522 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 523 vin-supply = <&sys_3v3_reg>;
524 };
525
526 vdd_cam2_ldo_reg: regulator@7 {
527 compatible = "regulator-fixed";
528 reg = <7>;
529 regulator-name = "vdd_cam2_ldo";
530 regulator-min-microvolt = <2800000>;
531 regulator-max-microvolt = <2800000>;
532 enable-active-high;
3325f1bc 533 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 534 vin-supply = <&sys_3v3_reg>;
535 };
536
537 vdd_cam3_ldo_reg: regulator@8 {
538 compatible = "regulator-fixed";
539 reg = <8>;
540 regulator-name = "vdd_cam3_ldo";
541 regulator-min-microvolt = <3300000>;
542 regulator-max-microvolt = <3300000>;
543 enable-active-high;
3325f1bc 544 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 545 vin-supply = <&sys_3v3_reg>;
546 };
547
548 vdd_com_reg: regulator@9 {
549 compatible = "regulator-fixed";
550 reg = <9>;
551 regulator-name = "vdd_com";
552 regulator-min-microvolt = <3300000>;
553 regulator-max-microvolt = <3300000>;
6fb11131
WN		 554 regulator-always-on;
555 regulator-boot-on;
fa4a9252 556 enable-active-high;
3325f1bc 557 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 558 vin-supply = <&sys_3v3_reg>;
559 };
560
561 vdd_fuse_3v3_reg: regulator@10 {
562 compatible = "regulator-fixed";
563 reg = <10>;
564 regulator-name = "vdd_fuse_3v3";
565 regulator-min-microvolt = <3300000>;
566 regulator-max-microvolt = <3300000>;
567 enable-active-high;
3325f1bc 568 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 569 vin-supply = <&sys_3v3_reg>;
570 };
571
572 vdd_pnl1_reg: regulator@11 {
573 compatible = "regulator-fixed";
574 reg = <11>;
575 regulator-name = "vdd_pnl1";
576 regulator-min-microvolt = <3300000>;
577 regulator-max-microvolt = <3300000>;
578 regulator-always-on;
579 regulator-boot-on;
580 enable-active-high;
3325f1bc 581 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 582 vin-supply = <&sys_3v3_reg>;
583 };
584
585 vdd_vid_reg: regulator@12 {
586 compatible = "regulator-fixed";
587 reg = <12>;
588 regulator-name = "vddio_vid";
589 regulator-min-microvolt = <5000000>;
590 regulator-max-microvolt = <5000000>;
591 enable-active-high;
3325f1bc 592 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 593 gpio-open-drain;
594 vin-supply = <&vdd_5v0_reg>;
595 };
167e6279
LD		 596 };
597
8c6a3852
SW		 598 sound {
599 compatible = "nvidia,tegra-audio-wm8903-cardhu",
600 "nvidia,tegra-audio-wm8903";
601 nvidia,model = "NVIDIA Tegra Cardhu";
602
603 nvidia,audio-routing =
604 "Headphone Jack", "HPOUTR",
605 "Headphone Jack", "HPOUTL",
606 "Int Spk", "ROP",
607 "Int Spk", "RON",
608 "Int Spk", "LOP",
609 "Int Spk", "LON",
610 "Mic Jack", "MICBIAS",
611 "IN1L", "Mic Jack";
612
613 nvidia,i2s-controller = <&tegra_i2s1>;
614 nvidia,audio-codec = <&wm8903>;
615
3325f1bc
SW		 616 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
617 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
618 GPIO_ACTIVE_HIGH>;
f9cd2b3b 619
05849c93
HD		 620 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
621 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
622 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 623 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 624 };
5780c206
TR		 625
626 gpio-keys {
627 compatible = "gpio-keys";
628
629 power {
630 label = "Power";
631 interrupt-parent = <&pmic>;
632 interrupts = <2 0>;
633 linux,code = <KEY_POWER>;
634 debounce-interval = <100>;
d1c04d30 635 wakeup-source;
5780c206
TR		 636 };
637
638 volume-down {
639 label = "Volume Down";
640 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
641 linux,code = <KEY_VOLUMEDOWN>;
642 debounce-interval = <10>;
643 };
644
645 volume-up {
646 label = "Volume Up";
647 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
648 linux,code = <KEY_VOLUMEUP>;
649 debounce-interval = <10>;
650 };
651 };
64c4e9f8 652};
Ubuntu Hirsute Linux kernel mirror