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ARM: tegra: Enable LVDS on Harmony
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
CommitLineData
1bd0bd49 1#include "tegra30.dtsi"
64c4e9f8 2
640a7af5
LD		 3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
64c4e9f8
PDS		 26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
553c0a20
SW		 30 aliases {
31 rtc0 = "/i2c@7000d000/tps6586x@34";
32 rtc1 = "/rtc@7000e000";
33 };
34
64c4e9f8 35 memory {
95decf84 36 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 37 };
38
58ecb23f 39 pcie-controller@00003000 {
89e7ada4
JA		 40 status = "okay";
41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
42 vdd-supply = <&ldo1_reg>;
43 avdd-supply = <&ldo2_reg>;
44
45 pci@1,0 {
46 nvidia,num-lanes = <4>;
47 };
48
49 pci@2,0 {
50 nvidia,num-lanes = <1>;
51 };
52
53 pci@3,0 {
54 status = "okay";
55 nvidia,num-lanes = <1>;
56 };
57 };
58
58ecb23f 59 pinmux@70000868 {
e5cbeef0
SW		 60 pinctrl-names = "default";
61 pinctrl-0 = <&state_default>;
62
63 state_default: pinmux {
64 sdmmc1_clk_pz0 {
65 nvidia,pins = "sdmmc1_clk_pz0";
66 nvidia,function = "sdmmc1";
a47c662a
LD		 67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 69 };
70 sdmmc1_cmd_pz1 {
71 nvidia,pins = "sdmmc1_cmd_pz1",
72 "sdmmc1_dat0_py7",
73 "sdmmc1_dat1_py6",
74 "sdmmc1_dat2_py5",
75 "sdmmc1_dat3_py4";
76 nvidia,function = "sdmmc1";
a47c662a
LD		 77 nvidia,pull = <TEGRA_PIN_PULL_UP>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 79 };
6fb11131
WN		 80 sdmmc3_clk_pa6 {
81 nvidia,pins = "sdmmc3_clk_pa6";
82 nvidia,function = "sdmmc3";
a47c662a
LD		 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 85 };
86 sdmmc3_cmd_pa7 {
87 nvidia,pins = "sdmmc3_cmd_pa7",
88 "sdmmc3_dat0_pb7",
89 "sdmmc3_dat1_pb6",
90 "sdmmc3_dat2_pb5",
91 "sdmmc3_dat3_pb4";
92 nvidia,function = "sdmmc3";
a47c662a
LD		 93 nvidia,pull = <TEGRA_PIN_PULL_UP>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 95 };
e5cbeef0
SW		 96 sdmmc4_clk_pcc4 {
97 nvidia,pins = "sdmmc4_clk_pcc4",
98 "sdmmc4_rst_n_pcc3";
99 nvidia,function = "sdmmc4";
a47c662a
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 102 };
103 sdmmc4_dat0_paa0 {
104 nvidia,pins = "sdmmc4_dat0_paa0",
105 "sdmmc4_dat1_paa1",
106 "sdmmc4_dat2_paa2",
107 "sdmmc4_dat3_paa3",
108 "sdmmc4_dat4_paa4",
109 "sdmmc4_dat5_paa5",
110 "sdmmc4_dat6_paa6",
111 "sdmmc4_dat7_paa7";
112 nvidia,function = "sdmmc4";
a47c662a
LD		 113 nvidia,pull = <TEGRA_PIN_PULL_UP>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 115 };
8c6a3852
SW		 116 dap2_fs_pa2 {
117 nvidia,pins = "dap2_fs_pa2",
118 "dap2_sclk_pa3",
119 "dap2_din_pa4",
120 "dap2_dout_pa5";
121 nvidia,function = "i2s1";
a47c662a
LD		 122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 124 };
6fb11131
WN		 125 sdio3 {
126 nvidia,pins = "drive_sdio3";
a47c662a
LD		 127 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
128 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 129 nvidia,pull-down-strength = <46>;
130 nvidia,pull-up-strength = <42>;
a47c662a
LD		 131 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
132 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 133 };
ecfd6c7f
LD		 134 uart3_txd_pw6 {
135 nvidia,pins = "uart3_txd_pw6",
136 "uart3_cts_n_pa1",
137 "uart3_rts_n_pc0",
138 "uart3_rxd_pw7";
139 nvidia,function = "uartc";
a47c662a
LD		 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 142 };
e5cbeef0
SW		 143 };
144 };
145
64c4e9f8 146 serial@70006000 {
2a5fdc9a 147 status = "okay";
64c4e9f8
PDS		 148 };
149
ecfd6c7f
LD		 150 serial@70006200 {
151 compatible = "nvidia,tegra30-hsuart";
152 status = "okay";
ecfd6c7f
LD		 153 };
154
64c4e9f8 155 i2c@7000c000 {
2a5fdc9a 156 status = "okay";
64c4e9f8
PDS		 157 clock-frequency = <100000>;
158 };
159
160 i2c@7000c400 {
2a5fdc9a 161 status = "okay";
64c4e9f8
PDS		 162 clock-frequency = <100000>;
163 };
164
165 i2c@7000c500 {
2a5fdc9a 166 status = "okay";
64c4e9f8 167 clock-frequency = <100000>;
b46b0b54
LD		 168
169 /* ALS and Proximity sensor */
170 isl29028@44 {
171 compatible = "isil,isl29028";
172 reg = <0x44>;
173 interrupt-parent = <&gpio>;
6cecf916 174 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 175 };
64c4e9f8
PDS		 176 };
177
178 i2c@7000c700 {
2a5fdc9a 179 status = "okay";
64c4e9f8
PDS		 180 clock-frequency = <100000>;
181 };
182
183 i2c@7000d000 {
2a5fdc9a 184 status = "okay";
64c4e9f8 185 clock-frequency = <100000>;
8c6a3852
SW		 186
187 wm8903: wm8903@1a {
188 compatible = "wlf,wm8903";
189 reg = <0x1a>;
190 interrupt-parent = <&gpio>;
6cecf916 191 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 192
193 gpio-controller;
194 #gpio-cells = <2>;
195
196 micdet-cfg = <0>;
197 micdet-delay = <100>;
198 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
199 };
331da58c 200
167e6279
LD		 201 pmic: tps65911@2d {
202 compatible = "ti,tps65911";
203 reg = <0x2d>;
204
6cecf916 205 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 206 #interrupt-cells = <2>;
207 interrupt-controller;
208
44b12ef7
SW		 209 ti,system-power-controller;
210
167e6279
LD		 211 #gpio-cells = <2>;
212 gpio-controller;
213
214 vcc1-supply = <&vdd_ac_bat_reg>;
215 vcc2-supply = <&vdd_ac_bat_reg>;
216 vcc3-supply = <&vio_reg>;
fa4a9252 217 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 218 vcc5-supply = <&vdd_ac_bat_reg>;
219 vcc6-supply = <&vdd2_reg>;
220 vcc7-supply = <&vdd_ac_bat_reg>;
221 vccio-supply = <&vdd_ac_bat_reg>;
222
223 regulators {
b9c665d7 224 vdd1_reg: vdd1 {
167e6279
LD		 225 regulator-name = "vddio_ddr_1v2";
226 regulator-min-microvolt = <1200000>;
227 regulator-max-microvolt = <1200000>;
228 regulator-always-on;
229 };
230
b9c665d7 231 vdd2_reg: vdd2 {
167e6279
LD		 232 regulator-name = "vdd_1v5_gen";
233 regulator-min-microvolt = <1500000>;
234 regulator-max-microvolt = <1500000>;
235 regulator-always-on;
236 };
237
b9c665d7 238 vddctrl_reg: vddctrl {
167e6279
LD		 239 regulator-name = "vdd_cpu,vdd_sys";
240 regulator-min-microvolt = <1000000>;
241 regulator-max-microvolt = <1000000>;
242 regulator-always-on;
243 };
244
b9c665d7 245 vio_reg: vio {
167e6279
LD		 246 regulator-name = "vdd_1v8_gen";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <1800000>;
249 regulator-always-on;
250 };
251
b9c665d7 252 ldo1_reg: ldo1 {
167e6279
LD		 253 regulator-name = "vdd_pexa,vdd_pexb";
254 regulator-min-microvolt = <1050000>;
255 regulator-max-microvolt = <1050000>;
256 };
257
b9c665d7 258 ldo2_reg: ldo2 {
167e6279
LD		 259 regulator-name = "vdd_sata,avdd_plle";
260 regulator-min-microvolt = <1050000>;
261 regulator-max-microvolt = <1050000>;
262 };
263
264 /* LDO3 is not connected to anything */
265
b9c665d7 266 ldo4_reg: ldo4 {
167e6279
LD		 267 regulator-name = "vdd_rtc";
268 regulator-min-microvolt = <1200000>;
269 regulator-max-microvolt = <1200000>;
270 regulator-always-on;
271 };
272
b9c665d7 273 ldo5_reg: ldo5 {
fa4a9252
LD		 274 regulator-name = "vddio_sdmmc,avdd_vdac";
275 regulator-min-microvolt = <3300000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-always-on;
278 };
279
b9c665d7 280 ldo6_reg: ldo6 {
167e6279
LD		 281 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
282 regulator-min-microvolt = <1200000>;
283 regulator-max-microvolt = <1200000>;
284 };
285
b9c665d7 286 ldo7_reg: ldo7 {
167e6279
LD		 287 regulator-name = "vdd_pllm,x,u,a_p_c_s";
288 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>;
290 regulator-always-on;
291 };
292
b9c665d7 293 ldo8_reg: ldo8 {
167e6279
LD		 294 regulator-name = "vdd_ddr_hs";
295 regulator-min-microvolt = <1000000>;
296 regulator-max-microvolt = <1000000>;
297 regulator-always-on;
298 };
299 };
300 };
74ecab27 301
7c7de6b0 302 temperature-sensor@4c {
74ecab27
WN		 303 compatible = "onnn,nct1008";
304 reg = <0x4c>;
7c7de6b0 305 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 306 interrupt-parent = <&gpio>;
307 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
308 };
2b8584d5 309
58ecb23f 310 tps62361@60 {
2b8584d5
SW		 311 compatible = "ti,tps62361";
312 reg = <0x60>;
313
314 regulator-name = "tps62361-vout";
315 regulator-min-microvolt = <500000>;
316 regulator-max-microvolt = <1500000>;
317 regulator-boot-on;
318 regulator-always-on;
319 ti,vsel0-state-high;
320 ti,vsel1-state-high;
321 };
64c4e9f8 322 };
850c4c8f 323
c42cb1c3
LD		 324 spi@7000da00 {
325 status = "okay";
326 spi-max-frequency = <25000000>;
327 spi-flash@1 {
328 compatible = "winbond,w25q32";
329 reg = <1>;
330 spi-max-frequency = <20000000>;
331 };
332 };
333
58ecb23f 334 pmc@7000e400 {
167e6279
LD		 335 status = "okay";
336 nvidia,invert-interrupt;
47d2d63b 337 nvidia,suspend-mode = <1>;
a44a019d
JL		 338 nvidia,cpu-pwr-good-time = <2000>;
339 nvidia,cpu-pwr-off-time = <200>;
340 nvidia,core-pwr-good-time = <3845 3845>;
341 nvidia,core-pwr-off-time = <0>;
342 nvidia,core-power-req-active-high;
343 nvidia,sys-clock-req-active-high;
167e6279
LD		 344 };
345
57899053
SW		 346 ahub@70080000 {
347 i2s@70080400 {
348 status = "okay";
349 };
350 };
351
c04abb3a 352 sdhci@78000000 {
2a5fdc9a 353 status = "okay";
3325f1bc
SW		 354 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
355 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
356 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 357 bus-width = <4>;
c04abb3a
SW		 358 };
359
c04abb3a 360 sdhci@78000600 {
2a5fdc9a 361 status = "okay";
7f217794 362 bus-width = <8>;
7a2617a6 363 non-removable;
c04abb3a
SW		 364 };
365
cc34c9f7
TT		 366 usb@7d008000 {
367 status = "okay";
368 };
369
370 usb-phy@7d008000 {
371 vbus-supply = <&usb3_vbus_reg>;
372 status = "okay";
373 };
374
7021d122
JL		 375 clocks {
376 compatible = "simple-bus";
377 #address-cells = <1>;
378 #size-cells = <0>;
379
58ecb23f 380 clk32k_in: clock@0 {
7021d122
JL		 381 compatible = "fixed-clock";
382 reg=<0>;
383 #clock-cells = <0>;
384 clock-frequency = <32768>;
385 };
386 };
387
167e6279
LD		 388 regulators {
389 compatible = "simple-bus";
390 #address-cells = <1>;
391 #size-cells = <0>;
392
393 vdd_ac_bat_reg: regulator@0 {
394 compatible = "regulator-fixed";
395 reg = <0>;
396 regulator-name = "vdd_ac_bat";
397 regulator-min-microvolt = <5000000>;
398 regulator-max-microvolt = <5000000>;
399 regulator-always-on;
400 };
fa4a9252
LD		 401
402 cam_1v8_reg: regulator@1 {
403 compatible = "regulator-fixed";
404 reg = <1>;
405 regulator-name = "cam_1v8";
406 regulator-min-microvolt = <1800000>;
407 regulator-max-microvolt = <1800000>;
408 enable-active-high;
3325f1bc 409 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 410 vin-supply = <&vio_reg>;
411 };
412
413 cp_5v_reg: regulator@2 {
414 compatible = "regulator-fixed";
415 reg = <2>;
416 regulator-name = "cp_5v";
417 regulator-min-microvolt = <5000000>;
418 regulator-max-microvolt = <5000000>;
419 regulator-boot-on;
420 regulator-always-on;
421 enable-active-high;
3325f1bc 422 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 423 };
424
425 emmc_3v3_reg: regulator@3 {
426 compatible = "regulator-fixed";
427 reg = <3>;
428 regulator-name = "emmc_3v3";
429 regulator-min-microvolt = <3300000>;
430 regulator-max-microvolt = <3300000>;
431 regulator-always-on;
432 regulator-boot-on;
433 enable-active-high;
3325f1bc 434 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 435 vin-supply = <&sys_3v3_reg>;
436 };
437
438 modem_3v3_reg: regulator@4 {
439 compatible = "regulator-fixed";
440 reg = <4>;
441 regulator-name = "modem_3v3";
442 regulator-min-microvolt = <3300000>;
443 regulator-max-microvolt = <3300000>;
444 enable-active-high;
3325f1bc 445 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 446 };
447
448 pex_hvdd_3v3_reg: regulator@5 {
449 compatible = "regulator-fixed";
450 reg = <5>;
451 regulator-name = "pex_hvdd_3v3";
452 regulator-min-microvolt = <3300000>;
453 regulator-max-microvolt = <3300000>;
454 enable-active-high;
3325f1bc 455 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 456 vin-supply = <&sys_3v3_reg>;
457 };
458
459 vdd_cam1_ldo_reg: regulator@6 {
460 compatible = "regulator-fixed";
461 reg = <6>;
462 regulator-name = "vdd_cam1_ldo";
463 regulator-min-microvolt = <2800000>;
464 regulator-max-microvolt = <2800000>;
465 enable-active-high;
3325f1bc 466 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 467 vin-supply = <&sys_3v3_reg>;
468 };
469
470 vdd_cam2_ldo_reg: regulator@7 {
471 compatible = "regulator-fixed";
472 reg = <7>;
473 regulator-name = "vdd_cam2_ldo";
474 regulator-min-microvolt = <2800000>;
475 regulator-max-microvolt = <2800000>;
476 enable-active-high;
3325f1bc 477 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 478 vin-supply = <&sys_3v3_reg>;
479 };
480
481 vdd_cam3_ldo_reg: regulator@8 {
482 compatible = "regulator-fixed";
483 reg = <8>;
484 regulator-name = "vdd_cam3_ldo";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 enable-active-high;
3325f1bc 488 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 489 vin-supply = <&sys_3v3_reg>;
490 };
491
492 vdd_com_reg: regulator@9 {
493 compatible = "regulator-fixed";
494 reg = <9>;
495 regulator-name = "vdd_com";
496 regulator-min-microvolt = <3300000>;
497 regulator-max-microvolt = <3300000>;
6fb11131
WN		 498 regulator-always-on;
499 regulator-boot-on;
fa4a9252 500 enable-active-high;
3325f1bc 501 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 502 vin-supply = <&sys_3v3_reg>;
503 };
504
505 vdd_fuse_3v3_reg: regulator@10 {
506 compatible = "regulator-fixed";
507 reg = <10>;
508 regulator-name = "vdd_fuse_3v3";
509 regulator-min-microvolt = <3300000>;
510 regulator-max-microvolt = <3300000>;
511 enable-active-high;
3325f1bc 512 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 513 vin-supply = <&sys_3v3_reg>;
514 };
515
516 vdd_pnl1_reg: regulator@11 {
517 compatible = "regulator-fixed";
518 reg = <11>;
519 regulator-name = "vdd_pnl1";
520 regulator-min-microvolt = <3300000>;
521 regulator-max-microvolt = <3300000>;
522 regulator-always-on;
523 regulator-boot-on;
524 enable-active-high;
3325f1bc 525 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 526 vin-supply = <&sys_3v3_reg>;
527 };
528
529 vdd_vid_reg: regulator@12 {
530 compatible = "regulator-fixed";
531 reg = <12>;
532 regulator-name = "vddio_vid";
533 regulator-min-microvolt = <5000000>;
534 regulator-max-microvolt = <5000000>;
535 enable-active-high;
3325f1bc 536 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 537 gpio-open-drain;
538 vin-supply = <&vdd_5v0_reg>;
539 };
167e6279
LD		 540 };
541
8c6a3852
SW		 542 sound {
543 compatible = "nvidia,tegra-audio-wm8903-cardhu",
544 "nvidia,tegra-audio-wm8903";
545 nvidia,model = "NVIDIA Tegra Cardhu";
546
547 nvidia,audio-routing =
548 "Headphone Jack", "HPOUTR",
549 "Headphone Jack", "HPOUTL",
550 "Int Spk", "ROP",
551 "Int Spk", "RON",
552 "Int Spk", "LOP",
553 "Int Spk", "LON",
554 "Mic Jack", "MICBIAS",
555 "IN1L", "Mic Jack";
556
557 nvidia,i2s-controller = <&tegra_i2s1>;
558 nvidia,audio-codec = <&wm8903>;
559
3325f1bc
SW		 560 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
561 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
562 GPIO_ACTIVE_HIGH>;
f9cd2b3b 563
05849c93
HD		 564 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
565 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
566 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 567 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 568 };
64c4e9f8 569};
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