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Merge remote-tracking branches 'asoc/topic/ac97', 'asoc/topic/ac97-mfd', 'asoc/topic...
[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
5780c206 2#include <dt-bindings/input/input.h>
1bd0bd49 3#include "tegra30.dtsi"
64c4e9f8 4
640a7af5
LD		 5/**
6 * This file contains common DT entry for all fab version of Cardhu.
7 * There is multiple fab version of Cardhu starting from A01 to A07.
8 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
9 * A02 will have different sets of GPIOs for fixed regulator compare to
10 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
11 * compatible with fab version A04. Based on Cardhu fab version, the
12 * related dts file need to be chosen like for Cardhu fab version A02,
13 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
14 * tegra30-cardhu-a04.dts.
15 * The identification of board is done in two ways, by looking the sticker
16 * on PCB and by reading board id eeprom.
db374069 17 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
640a7af5
LD		 18 * number is the fab version like here it is 002 and hence fab version A02.
19 * The (downstream internal) U-Boot of Cardhu display the board-id as
20 * follows:
21 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
22 * In this Fab version is 02 i.e. A02.
23 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
24 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
25 * wide.
26 */
27
64c4e9f8
PDS		 28/ {
29 model = "NVIDIA Tegra30 Cardhu evaluation board";
30 compatible = "nvidia,cardhu", "nvidia,tegra30";
31
553c0a20 32 aliases {
763fbff2 33 rtc0 = "/i2c@7000d000/tps65911@2d";
553c0a20 34 rtc1 = "/rtc@7000e000";
c4574aa0
OJ		 35 serial0 = &uarta;
36 serial1 = &uartc;
553c0a20
SW		 37 };
38
f5bbb327
JH		 39 chosen {
40 stdout-path = "serial0:115200n8";
41 };
42
64c4e9f8 43 memory {
95decf84 44 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 45 };
46
508d690e 47 pcie@3000 {
89e7ada4 48 status = "okay";
cca8614d
TR		 49
50 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
51 avdd-pexb-supply = <&ldo1_reg>;
52 vdd-pexb-supply = <&ldo1_reg>;
53 avdd-pex-pll-supply = <&ldo1_reg>;
54 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
55 vddio-pex-ctl-supply = <&sys_3v3_reg>;
56 avdd-plle-supply = <&ldo2_reg>;
57
89e7ada4
JA		 58 pci@1,0 {
59 nvidia,num-lanes = <4>;
60 };
61
62 pci@2,0 {
63 nvidia,num-lanes = <1>;
64 };
65
66 pci@3,0 {
67 status = "okay";
68 nvidia,num-lanes = <1>;
69 };
70 };
71
02b1fea2
TR		 72 host1x@50000000 {
73 dc@54200000 {
74 rgb {
75 status = "okay";
76
77 nvidia,panel = <&panel>;
78 };
79 };
80 };
81
58ecb23f 82 pinmux@70000868 {
e5cbeef0
SW		 83 pinctrl-names = "default";
84 pinctrl-0 = <&state_default>;
85
86 state_default: pinmux {
87 sdmmc1_clk_pz0 {
88 nvidia,pins = "sdmmc1_clk_pz0";
89 nvidia,function = "sdmmc1";
a47c662a
LD		 90 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 92 };
93 sdmmc1_cmd_pz1 {
94 nvidia,pins = "sdmmc1_cmd_pz1",
95 "sdmmc1_dat0_py7",
96 "sdmmc1_dat1_py6",
97 "sdmmc1_dat2_py5",
98 "sdmmc1_dat3_py4";
99 nvidia,function = "sdmmc1";
a47c662a
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 102 };
6fb11131
WN		 103 sdmmc3_clk_pa6 {
104 nvidia,pins = "sdmmc3_clk_pa6";
105 nvidia,function = "sdmmc3";
a47c662a
LD		 106 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 108 };
109 sdmmc3_cmd_pa7 {
110 nvidia,pins = "sdmmc3_cmd_pa7",
111 "sdmmc3_dat0_pb7",
112 "sdmmc3_dat1_pb6",
113 "sdmmc3_dat2_pb5",
114 "sdmmc3_dat3_pb4";
115 nvidia,function = "sdmmc3";
a47c662a
LD		 116 nvidia,pull = <TEGRA_PIN_PULL_UP>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 118 };
e5cbeef0
SW		 119 sdmmc4_clk_pcc4 {
120 nvidia,pins = "sdmmc4_clk_pcc4",
121 "sdmmc4_rst_n_pcc3";
122 nvidia,function = "sdmmc4";
a47c662a
LD		 123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 125 };
126 sdmmc4_dat0_paa0 {
127 nvidia,pins = "sdmmc4_dat0_paa0",
128 "sdmmc4_dat1_paa1",
129 "sdmmc4_dat2_paa2",
130 "sdmmc4_dat3_paa3",
131 "sdmmc4_dat4_paa4",
132 "sdmmc4_dat5_paa5",
133 "sdmmc4_dat6_paa6",
134 "sdmmc4_dat7_paa7";
135 nvidia,function = "sdmmc4";
a47c662a
LD		 136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 138 };
8c6a3852
SW		 139 dap2_fs_pa2 {
140 nvidia,pins = "dap2_fs_pa2",
141 "dap2_sclk_pa3",
142 "dap2_din_pa4",
143 "dap2_dout_pa5";
144 nvidia,function = "i2s1";
a47c662a
LD		 145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 147 };
6fb11131
WN		 148 sdio3 {
149 nvidia,pins = "drive_sdio3";
a47c662a
LD		 150 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
151 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 152 nvidia,pull-down-strength = <46>;
153 nvidia,pull-up-strength = <42>;
a47c662a
LD		 154 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
155 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 156 };
ecfd6c7f
LD		 157 uart3_txd_pw6 {
158 nvidia,pins = "uart3_txd_pw6",
159 "uart3_cts_n_pa1",
160 "uart3_rts_n_pc0",
161 "uart3_rxd_pw7";
162 nvidia,function = "uartc";
a47c662a
LD		 163 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 165 };
e5cbeef0
SW		 166 };
167 };
168
64c4e9f8 169 serial@70006000 {
2a5fdc9a 170 status = "okay";
64c4e9f8
PDS		 171 };
172
ecfd6c7f
LD		 173 serial@70006200 {
174 compatible = "nvidia,tegra30-hsuart";
175 status = "okay";
ecfd6c7f
LD		 176 };
177
02b1fea2
TR		 178 pwm@7000a000 {
179 status = "okay";
180 };
181
182 panelddc: i2c@7000c000 {
2a5fdc9a 183 status = "okay";
64c4e9f8
PDS		 184 clock-frequency = <100000>;
185 };
186
187 i2c@7000c400 {
2a5fdc9a 188 status = "okay";
64c4e9f8
PDS		 189 clock-frequency = <100000>;
190 };
191
192 i2c@7000c500 {
2a5fdc9a 193 status = "okay";
64c4e9f8 194 clock-frequency = <100000>;
b46b0b54
LD		 195
196 /* ALS and Proximity sensor */
197 isl29028@44 {
62981239 198 compatible = "isil,isl29028";
b46b0b54
LD		 199 reg = <0x44>;
200 interrupt-parent = <&gpio>;
6cecf916 201 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 202 };
40431d16
BW		 203
204 i2cmux@70 {
205 compatible = "nxp,pca9546";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <0x70>;
209 };
64c4e9f8
PDS		 210 };
211
212 i2c@7000c700 {
2a5fdc9a 213 status = "okay";
64c4e9f8
PDS		 214 clock-frequency = <100000>;
215 };
216
217 i2c@7000d000 {
2a5fdc9a 218 status = "okay";
64c4e9f8 219 clock-frequency = <100000>;
8c6a3852
SW		 220
221 wm8903: wm8903@1a {
222 compatible = "wlf,wm8903";
223 reg = <0x1a>;
224 interrupt-parent = <&gpio>;
6cecf916 225 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 226
227 gpio-controller;
228 #gpio-cells = <2>;
229
230 micdet-cfg = <0>;
231 micdet-delay = <100>;
232 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
233 };
331da58c 234
167e6279
LD		 235 pmic: tps65911@2d {
236 compatible = "ti,tps65911";
237 reg = <0x2d>;
238
6cecf916 239 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 240 #interrupt-cells = <2>;
241 interrupt-controller;
242
44b12ef7
SW		 243 ti,system-power-controller;
244
167e6279
LD		 245 #gpio-cells = <2>;
246 gpio-controller;
247
248 vcc1-supply = <&vdd_ac_bat_reg>;
249 vcc2-supply = <&vdd_ac_bat_reg>;
250 vcc3-supply = <&vio_reg>;
fa4a9252 251 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 252 vcc5-supply = <&vdd_ac_bat_reg>;
253 vcc6-supply = <&vdd2_reg>;
254 vcc7-supply = <&vdd_ac_bat_reg>;
255 vccio-supply = <&vdd_ac_bat_reg>;
256
257 regulators {
b9c665d7 258 vdd1_reg: vdd1 {
167e6279
LD		 259 regulator-name = "vddio_ddr_1v2";
260 regulator-min-microvolt = <1200000>;
261 regulator-max-microvolt = <1200000>;
262 regulator-always-on;
263 };
264
b9c665d7 265 vdd2_reg: vdd2 {
167e6279
LD		 266 regulator-name = "vdd_1v5_gen";
267 regulator-min-microvolt = <1500000>;
268 regulator-max-microvolt = <1500000>;
269 regulator-always-on;
270 };
271
b9c665d7 272 vddctrl_reg: vddctrl {
167e6279
LD		 273 regulator-name = "vdd_cpu,vdd_sys";
274 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <1000000>;
276 regulator-always-on;
277 };
278
b9c665d7 279 vio_reg: vio {
167e6279
LD		 280 regulator-name = "vdd_1v8_gen";
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <1800000>;
283 regulator-always-on;
284 };
285
b9c665d7 286 ldo1_reg: ldo1 {
167e6279
LD		 287 regulator-name = "vdd_pexa,vdd_pexb";
288 regulator-min-microvolt = <1050000>;
289 regulator-max-microvolt = <1050000>;
290 };
291
b9c665d7 292 ldo2_reg: ldo2 {
167e6279
LD		 293 regulator-name = "vdd_sata,avdd_plle";
294 regulator-min-microvolt = <1050000>;
295 regulator-max-microvolt = <1050000>;
296 };
297
298 /* LDO3 is not connected to anything */
299
b9c665d7 300 ldo4_reg: ldo4 {
167e6279
LD		 301 regulator-name = "vdd_rtc";
302 regulator-min-microvolt = <1200000>;
303 regulator-max-microvolt = <1200000>;
304 regulator-always-on;
305 };
306
b9c665d7 307 ldo5_reg: ldo5 {
fa4a9252
LD		 308 regulator-name = "vddio_sdmmc,avdd_vdac";
309 regulator-min-microvolt = <3300000>;
310 regulator-max-microvolt = <3300000>;
311 regulator-always-on;
312 };
313
b9c665d7 314 ldo6_reg: ldo6 {
167e6279
LD		 315 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
318 };
319
b9c665d7 320 ldo7_reg: ldo7 {
167e6279
LD		 321 regulator-name = "vdd_pllm,x,u,a_p_c_s";
322 regulator-min-microvolt = <1200000>;
323 regulator-max-microvolt = <1200000>;
324 regulator-always-on;
325 };
326
b9c665d7 327 ldo8_reg: ldo8 {
167e6279
LD		 328 regulator-name = "vdd_ddr_hs";
329 regulator-min-microvolt = <1000000>;
330 regulator-max-microvolt = <1000000>;
331 regulator-always-on;
332 };
333 };
334 };
74ecab27 335
7c7de6b0 336 temperature-sensor@4c {
74ecab27
WN		 337 compatible = "onnn,nct1008";
338 reg = <0x4c>;
7c7de6b0 339 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 340 interrupt-parent = <&gpio>;
341 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
342 };
2b8584d5 343
58ecb23f 344 tps62361@60 {
2b8584d5
SW		 345 compatible = "ti,tps62361";
346 reg = <0x60>;
347
348 regulator-name = "tps62361-vout";
349 regulator-min-microvolt = <500000>;
350 regulator-max-microvolt = <1500000>;
351 regulator-boot-on;
352 regulator-always-on;
353 ti,vsel0-state-high;
354 ti,vsel1-state-high;
355 };
64c4e9f8 356 };
850c4c8f 357
c42cb1c3
LD		 358 spi@7000da00 {
359 status = "okay";
360 spi-max-frequency = <25000000>;
361 spi-flash@1 {
362 compatible = "winbond,w25q32";
363 reg = <1>;
364 spi-max-frequency = <20000000>;
365 };
366 };
367
58ecb23f 368 pmc@7000e400 {
167e6279
LD		 369 status = "okay";
370 nvidia,invert-interrupt;
47d2d63b 371 nvidia,suspend-mode = <1>;
a44a019d
JL		 372 nvidia,cpu-pwr-good-time = <2000>;
373 nvidia,cpu-pwr-off-time = <200>;
374 nvidia,core-pwr-good-time = <3845 3845>;
375 nvidia,core-pwr-off-time = <0>;
376 nvidia,core-power-req-active-high;
377 nvidia,sys-clock-req-active-high;
167e6279
LD		 378 };
379
57899053
SW		 380 ahub@70080000 {
381 i2s@70080400 {
382 status = "okay";
383 };
384 };
385
c04abb3a 386 sdhci@78000000 {
2a5fdc9a 387 status = "okay";
3325f1bc
SW		 388 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
389 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
390 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 391 bus-width = <4>;
c04abb3a
SW		 392 };
393
c04abb3a 394 sdhci@78000600 {
2a5fdc9a 395 status = "okay";
7f217794 396 bus-width = <8>;
7a2617a6 397 non-removable;
c04abb3a
SW		 398 };
399
cc34c9f7
TT		 400 usb@7d008000 {
401 status = "okay";
402 };
403
404 usb-phy@7d008000 {
405 vbus-supply = <&usb3_vbus_reg>;
406 status = "okay";
407 };
408
02b1fea2
TR		 409 backlight: backlight {
410 compatible = "pwm-backlight";
411
412 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
413 power-supply = <&vdd_bl_reg>;
414 pwms = <&pwm 0 5000000>;
415
416 brightness-levels = <0 4 8 16 32 64 128 255>;
417 default-brightness-level = <6>;
418 };
419
7021d122
JL		 420 clocks {
421 compatible = "simple-bus";
422 #address-cells = <1>;
423 #size-cells = <0>;
424
58ecb23f 425 clk32k_in: clock@0 {
7021d122 426 compatible = "fixed-clock";
4ec2e601 427 reg = <0>;
7021d122
JL		 428 #clock-cells = <0>;
429 clock-frequency = <32768>;
430 };
431 };
432
02b1fea2
TR		 433 panel: panel {
434 compatible = "chunghwa,claa101wb01", "simple-panel";
435 ddc-i2c-bus = <&panelddc>;
436
437 power-supply = <&vdd_pnl1_reg>;
438 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
439
440 backlight = <&backlight>;
441 };
442
167e6279
LD		 443 regulators {
444 compatible = "simple-bus";
445 #address-cells = <1>;
446 #size-cells = <0>;
447
448 vdd_ac_bat_reg: regulator@0 {
449 compatible = "regulator-fixed";
450 reg = <0>;
451 regulator-name = "vdd_ac_bat";
452 regulator-min-microvolt = <5000000>;
453 regulator-max-microvolt = <5000000>;
454 regulator-always-on;
455 };
fa4a9252
LD		 456
457 cam_1v8_reg: regulator@1 {
458 compatible = "regulator-fixed";
459 reg = <1>;
460 regulator-name = "cam_1v8";
461 regulator-min-microvolt = <1800000>;
462 regulator-max-microvolt = <1800000>;
463 enable-active-high;
3325f1bc 464 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 465 vin-supply = <&vio_reg>;
466 };
467
468 cp_5v_reg: regulator@2 {
469 compatible = "regulator-fixed";
470 reg = <2>;
471 regulator-name = "cp_5v";
472 regulator-min-microvolt = <5000000>;
473 regulator-max-microvolt = <5000000>;
474 regulator-boot-on;
475 regulator-always-on;
476 enable-active-high;
3325f1bc 477 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 478 };
479
480 emmc_3v3_reg: regulator@3 {
481 compatible = "regulator-fixed";
482 reg = <3>;
483 regulator-name = "emmc_3v3";
484 regulator-min-microvolt = <3300000>;
485 regulator-max-microvolt = <3300000>;
486 regulator-always-on;
487 regulator-boot-on;
488 enable-active-high;
3325f1bc 489 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 490 vin-supply = <&sys_3v3_reg>;
491 };
492
493 modem_3v3_reg: regulator@4 {
494 compatible = "regulator-fixed";
495 reg = <4>;
496 regulator-name = "modem_3v3";
497 regulator-min-microvolt = <3300000>;
498 regulator-max-microvolt = <3300000>;
499 enable-active-high;
3325f1bc 500 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 501 };
502
503 pex_hvdd_3v3_reg: regulator@5 {
504 compatible = "regulator-fixed";
505 reg = <5>;
506 regulator-name = "pex_hvdd_3v3";
507 regulator-min-microvolt = <3300000>;
508 regulator-max-microvolt = <3300000>;
509 enable-active-high;
3325f1bc 510 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 511 vin-supply = <&sys_3v3_reg>;
512 };
513
514 vdd_cam1_ldo_reg: regulator@6 {
515 compatible = "regulator-fixed";
516 reg = <6>;
517 regulator-name = "vdd_cam1_ldo";
518 regulator-min-microvolt = <2800000>;
519 regulator-max-microvolt = <2800000>;
520 enable-active-high;
3325f1bc 521 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 522 vin-supply = <&sys_3v3_reg>;
523 };
524
525 vdd_cam2_ldo_reg: regulator@7 {
526 compatible = "regulator-fixed";
527 reg = <7>;
528 regulator-name = "vdd_cam2_ldo";
529 regulator-min-microvolt = <2800000>;
530 regulator-max-microvolt = <2800000>;
531 enable-active-high;
3325f1bc 532 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 533 vin-supply = <&sys_3v3_reg>;
534 };
535
536 vdd_cam3_ldo_reg: regulator@8 {
537 compatible = "regulator-fixed";
538 reg = <8>;
539 regulator-name = "vdd_cam3_ldo";
540 regulator-min-microvolt = <3300000>;
541 regulator-max-microvolt = <3300000>;
542 enable-active-high;
3325f1bc 543 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 544 vin-supply = <&sys_3v3_reg>;
545 };
546
547 vdd_com_reg: regulator@9 {
548 compatible = "regulator-fixed";
549 reg = <9>;
550 regulator-name = "vdd_com";
551 regulator-min-microvolt = <3300000>;
552 regulator-max-microvolt = <3300000>;
6fb11131
WN		 553 regulator-always-on;
554 regulator-boot-on;
fa4a9252 555 enable-active-high;
3325f1bc 556 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 557 vin-supply = <&sys_3v3_reg>;
558 };
559
560 vdd_fuse_3v3_reg: regulator@10 {
561 compatible = "regulator-fixed";
562 reg = <10>;
563 regulator-name = "vdd_fuse_3v3";
564 regulator-min-microvolt = <3300000>;
565 regulator-max-microvolt = <3300000>;
566 enable-active-high;
3325f1bc 567 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 568 vin-supply = <&sys_3v3_reg>;
569 };
570
571 vdd_pnl1_reg: regulator@11 {
572 compatible = "regulator-fixed";
573 reg = <11>;
574 regulator-name = "vdd_pnl1";
575 regulator-min-microvolt = <3300000>;
576 regulator-max-microvolt = <3300000>;
577 regulator-always-on;
578 regulator-boot-on;
579 enable-active-high;
3325f1bc 580 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 581 vin-supply = <&sys_3v3_reg>;
582 };
583
584 vdd_vid_reg: regulator@12 {
585 compatible = "regulator-fixed";
586 reg = <12>;
587 regulator-name = "vddio_vid";
588 regulator-min-microvolt = <5000000>;
589 regulator-max-microvolt = <5000000>;
590 enable-active-high;
3325f1bc 591 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 592 gpio-open-drain;
593 vin-supply = <&vdd_5v0_reg>;
594 };
167e6279
LD		 595 };
596
8c6a3852
SW		 597 sound {
598 compatible = "nvidia,tegra-audio-wm8903-cardhu",
599 "nvidia,tegra-audio-wm8903";
600 nvidia,model = "NVIDIA Tegra Cardhu";
601
602 nvidia,audio-routing =
603 "Headphone Jack", "HPOUTR",
604 "Headphone Jack", "HPOUTL",
605 "Int Spk", "ROP",
606 "Int Spk", "RON",
607 "Int Spk", "LOP",
608 "Int Spk", "LON",
609 "Mic Jack", "MICBIAS",
610 "IN1L", "Mic Jack";
611
612 nvidia,i2s-controller = <&tegra_i2s1>;
613 nvidia,audio-codec = <&wm8903>;
614
3325f1bc
SW		 615 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
616 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
617 GPIO_ACTIVE_HIGH>;
f9cd2b3b 618
05849c93
HD		 619 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
620 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
621 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 622 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 623 };
5780c206
TR		 624
625 gpio-keys {
626 compatible = "gpio-keys";
627
628 power {
629 label = "Power";
630 interrupt-parent = <&pmic>;
631 interrupts = <2 0>;
632 linux,code = <KEY_POWER>;
633 debounce-interval = <100>;
d1c04d30 634 wakeup-source;
5780c206
TR		 635 };
636
637 volume-down {
638 label = "Volume Down";
639 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
640 linux,code = <KEY_VOLUMEDOWN>;
641 debounce-interval = <10>;
642 };
643
644 volume-up {
645 label = "Volume Up";
646 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
647 linux,code = <KEY_VOLUMEUP>;
648 debounce-interval = <10>;
649 };
650 };
64c4e9f8 651};
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