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Commit | Line | Data |
---|---|---|
64c4e9f8 PDS |
1 | /include/ "tegra30.dtsi" |
2 | ||
640a7af5 LD |
3 | /** |
4 | * This file contains common DT entry for all fab version of Cardhu. | |
5 | * There is multiple fab version of Cardhu starting from A01 to A07. | |
6 | * Cardhu fab version A01 and A03 are not supported. Cardhu fab version | |
7 | * A02 will have different sets of GPIOs for fixed regulator compare to | |
8 | * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are | |
9 | * compatible with fab version A04. Based on Cardhu fab version, the | |
10 | * related dts file need to be chosen like for Cardhu fab version A02, | |
11 | * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use | |
12 | * tegra30-cardhu-a04.dts. | |
13 | * The identification of board is done in two ways, by looking the sticker | |
14 | * on PCB and by reading board id eeprom. | |
15 | * The stciker will have number like 600-81291-1000-002 C.3. In this 4th | |
16 | * number is the fab version like here it is 002 and hence fab version A02. | |
17 | * The (downstream internal) U-Boot of Cardhu display the board-id as | |
18 | * follows: | |
19 | * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 | |
20 | * In this Fab version is 02 i.e. A02. | |
21 | * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). | |
22 | * The location 0x8 of this eeprom contains the Fab version. It is 1 byte | |
23 | * wide. | |
24 | */ | |
25 | ||
64c4e9f8 PDS |
26 | / { |
27 | model = "NVIDIA Tegra30 Cardhu evaluation board"; | |
28 | compatible = "nvidia,cardhu", "nvidia,tegra30"; | |
29 | ||
30 | memory { | |
95decf84 | 31 | reg = <0x80000000 0x40000000>; |
64c4e9f8 PDS |
32 | }; |
33 | ||
f9eb26a4 | 34 | pinmux { |
e5cbeef0 SW |
35 | pinctrl-names = "default"; |
36 | pinctrl-0 = <&state_default>; | |
37 | ||
38 | state_default: pinmux { | |
39 | sdmmc1_clk_pz0 { | |
40 | nvidia,pins = "sdmmc1_clk_pz0"; | |
41 | nvidia,function = "sdmmc1"; | |
42 | nvidia,pull = <0>; | |
43 | nvidia,tristate = <0>; | |
44 | }; | |
45 | sdmmc1_cmd_pz1 { | |
46 | nvidia,pins = "sdmmc1_cmd_pz1", | |
47 | "sdmmc1_dat0_py7", | |
48 | "sdmmc1_dat1_py6", | |
49 | "sdmmc1_dat2_py5", | |
50 | "sdmmc1_dat3_py4"; | |
51 | nvidia,function = "sdmmc1"; | |
52 | nvidia,pull = <2>; | |
53 | nvidia,tristate = <0>; | |
54 | }; | |
6fb11131 WN |
55 | sdmmc3_clk_pa6 { |
56 | nvidia,pins = "sdmmc3_clk_pa6"; | |
57 | nvidia,function = "sdmmc3"; | |
58 | nvidia,pull = <0>; | |
59 | nvidia,tristate = <0>; | |
60 | }; | |
61 | sdmmc3_cmd_pa7 { | |
62 | nvidia,pins = "sdmmc3_cmd_pa7", | |
63 | "sdmmc3_dat0_pb7", | |
64 | "sdmmc3_dat1_pb6", | |
65 | "sdmmc3_dat2_pb5", | |
66 | "sdmmc3_dat3_pb4"; | |
67 | nvidia,function = "sdmmc3"; | |
68 | nvidia,pull = <2>; | |
69 | nvidia,tristate = <0>; | |
70 | }; | |
e5cbeef0 SW |
71 | sdmmc4_clk_pcc4 { |
72 | nvidia,pins = "sdmmc4_clk_pcc4", | |
73 | "sdmmc4_rst_n_pcc3"; | |
74 | nvidia,function = "sdmmc4"; | |
75 | nvidia,pull = <0>; | |
76 | nvidia,tristate = <0>; | |
77 | }; | |
78 | sdmmc4_dat0_paa0 { | |
79 | nvidia,pins = "sdmmc4_dat0_paa0", | |
80 | "sdmmc4_dat1_paa1", | |
81 | "sdmmc4_dat2_paa2", | |
82 | "sdmmc4_dat3_paa3", | |
83 | "sdmmc4_dat4_paa4", | |
84 | "sdmmc4_dat5_paa5", | |
85 | "sdmmc4_dat6_paa6", | |
86 | "sdmmc4_dat7_paa7"; | |
87 | nvidia,function = "sdmmc4"; | |
88 | nvidia,pull = <2>; | |
89 | nvidia,tristate = <0>; | |
90 | }; | |
8c6a3852 SW |
91 | dap2_fs_pa2 { |
92 | nvidia,pins = "dap2_fs_pa2", | |
93 | "dap2_sclk_pa3", | |
94 | "dap2_din_pa4", | |
95 | "dap2_dout_pa5"; | |
96 | nvidia,function = "i2s1"; | |
97 | nvidia,pull = <0>; | |
98 | nvidia,tristate = <0>; | |
99 | }; | |
6fb11131 WN |
100 | sdio3 { |
101 | nvidia,pins = "drive_sdio3"; | |
102 | nvidia,high-speed-mode = <0>; | |
103 | nvidia,schmitt = <0>; | |
104 | nvidia,pull-down-strength = <46>; | |
105 | nvidia,pull-up-strength = <42>; | |
106 | nvidia,slew-rate-rising = <1>; | |
107 | nvidia,slew-rate-falling = <1>; | |
108 | }; | |
ecfd6c7f LD |
109 | uart3_txd_pw6 { |
110 | nvidia,pins = "uart3_txd_pw6", | |
111 | "uart3_cts_n_pa1", | |
112 | "uart3_rts_n_pc0", | |
113 | "uart3_rxd_pw7"; | |
114 | nvidia,function = "uartc"; | |
115 | nvidia,pull = <0>; | |
116 | nvidia,tristate = <0>; | |
117 | }; | |
e5cbeef0 SW |
118 | }; |
119 | }; | |
120 | ||
64c4e9f8 | 121 | serial@70006000 { |
2a5fdc9a | 122 | status = "okay"; |
64c4e9f8 PDS |
123 | }; |
124 | ||
ecfd6c7f LD |
125 | serial@70006200 { |
126 | compatible = "nvidia,tegra30-hsuart"; | |
127 | status = "okay"; | |
ecfd6c7f LD |
128 | }; |
129 | ||
64c4e9f8 | 130 | i2c@7000c000 { |
2a5fdc9a | 131 | status = "okay"; |
64c4e9f8 PDS |
132 | clock-frequency = <100000>; |
133 | }; | |
134 | ||
135 | i2c@7000c400 { | |
2a5fdc9a | 136 | status = "okay"; |
64c4e9f8 PDS |
137 | clock-frequency = <100000>; |
138 | }; | |
139 | ||
140 | i2c@7000c500 { | |
2a5fdc9a | 141 | status = "okay"; |
64c4e9f8 | 142 | clock-frequency = <100000>; |
b46b0b54 LD |
143 | |
144 | /* ALS and Proximity sensor */ | |
145 | isl29028@44 { | |
146 | compatible = "isil,isl29028"; | |
147 | reg = <0x44>; | |
148 | interrupt-parent = <&gpio>; | |
149 | interrupts = <88 0x04>; /*gpio PL0 */ | |
150 | }; | |
64c4e9f8 PDS |
151 | }; |
152 | ||
153 | i2c@7000c700 { | |
2a5fdc9a | 154 | status = "okay"; |
64c4e9f8 PDS |
155 | clock-frequency = <100000>; |
156 | }; | |
157 | ||
158 | i2c@7000d000 { | |
2a5fdc9a | 159 | status = "okay"; |
64c4e9f8 | 160 | clock-frequency = <100000>; |
8c6a3852 SW |
161 | |
162 | wm8903: wm8903@1a { | |
163 | compatible = "wlf,wm8903"; | |
164 | reg = <0x1a>; | |
165 | interrupt-parent = <&gpio>; | |
166 | interrupts = <179 0x04>; /* gpio PW3 */ | |
167 | ||
168 | gpio-controller; | |
169 | #gpio-cells = <2>; | |
170 | ||
171 | micdet-cfg = <0>; | |
172 | micdet-delay = <100>; | |
173 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; | |
174 | }; | |
331da58c LD |
175 | |
176 | tps62361 { | |
177 | compatible = "ti,tps62361"; | |
178 | reg = <0x60>; | |
179 | ||
180 | regulator-name = "tps62361-vout"; | |
181 | regulator-min-microvolt = <500000>; | |
182 | regulator-max-microvolt = <1500000>; | |
183 | regulator-boot-on; | |
184 | regulator-always-on; | |
185 | ti,vsel0-state-high; | |
186 | ti,vsel1-state-high; | |
187 | }; | |
167e6279 LD |
188 | |
189 | pmic: tps65911@2d { | |
190 | compatible = "ti,tps65911"; | |
191 | reg = <0x2d>; | |
192 | ||
193 | interrupts = <0 86 0x4>; | |
194 | #interrupt-cells = <2>; | |
195 | interrupt-controller; | |
196 | ||
44b12ef7 SW |
197 | ti,system-power-controller; |
198 | ||
167e6279 LD |
199 | #gpio-cells = <2>; |
200 | gpio-controller; | |
201 | ||
202 | vcc1-supply = <&vdd_ac_bat_reg>; | |
203 | vcc2-supply = <&vdd_ac_bat_reg>; | |
204 | vcc3-supply = <&vio_reg>; | |
fa4a9252 | 205 | vcc4-supply = <&vdd_5v0_reg>; |
167e6279 LD |
206 | vcc5-supply = <&vdd_ac_bat_reg>; |
207 | vcc6-supply = <&vdd2_reg>; | |
208 | vcc7-supply = <&vdd_ac_bat_reg>; | |
209 | vccio-supply = <&vdd_ac_bat_reg>; | |
210 | ||
211 | regulators { | |
b9c665d7 | 212 | vdd1_reg: vdd1 { |
167e6279 LD |
213 | regulator-name = "vddio_ddr_1v2"; |
214 | regulator-min-microvolt = <1200000>; | |
215 | regulator-max-microvolt = <1200000>; | |
216 | regulator-always-on; | |
217 | }; | |
218 | ||
b9c665d7 | 219 | vdd2_reg: vdd2 { |
167e6279 LD |
220 | regulator-name = "vdd_1v5_gen"; |
221 | regulator-min-microvolt = <1500000>; | |
222 | regulator-max-microvolt = <1500000>; | |
223 | regulator-always-on; | |
224 | }; | |
225 | ||
b9c665d7 | 226 | vddctrl_reg: vddctrl { |
167e6279 LD |
227 | regulator-name = "vdd_cpu,vdd_sys"; |
228 | regulator-min-microvolt = <1000000>; | |
229 | regulator-max-microvolt = <1000000>; | |
230 | regulator-always-on; | |
231 | }; | |
232 | ||
b9c665d7 | 233 | vio_reg: vio { |
167e6279 LD |
234 | regulator-name = "vdd_1v8_gen"; |
235 | regulator-min-microvolt = <1800000>; | |
236 | regulator-max-microvolt = <1800000>; | |
237 | regulator-always-on; | |
238 | }; | |
239 | ||
b9c665d7 | 240 | ldo1_reg: ldo1 { |
167e6279 LD |
241 | regulator-name = "vdd_pexa,vdd_pexb"; |
242 | regulator-min-microvolt = <1050000>; | |
243 | regulator-max-microvolt = <1050000>; | |
244 | }; | |
245 | ||
b9c665d7 | 246 | ldo2_reg: ldo2 { |
167e6279 LD |
247 | regulator-name = "vdd_sata,avdd_plle"; |
248 | regulator-min-microvolt = <1050000>; | |
249 | regulator-max-microvolt = <1050000>; | |
250 | }; | |
251 | ||
252 | /* LDO3 is not connected to anything */ | |
253 | ||
b9c665d7 | 254 | ldo4_reg: ldo4 { |
167e6279 LD |
255 | regulator-name = "vdd_rtc"; |
256 | regulator-min-microvolt = <1200000>; | |
257 | regulator-max-microvolt = <1200000>; | |
258 | regulator-always-on; | |
259 | }; | |
260 | ||
b9c665d7 | 261 | ldo5_reg: ldo5 { |
fa4a9252 LD |
262 | regulator-name = "vddio_sdmmc,avdd_vdac"; |
263 | regulator-min-microvolt = <3300000>; | |
264 | regulator-max-microvolt = <3300000>; | |
265 | regulator-always-on; | |
266 | }; | |
267 | ||
b9c665d7 | 268 | ldo6_reg: ldo6 { |
167e6279 LD |
269 | regulator-name = "avdd_dsi_csi,pwrdet_mipi"; |
270 | regulator-min-microvolt = <1200000>; | |
271 | regulator-max-microvolt = <1200000>; | |
272 | }; | |
273 | ||
b9c665d7 | 274 | ldo7_reg: ldo7 { |
167e6279 LD |
275 | regulator-name = "vdd_pllm,x,u,a_p_c_s"; |
276 | regulator-min-microvolt = <1200000>; | |
277 | regulator-max-microvolt = <1200000>; | |
278 | regulator-always-on; | |
279 | }; | |
280 | ||
b9c665d7 | 281 | ldo8_reg: ldo8 { |
167e6279 LD |
282 | regulator-name = "vdd_ddr_hs"; |
283 | regulator-min-microvolt = <1000000>; | |
284 | regulator-max-microvolt = <1000000>; | |
285 | regulator-always-on; | |
286 | }; | |
287 | }; | |
288 | }; | |
64c4e9f8 | 289 | }; |
850c4c8f | 290 | |
c42cb1c3 LD |
291 | spi@7000da00 { |
292 | status = "okay"; | |
293 | spi-max-frequency = <25000000>; | |
294 | spi-flash@1 { | |
295 | compatible = "winbond,w25q32"; | |
296 | reg = <1>; | |
297 | spi-max-frequency = <20000000>; | |
298 | }; | |
299 | }; | |
300 | ||
f9eb26a4 | 301 | ahub { |
2a5fdc9a SW |
302 | i2s@70080400 { |
303 | status = "okay"; | |
8c6a3852 SW |
304 | }; |
305 | }; | |
306 | ||
167e6279 LD |
307 | pmc { |
308 | status = "okay"; | |
309 | nvidia,invert-interrupt; | |
a44a019d JL |
310 | nvidia,suspend-mode = <2>; |
311 | nvidia,cpu-pwr-good-time = <2000>; | |
312 | nvidia,cpu-pwr-off-time = <200>; | |
313 | nvidia,core-pwr-good-time = <3845 3845>; | |
314 | nvidia,core-pwr-off-time = <0>; | |
315 | nvidia,core-power-req-active-high; | |
316 | nvidia,sys-clock-req-active-high; | |
167e6279 LD |
317 | }; |
318 | ||
c04abb3a | 319 | sdhci@78000000 { |
2a5fdc9a | 320 | status = "okay"; |
908ab936 | 321 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
c04abb3a SW |
322 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ |
323 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | |
7f217794 | 324 | bus-width = <4>; |
c04abb3a SW |
325 | }; |
326 | ||
c04abb3a | 327 | sdhci@78000600 { |
2a5fdc9a | 328 | status = "okay"; |
7f217794 | 329 | bus-width = <8>; |
7a2617a6 | 330 | non-removable; |
c04abb3a SW |
331 | }; |
332 | ||
7021d122 JL |
333 | clocks { |
334 | compatible = "simple-bus"; | |
335 | #address-cells = <1>; | |
336 | #size-cells = <0>; | |
337 | ||
338 | clk32k_in: clock { | |
339 | compatible = "fixed-clock"; | |
340 | reg=<0>; | |
341 | #clock-cells = <0>; | |
342 | clock-frequency = <32768>; | |
343 | }; | |
344 | }; | |
345 | ||
167e6279 LD |
346 | regulators { |
347 | compatible = "simple-bus"; | |
348 | #address-cells = <1>; | |
349 | #size-cells = <0>; | |
350 | ||
351 | vdd_ac_bat_reg: regulator@0 { | |
352 | compatible = "regulator-fixed"; | |
353 | reg = <0>; | |
354 | regulator-name = "vdd_ac_bat"; | |
355 | regulator-min-microvolt = <5000000>; | |
356 | regulator-max-microvolt = <5000000>; | |
357 | regulator-always-on; | |
358 | }; | |
fa4a9252 LD |
359 | |
360 | cam_1v8_reg: regulator@1 { | |
361 | compatible = "regulator-fixed"; | |
362 | reg = <1>; | |
363 | regulator-name = "cam_1v8"; | |
364 | regulator-min-microvolt = <1800000>; | |
365 | regulator-max-microvolt = <1800000>; | |
366 | enable-active-high; | |
367 | gpio = <&gpio 220 0>; /* gpio PBB4 */ | |
368 | vin-supply = <&vio_reg>; | |
369 | }; | |
370 | ||
371 | cp_5v_reg: regulator@2 { | |
372 | compatible = "regulator-fixed"; | |
373 | reg = <2>; | |
374 | regulator-name = "cp_5v"; | |
375 | regulator-min-microvolt = <5000000>; | |
376 | regulator-max-microvolt = <5000000>; | |
377 | regulator-boot-on; | |
378 | regulator-always-on; | |
379 | enable-active-high; | |
380 | gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ | |
381 | }; | |
382 | ||
383 | emmc_3v3_reg: regulator@3 { | |
384 | compatible = "regulator-fixed"; | |
385 | reg = <3>; | |
386 | regulator-name = "emmc_3v3"; | |
387 | regulator-min-microvolt = <3300000>; | |
388 | regulator-max-microvolt = <3300000>; | |
389 | regulator-always-on; | |
390 | regulator-boot-on; | |
391 | enable-active-high; | |
392 | gpio = <&gpio 25 0>; /* gpio PD1 */ | |
393 | vin-supply = <&sys_3v3_reg>; | |
394 | }; | |
395 | ||
396 | modem_3v3_reg: regulator@4 { | |
397 | compatible = "regulator-fixed"; | |
398 | reg = <4>; | |
399 | regulator-name = "modem_3v3"; | |
400 | regulator-min-microvolt = <3300000>; | |
401 | regulator-max-microvolt = <3300000>; | |
402 | enable-active-high; | |
403 | gpio = <&gpio 30 0>; /* gpio PD6 */ | |
404 | }; | |
405 | ||
406 | pex_hvdd_3v3_reg: regulator@5 { | |
407 | compatible = "regulator-fixed"; | |
408 | reg = <5>; | |
409 | regulator-name = "pex_hvdd_3v3"; | |
410 | regulator-min-microvolt = <3300000>; | |
411 | regulator-max-microvolt = <3300000>; | |
412 | enable-active-high; | |
413 | gpio = <&gpio 95 0>; /* gpio PL7 */ | |
414 | vin-supply = <&sys_3v3_reg>; | |
415 | }; | |
416 | ||
417 | vdd_cam1_ldo_reg: regulator@6 { | |
418 | compatible = "regulator-fixed"; | |
419 | reg = <6>; | |
420 | regulator-name = "vdd_cam1_ldo"; | |
421 | regulator-min-microvolt = <2800000>; | |
422 | regulator-max-microvolt = <2800000>; | |
423 | enable-active-high; | |
424 | gpio = <&gpio 142 0>; /* gpio PR6 */ | |
425 | vin-supply = <&sys_3v3_reg>; | |
426 | }; | |
427 | ||
428 | vdd_cam2_ldo_reg: regulator@7 { | |
429 | compatible = "regulator-fixed"; | |
430 | reg = <7>; | |
431 | regulator-name = "vdd_cam2_ldo"; | |
432 | regulator-min-microvolt = <2800000>; | |
433 | regulator-max-microvolt = <2800000>; | |
434 | enable-active-high; | |
435 | gpio = <&gpio 143 0>; /* gpio PR7 */ | |
436 | vin-supply = <&sys_3v3_reg>; | |
437 | }; | |
438 | ||
439 | vdd_cam3_ldo_reg: regulator@8 { | |
440 | compatible = "regulator-fixed"; | |
441 | reg = <8>; | |
442 | regulator-name = "vdd_cam3_ldo"; | |
443 | regulator-min-microvolt = <3300000>; | |
444 | regulator-max-microvolt = <3300000>; | |
445 | enable-active-high; | |
446 | gpio = <&gpio 144 0>; /* gpio PS0 */ | |
447 | vin-supply = <&sys_3v3_reg>; | |
448 | }; | |
449 | ||
450 | vdd_com_reg: regulator@9 { | |
451 | compatible = "regulator-fixed"; | |
452 | reg = <9>; | |
453 | regulator-name = "vdd_com"; | |
454 | regulator-min-microvolt = <3300000>; | |
455 | regulator-max-microvolt = <3300000>; | |
6fb11131 WN |
456 | regulator-always-on; |
457 | regulator-boot-on; | |
fa4a9252 LD |
458 | enable-active-high; |
459 | gpio = <&gpio 24 0>; /* gpio PD0 */ | |
460 | vin-supply = <&sys_3v3_reg>; | |
461 | }; | |
462 | ||
463 | vdd_fuse_3v3_reg: regulator@10 { | |
464 | compatible = "regulator-fixed"; | |
465 | reg = <10>; | |
466 | regulator-name = "vdd_fuse_3v3"; | |
467 | regulator-min-microvolt = <3300000>; | |
468 | regulator-max-microvolt = <3300000>; | |
469 | enable-active-high; | |
470 | gpio = <&gpio 94 0>; /* gpio PL6 */ | |
471 | vin-supply = <&sys_3v3_reg>; | |
472 | }; | |
473 | ||
474 | vdd_pnl1_reg: regulator@11 { | |
475 | compatible = "regulator-fixed"; | |
476 | reg = <11>; | |
477 | regulator-name = "vdd_pnl1"; | |
478 | regulator-min-microvolt = <3300000>; | |
479 | regulator-max-microvolt = <3300000>; | |
480 | regulator-always-on; | |
481 | regulator-boot-on; | |
482 | enable-active-high; | |
483 | gpio = <&gpio 92 0>; /* gpio PL4 */ | |
484 | vin-supply = <&sys_3v3_reg>; | |
485 | }; | |
486 | ||
487 | vdd_vid_reg: regulator@12 { | |
488 | compatible = "regulator-fixed"; | |
489 | reg = <12>; | |
490 | regulator-name = "vddio_vid"; | |
491 | regulator-min-microvolt = <5000000>; | |
492 | regulator-max-microvolt = <5000000>; | |
493 | enable-active-high; | |
494 | gpio = <&gpio 152 0>; /* GPIO PT0 */ | |
495 | gpio-open-drain; | |
496 | vin-supply = <&vdd_5v0_reg>; | |
497 | }; | |
167e6279 LD |
498 | }; |
499 | ||
8c6a3852 SW |
500 | sound { |
501 | compatible = "nvidia,tegra-audio-wm8903-cardhu", | |
502 | "nvidia,tegra-audio-wm8903"; | |
503 | nvidia,model = "NVIDIA Tegra Cardhu"; | |
504 | ||
505 | nvidia,audio-routing = | |
506 | "Headphone Jack", "HPOUTR", | |
507 | "Headphone Jack", "HPOUTL", | |
508 | "Int Spk", "ROP", | |
509 | "Int Spk", "RON", | |
510 | "Int Spk", "LOP", | |
511 | "Int Spk", "LON", | |
512 | "Mic Jack", "MICBIAS", | |
513 | "IN1L", "Mic Jack"; | |
514 | ||
515 | nvidia,i2s-controller = <&tegra_i2s1>; | |
516 | nvidia,audio-codec = <&wm8903>; | |
517 | ||
518 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | |
519 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | |
f9cd2b3b SW |
520 | |
521 | clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; | |
522 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
8c6a3852 | 523 | }; |
64c4e9f8 | 524 | }; |