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[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
CommitLineData
1bd0bd49 1#include "tegra30.dtsi"
64c4e9f8 2
640a7af5
LD		 3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
64c4e9f8
PDS		 26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
553c0a20 30 aliases {
763fbff2 31 rtc0 = "/i2c@7000d000/tps65911@2d";
553c0a20 32 rtc1 = "/rtc@7000e000";
c4574aa0
OJ		 33 serial0 = &uarta;
34 serial1 = &uartc;
553c0a20
SW		 35 };
36
64c4e9f8 37 memory {
95decf84 38 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 39 };
40
58ecb23f 41 pcie-controller@00003000 {
89e7ada4 42 status = "okay";
cca8614d
TR		 43
44 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
45 avdd-pexb-supply = <&ldo1_reg>;
46 vdd-pexb-supply = <&ldo1_reg>;
47 avdd-pex-pll-supply = <&ldo1_reg>;
48 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
49 vddio-pex-ctl-supply = <&sys_3v3_reg>;
50 avdd-plle-supply = <&ldo2_reg>;
51
89e7ada4
JA		 52 pci@1,0 {
53 nvidia,num-lanes = <4>;
54 };
55
56 pci@2,0 {
57 nvidia,num-lanes = <1>;
58 };
59
60 pci@3,0 {
61 status = "okay";
62 nvidia,num-lanes = <1>;
63 };
64 };
65
02b1fea2
TR		 66 host1x@50000000 {
67 dc@54200000 {
68 rgb {
69 status = "okay";
70
71 nvidia,panel = <&panel>;
72 };
73 };
74 };
75
58ecb23f 76 pinmux@70000868 {
e5cbeef0
SW		 77 pinctrl-names = "default";
78 pinctrl-0 = <&state_default>;
79
80 state_default: pinmux {
81 sdmmc1_clk_pz0 {
82 nvidia,pins = "sdmmc1_clk_pz0";
83 nvidia,function = "sdmmc1";
a47c662a
LD		 84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 86 };
87 sdmmc1_cmd_pz1 {
88 nvidia,pins = "sdmmc1_cmd_pz1",
89 "sdmmc1_dat0_py7",
90 "sdmmc1_dat1_py6",
91 "sdmmc1_dat2_py5",
92 "sdmmc1_dat3_py4";
93 nvidia,function = "sdmmc1";
a47c662a
LD		 94 nvidia,pull = <TEGRA_PIN_PULL_UP>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 96 };
6fb11131
WN		 97 sdmmc3_clk_pa6 {
98 nvidia,pins = "sdmmc3_clk_pa6";
99 nvidia,function = "sdmmc3";
a47c662a
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 102 };
103 sdmmc3_cmd_pa7 {
104 nvidia,pins = "sdmmc3_cmd_pa7",
105 "sdmmc3_dat0_pb7",
106 "sdmmc3_dat1_pb6",
107 "sdmmc3_dat2_pb5",
108 "sdmmc3_dat3_pb4";
109 nvidia,function = "sdmmc3";
a47c662a
LD		 110 nvidia,pull = <TEGRA_PIN_PULL_UP>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 112 };
e5cbeef0
SW		 113 sdmmc4_clk_pcc4 {
114 nvidia,pins = "sdmmc4_clk_pcc4",
115 "sdmmc4_rst_n_pcc3";
116 nvidia,function = "sdmmc4";
a47c662a
LD		 117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 119 };
120 sdmmc4_dat0_paa0 {
121 nvidia,pins = "sdmmc4_dat0_paa0",
122 "sdmmc4_dat1_paa1",
123 "sdmmc4_dat2_paa2",
124 "sdmmc4_dat3_paa3",
125 "sdmmc4_dat4_paa4",
126 "sdmmc4_dat5_paa5",
127 "sdmmc4_dat6_paa6",
128 "sdmmc4_dat7_paa7";
129 nvidia,function = "sdmmc4";
a47c662a
LD		 130 nvidia,pull = <TEGRA_PIN_PULL_UP>;
131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 132 };
8c6a3852
SW		 133 dap2_fs_pa2 {
134 nvidia,pins = "dap2_fs_pa2",
135 "dap2_sclk_pa3",
136 "dap2_din_pa4",
137 "dap2_dout_pa5";
138 nvidia,function = "i2s1";
a47c662a
LD		 139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 141 };
6fb11131
WN		 142 sdio3 {
143 nvidia,pins = "drive_sdio3";
a47c662a
LD		 144 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
145 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 146 nvidia,pull-down-strength = <46>;
147 nvidia,pull-up-strength = <42>;
a47c662a
LD		 148 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
149 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 150 };
ecfd6c7f
LD		 151 uart3_txd_pw6 {
152 nvidia,pins = "uart3_txd_pw6",
153 "uart3_cts_n_pa1",
154 "uart3_rts_n_pc0",
155 "uart3_rxd_pw7";
156 nvidia,function = "uartc";
a47c662a
LD		 157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 159 };
e5cbeef0
SW		 160 };
161 };
162
64c4e9f8 163 serial@70006000 {
2a5fdc9a 164 status = "okay";
64c4e9f8
PDS		 165 };
166
ecfd6c7f
LD		 167 serial@70006200 {
168 compatible = "nvidia,tegra30-hsuart";
169 status = "okay";
ecfd6c7f
LD		 170 };
171
02b1fea2
TR		 172 pwm@7000a000 {
173 status = "okay";
174 };
175
176 panelddc: i2c@7000c000 {
2a5fdc9a 177 status = "okay";
64c4e9f8
PDS		 178 clock-frequency = <100000>;
179 };
180
181 i2c@7000c400 {
2a5fdc9a 182 status = "okay";
64c4e9f8
PDS		 183 clock-frequency = <100000>;
184 };
185
186 i2c@7000c500 {
2a5fdc9a 187 status = "okay";
64c4e9f8 188 clock-frequency = <100000>;
b46b0b54
LD		 189
190 /* ALS and Proximity sensor */
191 isl29028@44 {
192 compatible = "isil,isl29028";
193 reg = <0x44>;
194 interrupt-parent = <&gpio>;
6cecf916 195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 196 };
40431d16
BW		 197
198 i2cmux@70 {
199 compatible = "nxp,pca9546";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x70>;
203 };
64c4e9f8
PDS		 204 };
205
206 i2c@7000c700 {
2a5fdc9a 207 status = "okay";
64c4e9f8
PDS		 208 clock-frequency = <100000>;
209 };
210
211 i2c@7000d000 {
2a5fdc9a 212 status = "okay";
64c4e9f8 213 clock-frequency = <100000>;
8c6a3852
SW		 214
215 wm8903: wm8903@1a {
216 compatible = "wlf,wm8903";
217 reg = <0x1a>;
218 interrupt-parent = <&gpio>;
6cecf916 219 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 220
221 gpio-controller;
222 #gpio-cells = <2>;
223
224 micdet-cfg = <0>;
225 micdet-delay = <100>;
226 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
227 };
331da58c 228
167e6279
LD		 229 pmic: tps65911@2d {
230 compatible = "ti,tps65911";
231 reg = <0x2d>;
232
6cecf916 233 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 234 #interrupt-cells = <2>;
235 interrupt-controller;
236
44b12ef7
SW		 237 ti,system-power-controller;
238
167e6279
LD		 239 #gpio-cells = <2>;
240 gpio-controller;
241
242 vcc1-supply = <&vdd_ac_bat_reg>;
243 vcc2-supply = <&vdd_ac_bat_reg>;
244 vcc3-supply = <&vio_reg>;
fa4a9252 245 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 246 vcc5-supply = <&vdd_ac_bat_reg>;
247 vcc6-supply = <&vdd2_reg>;
248 vcc7-supply = <&vdd_ac_bat_reg>;
249 vccio-supply = <&vdd_ac_bat_reg>;
250
251 regulators {
b9c665d7 252 vdd1_reg: vdd1 {
167e6279
LD		 253 regulator-name = "vddio_ddr_1v2";
254 regulator-min-microvolt = <1200000>;
255 regulator-max-microvolt = <1200000>;
256 regulator-always-on;
257 };
258
b9c665d7 259 vdd2_reg: vdd2 {
167e6279
LD		 260 regulator-name = "vdd_1v5_gen";
261 regulator-min-microvolt = <1500000>;
262 regulator-max-microvolt = <1500000>;
263 regulator-always-on;
264 };
265
b9c665d7 266 vddctrl_reg: vddctrl {
167e6279
LD		 267 regulator-name = "vdd_cpu,vdd_sys";
268 regulator-min-microvolt = <1000000>;
269 regulator-max-microvolt = <1000000>;
270 regulator-always-on;
271 };
272
b9c665d7 273 vio_reg: vio {
167e6279
LD		 274 regulator-name = "vdd_1v8_gen";
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <1800000>;
277 regulator-always-on;
278 };
279
b9c665d7 280 ldo1_reg: ldo1 {
167e6279
LD		 281 regulator-name = "vdd_pexa,vdd_pexb";
282 regulator-min-microvolt = <1050000>;
283 regulator-max-microvolt = <1050000>;
284 };
285
b9c665d7 286 ldo2_reg: ldo2 {
167e6279
LD		 287 regulator-name = "vdd_sata,avdd_plle";
288 regulator-min-microvolt = <1050000>;
289 regulator-max-microvolt = <1050000>;
290 };
291
292 /* LDO3 is not connected to anything */
293
b9c665d7 294 ldo4_reg: ldo4 {
167e6279
LD		 295 regulator-name = "vdd_rtc";
296 regulator-min-microvolt = <1200000>;
297 regulator-max-microvolt = <1200000>;
298 regulator-always-on;
299 };
300
b9c665d7 301 ldo5_reg: ldo5 {
fa4a9252
LD		 302 regulator-name = "vddio_sdmmc,avdd_vdac";
303 regulator-min-microvolt = <3300000>;
304 regulator-max-microvolt = <3300000>;
305 regulator-always-on;
306 };
307
b9c665d7 308 ldo6_reg: ldo6 {
167e6279
LD		 309 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
310 regulator-min-microvolt = <1200000>;
311 regulator-max-microvolt = <1200000>;
312 };
313
b9c665d7 314 ldo7_reg: ldo7 {
167e6279
LD		 315 regulator-name = "vdd_pllm,x,u,a_p_c_s";
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
318 regulator-always-on;
319 };
320
b9c665d7 321 ldo8_reg: ldo8 {
167e6279
LD		 322 regulator-name = "vdd_ddr_hs";
323 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>;
325 regulator-always-on;
326 };
327 };
328 };
74ecab27 329
7c7de6b0 330 temperature-sensor@4c {
74ecab27
WN		 331 compatible = "onnn,nct1008";
332 reg = <0x4c>;
7c7de6b0 333 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 334 interrupt-parent = <&gpio>;
335 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
336 };
2b8584d5 337
58ecb23f 338 tps62361@60 {
2b8584d5
SW		 339 compatible = "ti,tps62361";
340 reg = <0x60>;
341
342 regulator-name = "tps62361-vout";
343 regulator-min-microvolt = <500000>;
344 regulator-max-microvolt = <1500000>;
345 regulator-boot-on;
346 regulator-always-on;
347 ti,vsel0-state-high;
348 ti,vsel1-state-high;
349 };
64c4e9f8 350 };
850c4c8f 351
c42cb1c3
LD		 352 spi@7000da00 {
353 status = "okay";
354 spi-max-frequency = <25000000>;
355 spi-flash@1 {
356 compatible = "winbond,w25q32";
357 reg = <1>;
358 spi-max-frequency = <20000000>;
359 };
360 };
361
58ecb23f 362 pmc@7000e400 {
167e6279
LD		 363 status = "okay";
364 nvidia,invert-interrupt;
47d2d63b 365 nvidia,suspend-mode = <1>;
a44a019d
JL		 366 nvidia,cpu-pwr-good-time = <2000>;
367 nvidia,cpu-pwr-off-time = <200>;
368 nvidia,core-pwr-good-time = <3845 3845>;
369 nvidia,core-pwr-off-time = <0>;
370 nvidia,core-power-req-active-high;
371 nvidia,sys-clock-req-active-high;
167e6279
LD		 372 };
373
57899053
SW		 374 ahub@70080000 {
375 i2s@70080400 {
376 status = "okay";
377 };
378 };
379
c04abb3a 380 sdhci@78000000 {
2a5fdc9a 381 status = "okay";
3325f1bc
SW		 382 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
383 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
384 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 385 bus-width = <4>;
c04abb3a
SW		 386 };
387
c04abb3a 388 sdhci@78000600 {
2a5fdc9a 389 status = "okay";
7f217794 390 bus-width = <8>;
7a2617a6 391 non-removable;
c04abb3a
SW		 392 };
393
cc34c9f7
TT		 394 usb@7d008000 {
395 status = "okay";
396 };
397
398 usb-phy@7d008000 {
399 vbus-supply = <&usb3_vbus_reg>;
400 status = "okay";
401 };
402
02b1fea2
TR		 403 backlight: backlight {
404 compatible = "pwm-backlight";
405
406 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
407 power-supply = <&vdd_bl_reg>;
408 pwms = <&pwm 0 5000000>;
409
410 brightness-levels = <0 4 8 16 32 64 128 255>;
411 default-brightness-level = <6>;
412 };
413
7021d122
JL		 414 clocks {
415 compatible = "simple-bus";
416 #address-cells = <1>;
417 #size-cells = <0>;
418
58ecb23f 419 clk32k_in: clock@0 {
7021d122
JL		 420 compatible = "fixed-clock";
421 reg=<0>;
422 #clock-cells = <0>;
423 clock-frequency = <32768>;
424 };
425 };
426
02b1fea2
TR		 427 panel: panel {
428 compatible = "chunghwa,claa101wb01", "simple-panel";
429 ddc-i2c-bus = <&panelddc>;
430
431 power-supply = <&vdd_pnl1_reg>;
432 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
433
434 backlight = <&backlight>;
435 };
436
167e6279
LD		 437 regulators {
438 compatible = "simple-bus";
439 #address-cells = <1>;
440 #size-cells = <0>;
441
442 vdd_ac_bat_reg: regulator@0 {
443 compatible = "regulator-fixed";
444 reg = <0>;
445 regulator-name = "vdd_ac_bat";
446 regulator-min-microvolt = <5000000>;
447 regulator-max-microvolt = <5000000>;
448 regulator-always-on;
449 };
fa4a9252
LD		 450
451 cam_1v8_reg: regulator@1 {
452 compatible = "regulator-fixed";
453 reg = <1>;
454 regulator-name = "cam_1v8";
455 regulator-min-microvolt = <1800000>;
456 regulator-max-microvolt = <1800000>;
457 enable-active-high;
3325f1bc 458 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 459 vin-supply = <&vio_reg>;
460 };
461
462 cp_5v_reg: regulator@2 {
463 compatible = "regulator-fixed";
464 reg = <2>;
465 regulator-name = "cp_5v";
466 regulator-min-microvolt = <5000000>;
467 regulator-max-microvolt = <5000000>;
468 regulator-boot-on;
469 regulator-always-on;
470 enable-active-high;
3325f1bc 471 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 472 };
473
474 emmc_3v3_reg: regulator@3 {
475 compatible = "regulator-fixed";
476 reg = <3>;
477 regulator-name = "emmc_3v3";
478 regulator-min-microvolt = <3300000>;
479 regulator-max-microvolt = <3300000>;
480 regulator-always-on;
481 regulator-boot-on;
482 enable-active-high;
3325f1bc 483 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 484 vin-supply = <&sys_3v3_reg>;
485 };
486
487 modem_3v3_reg: regulator@4 {
488 compatible = "regulator-fixed";
489 reg = <4>;
490 regulator-name = "modem_3v3";
491 regulator-min-microvolt = <3300000>;
492 regulator-max-microvolt = <3300000>;
493 enable-active-high;
3325f1bc 494 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 495 };
496
497 pex_hvdd_3v3_reg: regulator@5 {
498 compatible = "regulator-fixed";
499 reg = <5>;
500 regulator-name = "pex_hvdd_3v3";
501 regulator-min-microvolt = <3300000>;
502 regulator-max-microvolt = <3300000>;
503 enable-active-high;
3325f1bc 504 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 505 vin-supply = <&sys_3v3_reg>;
506 };
507
508 vdd_cam1_ldo_reg: regulator@6 {
509 compatible = "regulator-fixed";
510 reg = <6>;
511 regulator-name = "vdd_cam1_ldo";
512 regulator-min-microvolt = <2800000>;
513 regulator-max-microvolt = <2800000>;
514 enable-active-high;
3325f1bc 515 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 516 vin-supply = <&sys_3v3_reg>;
517 };
518
519 vdd_cam2_ldo_reg: regulator@7 {
520 compatible = "regulator-fixed";
521 reg = <7>;
522 regulator-name = "vdd_cam2_ldo";
523 regulator-min-microvolt = <2800000>;
524 regulator-max-microvolt = <2800000>;
525 enable-active-high;
3325f1bc 526 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 527 vin-supply = <&sys_3v3_reg>;
528 };
529
530 vdd_cam3_ldo_reg: regulator@8 {
531 compatible = "regulator-fixed";
532 reg = <8>;
533 regulator-name = "vdd_cam3_ldo";
534 regulator-min-microvolt = <3300000>;
535 regulator-max-microvolt = <3300000>;
536 enable-active-high;
3325f1bc 537 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 538 vin-supply = <&sys_3v3_reg>;
539 };
540
541 vdd_com_reg: regulator@9 {
542 compatible = "regulator-fixed";
543 reg = <9>;
544 regulator-name = "vdd_com";
545 regulator-min-microvolt = <3300000>;
546 regulator-max-microvolt = <3300000>;
6fb11131
WN		 547 regulator-always-on;
548 regulator-boot-on;
fa4a9252 549 enable-active-high;
3325f1bc 550 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 551 vin-supply = <&sys_3v3_reg>;
552 };
553
554 vdd_fuse_3v3_reg: regulator@10 {
555 compatible = "regulator-fixed";
556 reg = <10>;
557 regulator-name = "vdd_fuse_3v3";
558 regulator-min-microvolt = <3300000>;
559 regulator-max-microvolt = <3300000>;
560 enable-active-high;
3325f1bc 561 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 562 vin-supply = <&sys_3v3_reg>;
563 };
564
565 vdd_pnl1_reg: regulator@11 {
566 compatible = "regulator-fixed";
567 reg = <11>;
568 regulator-name = "vdd_pnl1";
569 regulator-min-microvolt = <3300000>;
570 regulator-max-microvolt = <3300000>;
571 regulator-always-on;
572 regulator-boot-on;
573 enable-active-high;
3325f1bc 574 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 575 vin-supply = <&sys_3v3_reg>;
576 };
577
578 vdd_vid_reg: regulator@12 {
579 compatible = "regulator-fixed";
580 reg = <12>;
581 regulator-name = "vddio_vid";
582 regulator-min-microvolt = <5000000>;
583 regulator-max-microvolt = <5000000>;
584 enable-active-high;
3325f1bc 585 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 586 gpio-open-drain;
587 vin-supply = <&vdd_5v0_reg>;
588 };
167e6279
LD		 589 };
590
8c6a3852
SW		 591 sound {
592 compatible = "nvidia,tegra-audio-wm8903-cardhu",
593 "nvidia,tegra-audio-wm8903";
594 nvidia,model = "NVIDIA Tegra Cardhu";
595
596 nvidia,audio-routing =
597 "Headphone Jack", "HPOUTR",
598 "Headphone Jack", "HPOUTL",
599 "Int Spk", "ROP",
600 "Int Spk", "RON",
601 "Int Spk", "LOP",
602 "Int Spk", "LON",
603 "Mic Jack", "MICBIAS",
604 "IN1L", "Mic Jack";
605
606 nvidia,i2s-controller = <&tegra_i2s1>;
607 nvidia,audio-codec = <&wm8903>;
608
3325f1bc
SW		 609 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
610 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
611 GPIO_ACTIVE_HIGH>;
f9cd2b3b 612
05849c93
HD		 613 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
614 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
615 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 616 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 617 };
64c4e9f8 618};
Ubuntu Eoan Linux kernel mirror