[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / tegra30-colibri.dtsi

#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"

/*
 * Toradex Colibri T30 Module Device Tree
 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
 */
/ {
	model = "Toradex Colibri T30";
	compatible = "toradex,colibri_t30", "nvidia,tegra30";

	memory {
		reg = <0x80000000 0x40000000>;
	};

	host1x@50000000 {
		hdmi@54280000 {
			vdd-supply = <&avdd_hdmi_3v3_reg>;
			pll-supply = <&avdd_hdmi_pll_1v8_reg>;

			nvidia,hpd-gpio =
				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
			nvidia,ddc-i2c-bus = <&hdmiddc>;
		};
	};

	pinmux@70000868 {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			/* Analogue Audio (On-module) */
			clk1_out_pw4 {
				nvidia,pins = "clk1_out_pw4";
				nvidia,function = "extperiph1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			dap3_fs_pp0 {
				nvidia,pins =	"dap3_fs_pp0",
						"dap3_sclk_pp3",
						"dap3_din_pp1",
						"dap3_dout_pp2";
				nvidia,function = "i2s2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri BL_ON */
			pv2 {
				nvidia,pins = "pv2";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri Backlight PWM<A> */
			sdmmc3_dat3_pb4 {
				nvidia,pins = "sdmmc3_dat3_pb4";
				nvidia,function = "pwm0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri CAN_INT */
			kb_row8_ps0 {
				nvidia,pins = "kb_row8_ps0";
				nvidia,function = "kbc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			/*
			 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
			 * todays display need DE, disable LCD_M1
			 */
			lcd_m1_pw1 {
				nvidia,pins = "lcd_m1_pw1";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			/* Colibri MMC */
			kb_row10_ps2 {
				nvidia,pins = "kb_row10_ps2";
				nvidia,function = "sdmmc2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			kb_row11_ps3 {
				nvidia,pins = "kb_row11_ps3",
					      "kb_row12_ps4",
					      "kb_row13_ps5",
					      "kb_row14_ps6",
					      "kb_row15_ps7";
				nvidia,function = "sdmmc2";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri SSP */
			ulpi_clk_py0 {
				nvidia,pins = "ulpi_clk_py0",
					      "ulpi_dir_py1",
					      "ulpi_nxt_py2",
					      "ulpi_stp_py3";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			sdmmc3_dat6_pd3 {
				nvidia,pins = "sdmmc3_dat6_pd3",
					      "sdmmc3_dat7_pd4";
				nvidia,function = "spdif";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};

			/* Colibri UART_A */
			ulpi_data0 {
				nvidia,pins = "ulpi_data0_po1",
					      "ulpi_data1_po2",
					      "ulpi_data2_po3",
					      "ulpi_data3_po4",
					      "ulpi_data4_po5",
					      "ulpi_data5_po6",
					      "ulpi_data6_po7",
					      "ulpi_data7_po0";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri UART_B */
			gmi_a16_pj7 {
				nvidia,pins = "gmi_a16_pj7",
					      "gmi_a17_pb0",
					      "gmi_a18_pb1",
					      "gmi_a19_pk7";
				nvidia,function = "uartd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Colibri UART_C */
			uart2_rxd {
				nvidia,pins = "uart2_rxd_pc3",
					      "uart2_txd_pc2";
				nvidia,function = "uartb";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* eMMC */
			sdmmc4_clk_pcc4 {
				nvidia,pins = "sdmmc4_clk_pcc4",
					      "sdmmc4_rst_n_pcc3";
				nvidia,function = "sdmmc4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			sdmmc4_dat0_paa0 {
				nvidia,pins = "sdmmc4_dat0_paa0",
					      "sdmmc4_dat1_paa1",
					      "sdmmc4_dat2_paa2",
					      "sdmmc4_dat3_paa3",
					      "sdmmc4_dat4_paa4",
					      "sdmmc4_dat5_paa5",
					      "sdmmc4_dat6_paa6",
					      "sdmmc4_dat7_paa7";
				nvidia,function = "sdmmc4";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};

			/* Power I2C (On-module) */
			pwr_i2c_scl_pz6 {
				nvidia,pins = "pwr_i2c_scl_pz6",
					      "pwr_i2c_sda_pz7";
				nvidia,function = "i2cpwr";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
			};

			/*
			 * THERMD_ALERT#, unlatched I2C address pin of LM95245
			 * temperature sensor therefore requires disabling for
			 * now
			 */
			lcd_dc1_pd2 {
				nvidia,pins = "lcd_dc1_pd2";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			/* TOUCH_PEN_INT# */
			pv0 {
				nvidia,pins = "pv0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
		};
	};

	hdmiddc: i2c@7000c700 {
		clock-frequency = <100000>;
	};

	/*
	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	 * touch screen controller
	 */
	i2c@7000d000 {
		status = "okay";
		clock-frequency = <100000>;

		/* SGTL5000 audio codec */
		sgtl5000: codec@a {
			compatible = "fsl,sgtl5000";
			reg = <0x0a>;
			VDDA-supply = <&sys_3v3_reg>;
			VDDIO-supply = <&sys_3v3_reg>;
			clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
		};

		pmic: tps65911@2d {
			compatible = "ti,tps65911";
			reg = <0x2d>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <2>;
			interrupt-controller;

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

			vcc1-supply = <&sys_3v3_reg>;
			vcc2-supply = <&sys_3v3_reg>;
			vcc3-supply = <&vio_reg>;
			vcc4-supply = <&sys_3v3_reg>;
			vcc5-supply = <&sys_3v3_reg>;
			vcc6-supply = <&vio_reg>;
			vcc7-supply = <&charge_pump_5v0_reg>;
			vccio-supply = <&sys_3v3_reg>;

			regulators {
				/* SW1: +V1.35_VDDIO_DDR */
				vdd1_reg: vdd1 {
					regulator-name = "vddio_ddr_1v35";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
				};

				/* SW2: unused */

				/* SW CTRL: +V1.0_VDD_CPU */
				vddctrl_reg: vddctrl {
					regulator-name = "vdd_cpu,vdd_sys";
					regulator-min-microvolt = <1150000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
				};

				/* SWIO: +V1.8 */
				vio_reg: vio {
					regulator-name = "vdd_1v8_gen";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				/* LDO1: unused */

				/*
				 * EN_+V3.3 switching via FET:
				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
				 * see also 3v3 fixed supply
				 */
				ldo2_reg: ldo2 {
					regulator-name = "en_3v3";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				/* LDO3: unused */

				/* +V1.2_VDD_RTC */
				ldo4_reg: ldo4 {
					regulator-name = "vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				/*
				 * +V2.8_AVDD_VDAC:
				 * only required for analog RGB
				 */
				ldo5_reg: ldo5 {
					regulator-name = "avdd_vdac";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					regulator-always-on;
				};

				/*
				 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
				 * but LDO6 can't set voltage in 50mV
				 * granularity
				 */
				ldo6_reg: ldo6 {
					regulator-name = "avdd_plle";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
				};

				/* +V1.2_AVDD_PLL */
				ldo7_reg: ldo7 {
					regulator-name = "avdd_pll";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				/* +V1.0_VDD_DDR_HS */
				ldo8_reg: ldo8 {
					regulator-name = "vdd_ddr_hs";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};
			};
		};

		/* STMPE811 touch screen controller */
		stmpe811@41 {
			compatible = "st,stmpe811";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x41>;
			interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
			interrupt-parent = <&gpio>;
			interrupt-controller;
			id = <0>;
			blocks = <0x5>;
			irq-trigger = <0x1>;

			stmpe_touchscreen {
				compatible = "st,stmpe-ts";
				reg = <0>;
				/* 3.25 MHz ADC clock speed */
				st,adc-freq = <1>;
				/* 8 sample average control */
				st,ave-ctrl = <3>;
				/* 7 length fractional part in z */
				st,fraction-z = <7>;
				/*
				 * 50 mA typical 80 mA max touchscreen drivers
				 * current limit value
				 */
				st,i-drive = <1>;
				/* 12-bit ADC */
				st,mod-12b = <1>;
				/* internal ADC reference */
				st,ref-sel = <0>;
				/* ADC converstion time: 80 clocks */
				st,sample-time = <4>;
				/* 1 ms panel driver settling time */
				st,settling = <3>;
				/* 5 ms touch detect interrupt delay */
				st,touch-det-delay = <5>;
			};
		};

		/*
		 * LM95245 temperature sensor
		 * Note: OVERT_N directly connected to PMIC PWRDN
		 */
		temp-sensor@4c {
			compatible = "national,lm95245";
			reg = <0x4c>;
		};

		/* SW: +V1.2_VDD_CORE */
		tps62362@60 {
			compatible = "ti,tps62362";
			reg = <0x60>;

			regulator-name = "tps62362-vout";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <1400000>;
			regulator-boot-on;
			regulator-always-on;
			ti,vsel0-state-low;
			/* VSEL1: EN_CORE_DVFS_N low for DVFS */
			ti,vsel1-state-low;
		};
	};

	pmc@7000e400 {
		nvidia,invert-interrupt;
		nvidia,suspend-mode = <1>;
		nvidia,cpu-pwr-good-time = <5000>;
		nvidia,cpu-pwr-off-time = <5000>;
		nvidia,core-pwr-good-time = <3845 3845>;
		nvidia,core-pwr-off-time = <0>;
		nvidia,core-power-req-active-high;
		nvidia,sys-clock-req-active-high;
	};

	ahub@70080000 {
		i2s@70080500 {
			status = "okay";
		};
	};

	/* eMMC */
	sdhci@78000600 {
		status = "okay";
		bus-width = <8>;
		non-removable;
	};

	/* EHCI instance 1: USB2_DP/N -> AX88772B */
	usb@7d004000 {
		status = "okay";
	};

	usb-phy@7d004000 {
		status = "okay";
		nvidia,is-wired = <1>;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clk@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		avdd_hdmi_pll_1v8_reg: regulator@100 {
			compatible = "regulator-fixed";
			reg = <100>;
			regulator-name = "+V1.8_AVDD_HDMI_PLL";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			enable-active-high;
			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
			vin-supply = <&vio_reg>;
		};

		sys_3v3_reg: regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		avdd_hdmi_3v3_reg: regulator@102 {
			compatible = "regulator-fixed";
			reg = <102>;
			regulator-name = "+V3.3_AVDD_HDMI";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
			vin-supply = <&sys_3v3_reg>;
		};

		charge_pump_5v0_reg: regulator@103 {
			compatible = "regulator-fixed";
			reg = <103>;
			regulator-name = "5v0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
			     "nvidia,tegra-audio-sgtl5000";
		nvidia,model = "Toradex Colibri T30";
		nvidia,audio-routing =
			"Headphone Jack", "HP_OUT",
			"LINE_IN", "Line In Jack",
			"MIC_IN", "Mic Jack";
		nvidia,i2s-controller = <&tegra_i2s2>;
		nvidia,audio-codec = <&sgtl5000>;
		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA30_CLK_EXTERN1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";
	};
};
Commit	Line	Data
446e9c63 SA	1	#include <dt-bindings/input/input.h>
	2	#include "tegra30.dtsi"
	3
	4	/*
39ebbf61 MZ	5	* Toradex Colibri T30 Module Device Tree
39ebbf61 MZ	6	* Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
446e9c63 SA	7	*/
	8	/ {
	9	model = "Toradex Colibri T30";
	10	compatible = "toradex,colibri_t30", "nvidia,tegra30";
	11
	12	memory {
	13	reg = <0x80000000 0x40000000>;
	14	};
	15
	16	host1x@50000000 {
	17	hdmi@54280000 {
312d3732 MZ	18	vdd-supply = <&avdd_hdmi_3v3_reg>;
312d3732 MZ	19	pll-supply = <&avdd_hdmi_pll_1v8_reg>;
446e9c63 SA	20
	21	nvidia,hpd-gpio =
	22	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	23	nvidia,ddc-i2c-bus = <&hdmiddc>;
	24	};
	25	};
	26
	27	pinmux@70000868 {
	28	pinctrl-names = "default";
	29	pinctrl-0 = <&state_default>;
	30
	31	state_default: pinmux {
8948e746 MZ	32	/* Analogue Audio (On-module) */
	33	clk1_out_pw4 {
	34	nvidia,pins = "clk1_out_pw4";
	35	nvidia,function = "extperiph1";
	36	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	37	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	38	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	39	};
	40	dap3_fs_pp0 {
	41	nvidia,pins = "dap3_fs_pp0",
	42	"dap3_sclk_pp3",
	43	"dap3_din_pp1",
	44	"dap3_dout_pp2";
	45	nvidia,function = "i2s2";
	46	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	47	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	48	};
	49
446e9c63 SA	50	/* Colibri BL_ON */
	51	pv2 {
	52	nvidia,pins = "pv2";
	53	nvidia,function = "rsvd4";
	54	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	55	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	56	};
	57
	58	/* Colibri Backlight PWM<A> */
	59	sdmmc3_dat3_pb4 {
d5edc4ec	60	nvidia,pins = "sdmmc3_dat3_pb4";
446e9c63 SA	61	nvidia,function = "pwm0";
	62	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	63	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	64	};
	65
	66	/* Colibri CAN_INT */
	67	kb_row8_ps0 {
	68	nvidia,pins = "kb_row8_ps0";
	69	nvidia,function = "kbc";
	70	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	71	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	72	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	73	};
	74
	75	/*
	76	* Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
	77	* todays display need DE, disable LCD_M1
	78	*/
	79	lcd_m1_pw1 {
	80	nvidia,pins = "lcd_m1_pw1";
	81	nvidia,function = "rsvd3";
	82	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	83	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	84	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	85	};
	86
446e9c63 SA	87	/* Colibri MMC */
	88	kb_row10_ps2 {
	89	nvidia,pins = "kb_row10_ps2";
	90	nvidia,function = "sdmmc2";
	91	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	92	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	93	};
	94	kb_row11_ps3 {
d5edc4ec TR	95	nvidia,pins = "kb_row11_ps3",
	96	"kb_row12_ps4",
	97	"kb_row13_ps5",
	98	"kb_row14_ps6",
	99	"kb_row15_ps7";
446e9c63 SA	100	nvidia,function = "sdmmc2";
	101	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	102	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	103	};
	104
	105	/* Colibri SSP */
	106	ulpi_clk_py0 {
d5edc4ec TR	107	nvidia,pins = "ulpi_clk_py0",
	108	"ulpi_dir_py1",
	109	"ulpi_nxt_py2",
	110	"ulpi_stp_py3";
446e9c63 SA	111	nvidia,function = "spi1";
	112	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	113	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	114	};
	115	sdmmc3_dat6_pd3 {
d5edc4ec TR	116	nvidia,pins = "sdmmc3_dat6_pd3",
d5edc4ec TR	117	"sdmmc3_dat7_pd4";
446e9c63 SA	118	nvidia,function = "spdif";
	119	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	120	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	121	};
	122
	123	/* Colibri UART_A */
	124	ulpi_data0 {
d5edc4ec TR	125	nvidia,pins = "ulpi_data0_po1",
	126	"ulpi_data1_po2",
	127	"ulpi_data2_po3",
	128	"ulpi_data3_po4",
	129	"ulpi_data4_po5",
	130	"ulpi_data5_po6",
	131	"ulpi_data6_po7",
	132	"ulpi_data7_po0";
446e9c63 SA	133	nvidia,function = "uarta";
	134	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	135	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	136	};
	137
	138	/* Colibri UART_B */
	139	gmi_a16_pj7 {
d5edc4ec TR	140	nvidia,pins = "gmi_a16_pj7",
	141	"gmi_a17_pb0",
	142	"gmi_a18_pb1",
	143	"gmi_a19_pk7";
446e9c63 SA	144	nvidia,function = "uartd";
	145	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	146	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	147	};
	148
	149	/* Colibri UART_C */
	150	uart2_rxd {
d5edc4ec TR	151	nvidia,pins = "uart2_rxd_pc3",
d5edc4ec TR	152	"uart2_txd_pc2";
446e9c63 SA	153	nvidia,function = "uartb";
	154	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	155	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	156	};
	157
	158	/* eMMC */
	159	sdmmc4_clk_pcc4 {
d5edc4ec TR	160	nvidia,pins = "sdmmc4_clk_pcc4",
d5edc4ec TR	161	"sdmmc4_rst_n_pcc3";
446e9c63 SA	162	nvidia,function = "sdmmc4";
	163	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	164	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	165	};
	166	sdmmc4_dat0_paa0 {
d5edc4ec TR	167	nvidia,pins = "sdmmc4_dat0_paa0",
	168	"sdmmc4_dat1_paa1",
	169	"sdmmc4_dat2_paa2",
	170	"sdmmc4_dat3_paa3",
	171	"sdmmc4_dat4_paa4",
	172	"sdmmc4_dat5_paa5",
	173	"sdmmc4_dat6_paa6",
	174	"sdmmc4_dat7_paa7";
446e9c63 SA	175	nvidia,function = "sdmmc4";
	176	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	177	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	178	};
62bcaba1	179
e48f6c0e MZ	180	/* Power I2C (On-module) */
	181	pwr_i2c_scl_pz6 {
	182	nvidia,pins = "pwr_i2c_scl_pz6",
	183	"pwr_i2c_sda_pz7";
	184	nvidia,function = "i2cpwr";
	185	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	186	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	187	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	188	nvidia,lock = <TEGRA_PIN_DISABLE>;
	189	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	190	};
	191
62bcaba1 MZ	192	/*
	193	* THERMD_ALERT#, unlatched I2C address pin of LM95245
	194	* temperature sensor therefore requires disabling for
	195	* now
	196	*/
	197	lcd_dc1_pd2 {
	198	nvidia,pins = "lcd_dc1_pd2";
	199	nvidia,function = "rsvd3";
	200	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	201	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	202	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	203	};
6456e9c5 MZ	204
	205	/* TOUCH_PEN_INT# */
	206	pv0 {
	207	nvidia,pins = "pv0";
	208	nvidia,function = "rsvd1";
	209	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	210	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	211	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	212	};
446e9c63 SA	213	};
	214	};
	215
	216	hdmiddc: i2c@7000c700 {
	217	clock-frequency = <100000>;
	218	};
	219
	220	/*
	221	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	222	* touch screen controller
	223	*/
	224	i2c@7000d000 {
	225	status = "okay";
	226	clock-frequency = <100000>;
	227
8948e746 MZ	228	/* SGTL5000 audio codec */
	229	sgtl5000: codec@a {
	230	compatible = "fsl,sgtl5000";
	231	reg = <0x0a>;
	232	VDDA-supply = <&sys_3v3_reg>;
	233	VDDIO-supply = <&sys_3v3_reg>;
	234	clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
	235	};
	236
446e9c63 SA	237	pmic: tps65911@2d {
	238	compatible = "ti,tps65911";
	239	reg = <0x2d>;
	240
	241	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	242	#interrupt-cells = <2>;
	243	interrupt-controller;
	244
	245	ti,system-power-controller;
	246
	247	#gpio-cells = <2>;
	248	gpio-controller;
	249
	250	vcc1-supply = <&sys_3v3_reg>;
	251	vcc2-supply = <&sys_3v3_reg>;
	252	vcc3-supply = <&vio_reg>;
	253	vcc4-supply = <&sys_3v3_reg>;
	254	vcc5-supply = <&sys_3v3_reg>;
	255	vcc6-supply = <&vio_reg>;
caa9eac5	256	vcc7-supply = <&charge_pump_5v0_reg>;
446e9c63 SA	257	vccio-supply = <&sys_3v3_reg>;
	258
	259	regulators {
	260	/* SW1: +V1.35_VDDIO_DDR */
	261	vdd1_reg: vdd1 {
	262	regulator-name = "vddio_ddr_1v35";
	263	regulator-min-microvolt = <1350000>;
	264	regulator-max-microvolt = <1350000>;
	265	regulator-always-on;
	266	};
	267
	268	/* SW2: unused */
	269
	270	/* SW CTRL: +V1.0_VDD_CPU */
	271	vddctrl_reg: vddctrl {
	272	regulator-name = "vdd_cpu,vdd_sys";
	273	regulator-min-microvolt = <1150000>;
	274	regulator-max-microvolt = <1150000>;
	275	regulator-always-on;
	276	};
	277
	278	/* SWIO: +V1.8 */
	279	vio_reg: vio {
	280	regulator-name = "vdd_1v8_gen";
	281	regulator-min-microvolt = <1800000>;
	282	regulator-max-microvolt = <1800000>;
	283	regulator-always-on;
	284	};
	285
	286	/* LDO1: unused */
	287
	288	/*
	289	* EN_+V3.3 switching via FET:
	290	* +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
b038e3b9	291	* see also 3v3 fixed supply
446e9c63 SA	292	*/
	293	ldo2_reg: ldo2 {
	294	regulator-name = "en_3v3";
	295	regulator-min-microvolt = <3300000>;
	296	regulator-max-microvolt = <3300000>;
	297	regulator-always-on;
	298	};
	299
	300	/* LDO3: unused */
	301
	302	/* +V1.2_VDD_RTC */
	303	ldo4_reg: ldo4 {
	304	regulator-name = "vdd_rtc";
	305	regulator-min-microvolt = <1200000>;
	306	regulator-max-microvolt = <1200000>;
	307	regulator-always-on;
	308	};
	309
	310	/*
	311	* +V2.8_AVDD_VDAC:
	312	* only required for analog RGB
	313	*/
	314	ldo5_reg: ldo5 {
	315	regulator-name = "avdd_vdac";
	316	regulator-min-microvolt = <2800000>;
	317	regulator-max-microvolt = <2800000>;
	318	regulator-always-on;
	319	};
	320
	321	/*
	322	* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
	323	* but LDO6 can't set voltage in 50mV
	324	* granularity
	325	*/
	326	ldo6_reg: ldo6 {
	327	regulator-name = "avdd_plle";
	328	regulator-min-microvolt = <1100000>;
	329	regulator-max-microvolt = <1100000>;
	330	};
	331
	332	/* +V1.2_AVDD_PLL */
	333	ldo7_reg: ldo7 {
	334	regulator-name = "avdd_pll";
	335	regulator-min-microvolt = <1200000>;
	336	regulator-max-microvolt = <1200000>;
	337	regulator-always-on;
	338	};
	339
	340	/* +V1.0_VDD_DDR_HS */
	341	ldo8_reg: ldo8 {
	342	regulator-name = "vdd_ddr_hs";
	343	regulator-min-microvolt = <1000000>;
	344	regulator-max-microvolt = <1000000>;
	345	regulator-always-on;
	346	};
	347	};
	348	};
	349
737a7c26 MZ	350	/* STMPE811 touch screen controller */
	351	stmpe811@41 {
	352	compatible = "st,stmpe811";
	353	#address-cells = <1>;
	354	#size-cells = <0>;
	355	reg = <0x41>;
	356	interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
	357	interrupt-parent = <&gpio>;
	358	interrupt-controller;
	359	id = <0>;
	360	blocks = <0x5>;
	361	irq-trigger = <0x1>;
	362
	363	stmpe_touchscreen {
	364	compatible = "st,stmpe-ts";
	365	reg = <0>;
	366	/* 3.25 MHz ADC clock speed */
	367	st,adc-freq = <1>;
	368	/* 8 sample average control */
	369	st,ave-ctrl = <3>;
	370	/* 7 length fractional part in z */
	371	st,fraction-z = <7>;
	372	/*
	373	* 50 mA typical 80 mA max touchscreen drivers
	374	* current limit value
	375	*/
	376	st,i-drive = <1>;
	377	/* 12-bit ADC */
	378	st,mod-12b = <1>;
	379	/* internal ADC reference */
	380	st,ref-sel = <0>;
	381	/* ADC converstion time: 80 clocks */
	382	st,sample-time = <4>;
	383	/* 1 ms panel driver settling time */
	384	st,settling = <3>;
	385	/* 5 ms touch detect interrupt delay */
	386	st,touch-det-delay = <5>;
	387	};
	388	};
	389
446e9c63 SA	390	/*
	391	* LM95245 temperature sensor
	392	* Note: OVERT_N directly connected to PMIC PWRDN
	393	*/
	394	temp-sensor@4c {
	395	compatible = "national,lm95245";
	396	reg = <0x4c>;
	397	};
	398
	399	/* SW: +V1.2_VDD_CORE */
	400	tps62362@60 {
	401	compatible = "ti,tps62362";
	402	reg = <0x60>;
	403
	404	regulator-name = "tps62362-vout";
	405	regulator-min-microvolt = <900000>;
	406	regulator-max-microvolt = <1400000>;
	407	regulator-boot-on;
	408	regulator-always-on;
	409	ti,vsel0-state-low;
	410	/* VSEL1: EN_CORE_DVFS_N low for DVFS */
	411	ti,vsel1-state-low;
	412	};
	413	};
	414
	415	pmc@7000e400 {
	416	nvidia,invert-interrupt;
	417	nvidia,suspend-mode = <1>;
	418	nvidia,cpu-pwr-good-time = <5000>;
	419	nvidia,cpu-pwr-off-time = <5000>;
	420	nvidia,core-pwr-good-time = <3845 3845>;
	421	nvidia,core-pwr-off-time = <0>;
	422	nvidia,core-power-req-active-high;
	423	nvidia,sys-clock-req-active-high;
	424	};
	425
8948e746 MZ	426	ahub@70080000 {
	427	i2s@70080500 {
	428	status = "okay";
	429	};
	430	};
	431
3791d1cc MZ	432	/* eMMC */
3791d1cc MZ	433	sdhci@78000600 {
446e9c63 SA	434	status = "okay";
	435	bus-width = <8>;
	436	non-removable;
	437	};
	438
	439	/* EHCI instance 1: USB2_DP/N -> AX88772B */
	440	usb@7d004000 {
	441	status = "okay";
	442	};
	443
	444	usb-phy@7d004000 {
	445	status = "okay";
	446	nvidia,is-wired = <1>;
	447	};
	448
	449	clocks {
	450	compatible = "simple-bus";
	451	#address-cells = <1>;
	452	#size-cells = <0>;
	453
	454	clk32k_in: clk@0 {
	455	compatible = "fixed-clock";
4ec2e601	456	reg = <0>;
446e9c63 SA	457	#clock-cells = <0>;
	458	clock-frequency = <32768>;
	459	};
	460	};
	461
	462	regulators {
	463	compatible = "simple-bus";
	464	#address-cells = <1>;
	465	#size-cells = <0>;
	466
312d3732	467	avdd_hdmi_pll_1v8_reg: regulator@100 {
446e9c63 SA	468	compatible = "regulator-fixed";
446e9c63 SA	469	reg = <100>;
312d3732 MZ	470	regulator-name = "+V1.8_AVDD_HDMI_PLL";
	471	regulator-min-microvolt = <1800000>;
	472	regulator-max-microvolt = <1800000>;
	473	enable-active-high;
	474	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	475	vin-supply = <&vio_reg>;
	476	};
	477
	478	sys_3v3_reg: regulator@101 {
	479	compatible = "regulator-fixed";
	480	reg = <101>;
446e9c63 SA	481	regulator-name = "3v3";
	482	regulator-min-microvolt = <3300000>;
	483	regulator-max-microvolt = <3300000>;
	484	regulator-always-on;
	485	};
caa9eac5	486
312d3732	487	avdd_hdmi_3v3_reg: regulator@102 {
caa9eac5	488	compatible = "regulator-fixed";
312d3732 MZ	489	reg = <102>;
	490	regulator-name = "+V3.3_AVDD_HDMI";
	491	regulator-min-microvolt = <3300000>;
	492	regulator-max-microvolt = <3300000>;
	493	enable-active-high;
	494	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	495	vin-supply = <&sys_3v3_reg>;
	496	};
	497
	498	charge_pump_5v0_reg: regulator@103 {
	499	compatible = "regulator-fixed";
	500	reg = <103>;
caa9eac5 MZ	501	regulator-name = "5v0";
	502	regulator-min-microvolt = <5000000>;
	503	regulator-max-microvolt = <5000000>;
	504	regulator-always-on;
	505	};
446e9c63	506	};
8948e746 MZ	507
	508	sound {
	509	compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
	510	"nvidia,tegra-audio-sgtl5000";
	511	nvidia,model = "Toradex Colibri T30";
	512	nvidia,audio-routing =
	513	"Headphone Jack", "HP_OUT",
	514	"LINE_IN", "Line In Jack",
	515	"MIC_IN", "Mic Jack";
	516	nvidia,i2s-controller = <&tegra_i2s2>;
	517	nvidia,audio-codec = <&sgtl5000>;
	518	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	519	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	520	<&tegra_car TEGRA30_CLK_EXTERN1>;
	521	clock-names = "pll_a", "pll_a_out0", "mclk";
	522	};
446e9c63	523	};