]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/tegra30.dtsi
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
05849c93 2#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 4#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 6#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 7
1bd0bd49 8#include "skeleton.dtsi"
c3e00a0e
PDS		 9
10/ {
11 compatible = "nvidia,tegra30";
870c81a4 12 interrupt-parent = <&lic>;
c3e00a0e 13
508d690e 14 pcie@3000 {
e07e3dbd
TR		 15 compatible = "nvidia,tegra30-pcie";
16 device_type = "pci";
17 reg = <0x00003000 0x00000800 /* PADS registers */
18 0x00003800 0x00000200 /* AFI registers */
19 0x10000000 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
22 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
97070bd4
LS		 25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
e07e3dbd
TR		 29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
35 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
36 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 37 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
38 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 39
40 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
41 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 42 <&tegra_car TEGRA30_CLK_PLL_E>,
43 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 44 clock-names = "pex", "afi", "pll_e", "cml";
3393d422 45 resets = <&tegra_car 70>,
d8b316b2
MZ		 46 <&tegra_car 72>,
47 <&tegra_car 74>;
3393d422 48 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
508d690e 55 bus-range = <0x00 0xff>;
e07e3dbd
TR		 56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
508d690e 69 bus-range = <0x00 0xff>;
e07e3dbd
TR		 70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
508d690e 83 bus-range = <0x00 0xff>;
e07e3dbd
TR		 84 status = "disabled";
85
86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges;
89
90 nvidia,num-lanes = <2>;
91 };
92 };
93
ea857036
DO		 94 iram@40000000 {
95 compatible = "mmio-sram";
96 reg = <0x40000000 0x40000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x40000000 0x40000>;
55f939c2
DO		 100
101 vde_pool: vde@400 {
102 reg = <0x400 0x3fc00>;
103 pool;
104 };
ea857036
DO		 105 };
106
58ecb23f 107 host1x@50000000 {
ed39097c
TR		 108 compatible = "nvidia,tegra30-host1x", "simple-bus";
109 reg = <0x50000000 0x00024000>;
6cecf916
SW		 110 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
111 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 112 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 113 resets = <&tegra_car 28>;
114 reset-names = "host1x";
1dac1827 115 iommus = <&mc TEGRA_SWGROUP_HC>;
ed39097c
TR		 116
117 #address-cells = <1>;
118 #size-cells = <1>;
119
120 ranges = <0x54000000 0x54000000 0x04000000>;
121
58ecb23f 122 mpe@54040000 {
ed39097c
TR		 123 compatible = "nvidia,tegra30-mpe";
124 reg = <0x54040000 0x00040000>;
6cecf916 125 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 126 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 127 resets = <&tegra_car 60>;
128 reset-names = "mpe";
1dac1827
DO		 129
130 iommus = <&mc TEGRA_SWGROUP_MPE>;
ed39097c
TR		 131 };
132
58ecb23f 133 vi@54080000 {
ed39097c
TR		 134 compatible = "nvidia,tegra30-vi";
135 reg = <0x54080000 0x00040000>;
6cecf916 136 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 137 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 138 resets = <&tegra_car 20>;
139 reset-names = "vi";
1dac1827
DO		 140
141 iommus = <&mc TEGRA_SWGROUP_VI>;
ed39097c
TR		 142 };
143
58ecb23f 144 epp@540c0000 {
ed39097c
TR		 145 compatible = "nvidia,tegra30-epp";
146 reg = <0x540c0000 0x00040000>;
6cecf916 147 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 148 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 149 resets = <&tegra_car 19>;
150 reset-names = "epp";
1dac1827
DO		 151
152 iommus = <&mc TEGRA_SWGROUP_EPP>;
ed39097c
TR		 153 };
154
58ecb23f 155 isp@54100000 {
ed39097c
TR		 156 compatible = "nvidia,tegra30-isp";
157 reg = <0x54100000 0x00040000>;
6cecf916 158 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 159 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 160 resets = <&tegra_car 23>;
161 reset-names = "isp";
1dac1827
DO		 162
163 iommus = <&mc TEGRA_SWGROUP_ISP>;
ed39097c
TR		 164 };
165
58ecb23f 166 gr2d@54140000 {
ed39097c
TR		 167 compatible = "nvidia,tegra30-gr2d";
168 reg = <0x54140000 0x00040000>;
6cecf916 169 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 170 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 171 resets = <&tegra_car 21>;
172 reset-names = "2d";
1dac1827
DO		 173
174 iommus = <&mc TEGRA_SWGROUP_G2>;
ed39097c
TR		 175 };
176
58ecb23f 177 gr3d@54180000 {
ed39097c
TR		 178 compatible = "nvidia,tegra30-gr3d";
179 reg = <0x54180000 0x00040000>;
c71d3909
TR		 180 clocks = <&tegra_car TEGRA30_CLK_GR3D
181 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 182 clock-names = "3d", "3d2";
3393d422 183 resets = <&tegra_car 24>,
d8b316b2 184 <&tegra_car 98>;
3393d422 185 reset-names = "3d", "3d2";
1dac1827
DO		 186
187 iommus = <&mc TEGRA_SWGROUP_NV>,
188 <&mc TEGRA_SWGROUP_NV2>;
ed39097c
TR		 189 };
190
191 dc@54200000 {
05465f4e 192 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 193 reg = <0x54200000 0x00040000>;
6cecf916 194 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 195 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
196 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 197 clock-names = "dc", "parent";
3393d422
SW		 198 resets = <&tegra_car 27>;
199 reset-names = "dc";
ed39097c 200
6d9adf6f
TR		 201 iommus = <&mc TEGRA_SWGROUP_DC>;
202
688b56b4
TR		 203 nvidia,head = <0>;
204
ed39097c
TR		 205 rgb {
206 status = "disabled";
207 };
208 };
209
210 dc@54240000 {
211 compatible = "nvidia,tegra30-dc";
212 reg = <0x54240000 0x00040000>;
6cecf916 213 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 214 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
215 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 216 clock-names = "dc", "parent";
3393d422
SW		 217 resets = <&tegra_car 26>;
218 reset-names = "dc";
ed39097c 219
6d9adf6f
TR		 220 iommus = <&mc TEGRA_SWGROUP_DCB>;
221
688b56b4
TR		 222 nvidia,head = <1>;
223
ed39097c
TR		 224 rgb {
225 status = "disabled";
226 };
227 };
228
58ecb23f 229 hdmi@54280000 {
ed39097c
TR		 230 compatible = "nvidia,tegra30-hdmi";
231 reg = <0x54280000 0x00040000>;
6cecf916 232 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 233 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
234 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 235 clock-names = "hdmi", "parent";
3393d422
SW		 236 resets = <&tegra_car 51>;
237 reset-names = "hdmi";
ed39097c
TR		 238 status = "disabled";
239 };
240
58ecb23f 241 tvo@542c0000 {
ed39097c
TR		 242 compatible = "nvidia,tegra30-tvo";
243 reg = <0x542c0000 0x00040000>;
6cecf916 244 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 245 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 246 status = "disabled";
247 };
248
58ecb23f 249 dsi@54300000 {
ed39097c
TR		 250 compatible = "nvidia,tegra30-dsi";
251 reg = <0x54300000 0x00040000>;
05849c93 252 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 253 resets = <&tegra_car 48>;
254 reset-names = "dsi";
ed39097c
TR		 255 status = "disabled";
256 };
257 };
258
2cda1880 259 timer@50040600 {
73368ba0
SW		 260 compatible = "arm,cortex-a9-twd-timer";
261 reg = <0x50040600 0x20>;
870c81a4 262 interrupt-parent = <&intc>;
6cecf916 263 interrupts = <GIC_PPI 13
e7d9b270 264 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
05849c93 265 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 266 };
267
58ecb23f 268 intc: interrupt-controller@50041000 {
c3e00a0e 269 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 270 reg = <0x50041000 0x1000
271 0x50040100 0x0100>;
2eaab06e
SW		 272 interrupt-controller;
273 #interrupt-cells = <3>;
870c81a4 274 interrupt-parent = <&intc>;
c3e00a0e
PDS		 275 };
276
58ecb23f 277 cache-controller@50043000 {
bb2c1de9
SW		 278 compatible = "arm,pl310-cache";
279 reg = <0x50043000 0x1000>;
280 arm,data-latency = <6 6 2>;
281 arm,tag-latency = <5 5 2>;
282 cache-unified;
283 cache-level = <2>;
284 };
285
870c81a4
MZ		 286 lic: interrupt-controller@60004000 {
287 compatible = "nvidia,tegra30-ictlr";
288 reg = <0x60004000 0x100>,
289 <0x60004100 0x50>,
290 <0x60004200 0x50>,
291 <0x60004300 0x50>,
292 <0x60004400 0x50>;
293 interrupt-controller;
294 #interrupt-cells = <3>;
295 interrupt-parent = <&intc>;
296 };
297
2f2b7fb2
SW		 298 timer@60005000 {
299 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
300 reg = <0x60005000 0x400>;
6cecf916
SW		 301 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 307 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 308 };
309
58ecb23f 310 tegra_car: clock@60006000 {
95985667
PG		 311 compatible = "nvidia,tegra30-car";
312 reg = <0x60006000 0x1000>;
313 #clock-cells = <1>;
3393d422 314 #reset-cells = <1>;
95985667
PG		 315 };
316
b1023134
TR		 317 flow-controller@60007000 {
318 compatible = "nvidia,tegra30-flowctrl";
319 reg = <0x60007000 0x1000>;
320 };
321
58ecb23f 322 apbdma: dma@6000a000 {
8051b75a
SW		 323 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
324 reg = <0x6000a000 0x1400>;
6cecf916
SW		 325 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 357 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 358 resets = <&tegra_car 34>;
359 reset-names = "dma";
034d023f 360 #dma-cells = <1>;
8051b75a
SW		 361 };
362
0d5ccb38 363 ahb: ahb@6000c000 {
c04abb3a 364 compatible = "nvidia,tegra30-ahb";
0d5ccb38 365 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 366 };
367
58ecb23f 368 gpio: gpio@6000d000 {
35f210ec 369 compatible = "nvidia,tegra30-gpio";
95decf84 370 reg = <0x6000d000 0x1000>;
6cecf916
SW		 371 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 379 #gpio-cells = <2>;
380 gpio-controller;
6f74dc9b
SW		 381 #interrupt-cells = <2>;
382 interrupt-controller;
4f1d8414 383 /*
17cdddf0 384 gpio-ranges = <&pinmux 0 0 248>;
4f1d8414 385 */
c3e00a0e
PDS		 386 };
387
55f939c2
DO		 388 vde@6001a000 {
389 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
390 reg = <0x6001a000 0x1000 /* Syntax Engine */
391 0x6001b000 0x1000 /* Video Bitstream Engine */
392 0x6001c000 0x100 /* Macroblock Engine */
393 0x6001c200 0x100 /* Post-processing Engine */
394 0x6001c400 0x100 /* Motion Compensation Engine */
395 0x6001c600 0x100 /* Transform Engine */
396 0x6001c800 0x100 /* Pixel prediction block */
397 0x6001ca00 0x100 /* Video DMA */
398 0x6001d800 0x400>; /* Video frame controls */
399 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
400 "tfe", "ppb", "vdma", "frameid";
401 iram = <&vde_pool>; /* IRAM region */
402 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
403 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
404 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
405 interrupt-names = "sync-token", "bsev", "sxe";
406 clocks = <&tegra_car TEGRA30_CLK_VDE>;
407 resets = <&tegra_car 61>;
408 };
409
155dfc7b
PDS		 410 apbmisc@70000800 {
411 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
412 reg = <0x70000800 0x64 /* Chip revision */
413 0x70000008 0x04>; /* Strapping options */
414 };
415
58ecb23f 416 pinmux: pinmux@70000868 {
c04abb3a 417 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 418 reg = <0x70000868 0xd4 /* Pad control registers */
419 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 420 };
421
b6551bb9
LD		 422 /*
423 * There are two serial driver i.e. 8250 based simple serial
424 * driver and APB DMA based serial driver for higher baudrate
425 * and performace. To enable the 8250 based driver, the compatible
426 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
e1098248 427 * the APB DMA based serial driver, the compatible is
b6551bb9
LD		 428 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
429 */
430 uarta: serial@70006000 {
c3e00a0e
PDS		 431 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
432 reg = <0x70006000 0x40>;
433 reg-shift = <2>;
6cecf916 434 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 435 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 436 resets = <&tegra_car 6>;
437 reset-names = "serial";
034d023f
SW		 438 dmas = <&apbdma 8>, <&apbdma 8>;
439 dma-names = "rx", "tx";
223ef78d 440 status = "disabled";
c3e00a0e
PDS		 441 };
442
b6551bb9 443 uartb: serial@70006040 {
c3e00a0e
PDS		 444 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
445 reg = <0x70006040 0x40>;
446 reg-shift = <2>;
6cecf916 447 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 448 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 449 resets = <&tegra_car 7>;
450 reset-names = "serial";
034d023f
SW		 451 dmas = <&apbdma 9>, <&apbdma 9>;
452 dma-names = "rx", "tx";
223ef78d 453 status = "disabled";
c3e00a0e
PDS		 454 };
455
b6551bb9 456 uartc: serial@70006200 {
c3e00a0e
PDS		 457 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
458 reg = <0x70006200 0x100>;
459 reg-shift = <2>;
6cecf916 460 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 461 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 462 resets = <&tegra_car 55>;
463 reset-names = "serial";
034d023f
SW		 464 dmas = <&apbdma 10>, <&apbdma 10>;
465 dma-names = "rx", "tx";
223ef78d 466 status = "disabled";
c3e00a0e
PDS		 467 };
468
b6551bb9 469 uartd: serial@70006300 {
c3e00a0e
PDS		 470 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
471 reg = <0x70006300 0x100>;
472 reg-shift = <2>;
6cecf916 473 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 474 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 475 resets = <&tegra_car 65>;
476 reset-names = "serial";
034d023f
SW		 477 dmas = <&apbdma 19>, <&apbdma 19>;
478 dma-names = "rx", "tx";
223ef78d 479 status = "disabled";
c3e00a0e
PDS		 480 };
481
b6551bb9 482 uarte: serial@70006400 {
c3e00a0e
PDS		 483 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
484 reg = <0x70006400 0x100>;
485 reg-shift = <2>;
6cecf916 486 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 487 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 488 resets = <&tegra_car 66>;
489 reset-names = "serial";
034d023f
SW		 490 dmas = <&apbdma 20>, <&apbdma 20>;
491 dma-names = "rx", "tx";
223ef78d 492 status = "disabled";
c3e00a0e
PDS		 493 };
494
5e35c1f0
MK		 495 gmi@70009000 {
496 compatible = "nvidia,tegra30-gmi";
497 reg = <0x70009000 0x1000>;
498 #address-cells = <2>;
499 #size-cells = <1>;
500 ranges = <0 0 0x48000000 0x7ffffff>;
501 clocks = <&tegra_car TEGRA30_CLK_NOR>;
502 clock-names = "gmi";
503 resets = <&tegra_car 42>;
504 reset-names = "gmi";
505 status = "disabled";
506 };
507
58ecb23f 508 pwm: pwm@7000a000 {
140fd977
TR		 509 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
510 reg = <0x7000a000 0x100>;
511 #pwm-cells = <2>;
05849c93 512 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 513 resets = <&tegra_car 17>;
514 reset-names = "pwm";
b69cd984 515 status = "disabled";
140fd977
TR		 516 };
517
58ecb23f 518 rtc@7000e000 {
380e04ac
SW		 519 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
520 reg = <0x7000e000 0x100>;
6cecf916 521 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 522 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 523 };
524
c04abb3a 525 i2c@7000c000 {
d8b316b2 526 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a 527 reg = <0x7000c000 0x100>;
6cecf916 528 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 529 #address-cells = <1>;
530 #size-cells = <0>;
05849c93
HD		 531 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
532 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 533 clock-names = "div-clk", "fast-clk";
3393d422
SW		 534 resets = <&tegra_car 12>;
535 reset-names = "i2c";
034d023f
SW		 536 dmas = <&apbdma 21>, <&apbdma 21>;
537 dma-names = "rx", "tx";
223ef78d 538 status = "disabled";
c3e00a0e
PDS		 539 };
540
c04abb3a 541 i2c@7000c400 {
c04abb3a
SW		 542 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
543 reg = <0x7000c400 0x100>;
6cecf916 544 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 545 #address-cells = <1>;
546 #size-cells = <0>;
05849c93
HD		 547 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
548 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 549 clock-names = "div-clk", "fast-clk";
3393d422
SW		 550 resets = <&tegra_car 54>;
551 reset-names = "i2c";
034d023f
SW		 552 dmas = <&apbdma 22>, <&apbdma 22>;
553 dma-names = "rx", "tx";
223ef78d 554 status = "disabled";
c3e00a0e
PDS		 555 };
556
c04abb3a 557 i2c@7000c500 {
c04abb3a
SW		 558 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
559 reg = <0x7000c500 0x100>;
6cecf916 560 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 561 #address-cells = <1>;
562 #size-cells = <0>;
05849c93
HD		 563 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
564 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 565 clock-names = "div-clk", "fast-clk";
3393d422
SW		 566 resets = <&tegra_car 67>;
567 reset-names = "i2c";
034d023f
SW		 568 dmas = <&apbdma 23>, <&apbdma 23>;
569 dma-names = "rx", "tx";
223ef78d 570 status = "disabled";
c3e00a0e
PDS		 571 };
572
c04abb3a 573 i2c@7000c700 {
c04abb3a
SW		 574 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
575 reg = <0x7000c700 0x100>;
6cecf916 576 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 577 #address-cells = <1>;
578 #size-cells = <0>;
05849c93
HD		 579 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
580 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 581 resets = <&tegra_car 103>;
582 reset-names = "i2c";
1cbc733d 583 clock-names = "div-clk", "fast-clk";
034d023f
SW		 584 dmas = <&apbdma 26>, <&apbdma 26>;
585 dma-names = "rx", "tx";
223ef78d 586 status = "disabled";
c3e00a0e
PDS		 587 };
588
c04abb3a 589 i2c@7000d000 {
c04abb3a
SW		 590 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
591 reg = <0x7000d000 0x100>;
6cecf916 592 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 593 #address-cells = <1>;
594 #size-cells = <0>;
05849c93
HD		 595 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
596 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 597 clock-names = "div-clk", "fast-clk";
3393d422
SW		 598 resets = <&tegra_car 47>;
599 reset-names = "i2c";
034d023f
SW		 600 dmas = <&apbdma 24>, <&apbdma 24>;
601 dma-names = "rx", "tx";
223ef78d 602 status = "disabled";
c04abb3a
SW		 603 };
604
a86b0db3
LD		 605 spi@7000d400 {
606 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
607 reg = <0x7000d400 0x200>;
6cecf916 608 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 609 #address-cells = <1>;
610 #size-cells = <0>;
05849c93 611 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 612 resets = <&tegra_car 41>;
613 reset-names = "spi";
034d023f
SW		 614 dmas = <&apbdma 15>, <&apbdma 15>;
615 dma-names = "rx", "tx";
a86b0db3
LD		 616 status = "disabled";
617 };
618
619 spi@7000d600 {
620 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
621 reg = <0x7000d600 0x200>;
6cecf916 622 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 623 #address-cells = <1>;
624 #size-cells = <0>;
05849c93 625 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 626 resets = <&tegra_car 44>;
627 reset-names = "spi";
034d023f
SW		 628 dmas = <&apbdma 16>, <&apbdma 16>;
629 dma-names = "rx", "tx";
a86b0db3
LD		 630 status = "disabled";
631 };
632
633 spi@7000d800 {
634 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 635 reg = <0x7000d800 0x200>;
6cecf916 636 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 637 #address-cells = <1>;
638 #size-cells = <0>;
05849c93 639 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 640 resets = <&tegra_car 46>;
641 reset-names = "spi";
034d023f
SW		 642 dmas = <&apbdma 17>, <&apbdma 17>;
643 dma-names = "rx", "tx";
a86b0db3
LD		 644 status = "disabled";
645 };
646
647 spi@7000da00 {
648 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
649 reg = <0x7000da00 0x200>;
6cecf916 650 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 651 #address-cells = <1>;
652 #size-cells = <0>;
05849c93 653 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 654 resets = <&tegra_car 68>;
655 reset-names = "spi";
034d023f
SW		 656 dmas = <&apbdma 18>, <&apbdma 18>;
657 dma-names = "rx", "tx";
a86b0db3
LD		 658 status = "disabled";
659 };
660
661 spi@7000dc00 {
662 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
663 reg = <0x7000dc00 0x200>;
6cecf916 664 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 665 #address-cells = <1>;
666 #size-cells = <0>;
05849c93 667 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 668 resets = <&tegra_car 104>;
669 reset-names = "spi";
034d023f
SW		 670 dmas = <&apbdma 27>, <&apbdma 27>;
671 dma-names = "rx", "tx";
a86b0db3
LD		 672 status = "disabled";
673 };
674
675 spi@7000de00 {
676 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
677 reg = <0x7000de00 0x200>;
6cecf916 678 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 679 #address-cells = <1>;
680 #size-cells = <0>;
05849c93 681 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 682 resets = <&tegra_car 106>;
683 reset-names = "spi";
034d023f
SW		 684 dmas = <&apbdma 28>, <&apbdma 28>;
685 dma-names = "rx", "tx";
a86b0db3
LD		 686 status = "disabled";
687 };
688
58ecb23f 689 kbc@7000e200 {
699ed4b9
LD		 690 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
691 reg = <0x7000e200 0x100>;
6cecf916 692 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 693 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 694 resets = <&tegra_car 36>;
695 reset-names = "kbc";
699ed4b9
LD		 696 status = "disabled";
697 };
698
58ecb23f 699 pmc@7000e400 {
2b84e53b 700 compatible = "nvidia,tegra30-pmc";
c04abb3a 701 reg = <0x7000e400 0x400>;
05849c93 702 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 703 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 704 };
705
a9fe468f 706 mc: memory-controller@7000f000 {
c04abb3a 707 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 708 reg = <0x7000f000 0x400>;
709 clocks = <&tegra_car TEGRA30_CLK_MC>;
710 clock-names = "mc";
711
6cecf916 712 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 713
a9fe468f 714 #iommu-cells = <1>;
c3e00a0e 715 };
9ee6a5c4 716
155dfc7b
PDS		 717 fuse@7000f800 {
718 compatible = "nvidia,tegra30-efuse";
719 reg = <0x7000f800 0x400>;
720 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
721 clock-names = "fuse";
722 resets = <&tegra_car 39>;
723 reset-names = "fuse";
724 };
725
cbee2613
MZ		 726 hda@70030000 {
727 compatible = "nvidia,tegra30-hda";
728 reg = <0x70030000 0x10000>;
729 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&tegra_car TEGRA30_CLK_HDA>,
d8b316b2 731 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
cbee2613
MZ		 732 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
733 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
734 resets = <&tegra_car 125>, /* hda */
735 <&tegra_car 128>, /* hda2hdmi */
736 <&tegra_car 111>; /* hda2codec_2x */
737 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
738 status = "disabled";
739 };
740
58ecb23f 741 ahub@70080000 {
9ee6a5c4 742 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 743 reg = <0x70080000 0x200
744 0x70080200 0x100>;
6cecf916 745 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 746 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 747 <&tegra_car TEGRA30_CLK_APBIF>;
748 clock-names = "d_audio", "apbif";
3393d422
SW		 749 resets = <&tegra_car 106>, /* d_audio */
750 <&tegra_car 107>, /* apbif */
751 <&tegra_car 30>, /* i2s0 */
752 <&tegra_car 11>, /* i2s1 */
753 <&tegra_car 18>, /* i2s2 */
754 <&tegra_car 101>, /* i2s3 */
755 <&tegra_car 102>, /* i2s4 */
756 <&tegra_car 108>, /* dam0 */
757 <&tegra_car 109>, /* dam1 */
758 <&tegra_car 110>, /* dam2 */
759 <&tegra_car 10>; /* spdif */
760 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
761 "i2s3", "i2s4", "dam0", "dam1", "dam2",
762 "spdif";
034d023f
SW		 763 dmas = <&apbdma 1>, <&apbdma 1>,
764 <&apbdma 2>, <&apbdma 2>,
765 <&apbdma 3>, <&apbdma 3>,
766 <&apbdma 4>, <&apbdma 4>;
767 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
768 "rx3", "tx3";
9ee6a5c4
SW		 769 ranges;
770 #address-cells = <1>;
771 #size-cells = <1>;
772
773 tegra_i2s0: i2s@70080300 {
774 compatible = "nvidia,tegra30-i2s";
775 reg = <0x70080300 0x100>;
776 nvidia,ahub-cif-ids = <4 4>;
05849c93 777 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 778 resets = <&tegra_car 30>;
779 reset-names = "i2s";
223ef78d 780 status = "disabled";
9ee6a5c4
SW		 781 };
782
783 tegra_i2s1: i2s@70080400 {
784 compatible = "nvidia,tegra30-i2s";
785 reg = <0x70080400 0x100>;
786 nvidia,ahub-cif-ids = <5 5>;
05849c93 787 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 788 resets = <&tegra_car 11>;
789 reset-names = "i2s";
223ef78d 790 status = "disabled";
9ee6a5c4
SW		 791 };
792
793 tegra_i2s2: i2s@70080500 {
794 compatible = "nvidia,tegra30-i2s";
795 reg = <0x70080500 0x100>;
796 nvidia,ahub-cif-ids = <6 6>;
05849c93 797 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 798 resets = <&tegra_car 18>;
799 reset-names = "i2s";
223ef78d 800 status = "disabled";
9ee6a5c4
SW		 801 };
802
803 tegra_i2s3: i2s@70080600 {
804 compatible = "nvidia,tegra30-i2s";
805 reg = <0x70080600 0x100>;
806 nvidia,ahub-cif-ids = <7 7>;
05849c93 807 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 808 resets = <&tegra_car 101>;
809 reset-names = "i2s";
223ef78d 810 status = "disabled";
9ee6a5c4
SW		 811 };
812
813 tegra_i2s4: i2s@70080700 {
814 compatible = "nvidia,tegra30-i2s";
815 reg = <0x70080700 0x100>;
816 nvidia,ahub-cif-ids = <8 8>;
05849c93 817 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 818 resets = <&tegra_car 102>;
819 reset-names = "i2s";
223ef78d 820 status = "disabled";
9ee6a5c4
SW		 821 };
822 };
7868a9bc 823
c04abb3a
SW		 824 sdhci@78000000 {
825 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
826 reg = <0x78000000 0x200>;
6cecf916 827 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 828 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 829 resets = <&tegra_car 14>;
830 reset-names = "sdhci";
223ef78d 831 status = "disabled";
7868a9bc 832 };
ecf43742 833
c04abb3a
SW		 834 sdhci@78000200 {
835 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
836 reg = <0x78000200 0x200>;
6cecf916 837 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 838 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 839 resets = <&tegra_car 9>;
840 reset-names = "sdhci";
223ef78d 841 status = "disabled";
ecf43742 842 };
54174a33 843
c04abb3a
SW		 844 sdhci@78000400 {
845 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
846 reg = <0x78000400 0x200>;
6cecf916 847 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 848 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 849 resets = <&tegra_car 69>;
850 reset-names = "sdhci";
223ef78d 851 status = "disabled";
c04abb3a
SW		 852 };
853
854 sdhci@78000600 {
855 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
856 reg = <0x78000600 0x200>;
6cecf916 857 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 858 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 859 resets = <&tegra_car 15>;
860 reset-names = "sdhci";
223ef78d 861 status = "disabled";
c04abb3a
SW		 862 };
863
cc34c9f7
TT		 864 usb@7d000000 {
865 compatible = "nvidia,tegra30-ehci", "usb-ehci";
866 reg = <0x7d000000 0x4000>;
867 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
868 phy_type = "utmi";
869 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 870 resets = <&tegra_car 22>;
871 reset-names = "usb";
cc34c9f7
TT		 872 nvidia,needs-double-reset;
873 nvidia,phy = <&phy1>;
874 status = "disabled";
875 };
876
877 phy1: usb-phy@7d000000 {
878 compatible = "nvidia,tegra30-usb-phy";
879 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
880 phy_type = "utmi";
881 clocks = <&tegra_car TEGRA30_CLK_USBD>,
882 <&tegra_car TEGRA30_CLK_PLL_U>,
883 <&tegra_car TEGRA30_CLK_USBD>;
884 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 885 resets = <&tegra_car 22>, <&tegra_car 22>;
886 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 887 nvidia,hssync-start-delay = <9>;
888 nvidia,idle-wait-delay = <17>;
889 nvidia,elastic-limit = <16>;
890 nvidia,term-range-adj = <6>;
891 nvidia,xcvr-setup = <51>;
892 nvidia.xcvr-setup-use-fuses;
893 nvidia,xcvr-lsfslew = <1>;
894 nvidia,xcvr-lsrslew = <1>;
895 nvidia,xcvr-hsslew = <32>;
896 nvidia,hssquelch-level = <2>;
897 nvidia,hsdiscon-level = <5>;
308efde2 898 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 899 status = "disabled";
900 };
901
902 usb@7d004000 {
903 compatible = "nvidia,tegra30-ehci", "usb-ehci";
904 reg = <0x7d004000 0x4000>;
905 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 906 phy_type = "utmi";
cc34c9f7 907 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 908 resets = <&tegra_car 58>;
909 reset-names = "usb";
cc34c9f7
TT		 910 nvidia,phy = <&phy2>;
911 status = "disabled";
912 };
913
914 phy2: usb-phy@7d004000 {
915 compatible = "nvidia,tegra30-usb-phy";
fd6441ec
EB		 916 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
917 phy_type = "utmi";
cc34c9f7
TT		 918 clocks = <&tegra_car TEGRA30_CLK_USB2>,
919 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 920 <&tegra_car TEGRA30_CLK_USBD>;
921 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 922 resets = <&tegra_car 58>, <&tegra_car 22>;
923 reset-names = "usb", "utmi-pads";
fd6441ec
EB		 924 nvidia,hssync-start-delay = <9>;
925 nvidia,idle-wait-delay = <17>;
926 nvidia,elastic-limit = <16>;
927 nvidia,term-range-adj = <6>;
928 nvidia,xcvr-setup = <51>;
929 nvidia.xcvr-setup-use-fuses;
930 nvidia,xcvr-lsfslew = <2>;
931 nvidia,xcvr-lsrslew = <2>;
932 nvidia,xcvr-hsslew = <32>;
933 nvidia,hssquelch-level = <2>;
934 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 935 status = "disabled";
936 };
937
938 usb@7d008000 {
939 compatible = "nvidia,tegra30-ehci", "usb-ehci";
940 reg = <0x7d008000 0x4000>;
941 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
942 phy_type = "utmi";
943 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 944 resets = <&tegra_car 59>;
945 reset-names = "usb";
cc34c9f7
TT		 946 nvidia,phy = <&phy3>;
947 status = "disabled";
948 };
949
950 phy3: usb-phy@7d008000 {
951 compatible = "nvidia,tegra30-usb-phy";
952 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
953 phy_type = "utmi";
954 clocks = <&tegra_car TEGRA30_CLK_USB3>,
955 <&tegra_car TEGRA30_CLK_PLL_U>,
956 <&tegra_car TEGRA30_CLK_USBD>;
957 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 958 resets = <&tegra_car 59>, <&tegra_car 22>;
959 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 960 nvidia,hssync-start-delay = <0>;
961 nvidia,idle-wait-delay = <17>;
962 nvidia,elastic-limit = <16>;
963 nvidia,term-range-adj = <6>;
964 nvidia,xcvr-setup = <51>;
965 nvidia.xcvr-setup-use-fuses;
966 nvidia,xcvr-lsfslew = <2>;
967 nvidia,xcvr-lsrslew = <2>;
968 nvidia,xcvr-hsslew = <32>;
969 nvidia,hssquelch-level = <2>;
970 nvidia,hsdiscon-level = <5>;
971 status = "disabled";
972 };
973
7d19a34a
HD		 974 cpus {
975 #address-cells = <1>;
976 #size-cells = <0>;
977
978 cpu@0 {
979 device_type = "cpu";
980 compatible = "arm,cortex-a9";
981 reg = <0>;
982 };
983
984 cpu@1 {
985 device_type = "cpu";
986 compatible = "arm,cortex-a9";
987 reg = <1>;
988 };
989
990 cpu@2 {
991 device_type = "cpu";
992 compatible = "arm,cortex-a9";
993 reg = <2>;
994 };
995
996 cpu@3 {
997 device_type = "cpu";
998 compatible = "arm,cortex-a9";
999 reg = <3>;
1000 };
1001 };
1002
c04abb3a
SW		 1003 pmu {
1004 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 1005 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 1009 };
c3e00a0e 1010};
Ubuntu Eoan Linux kernel mirror