]>
Commit | Line | Data |
---|---|---|
05849c93 | 1 | #include <dt-bindings/clock/tegra30-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
6d9adf6f | 3 | #include <dt-bindings/memory/tegra30-mc.h> |
a47c662a | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 6 | |
1bd0bd49 | 7 | #include "skeleton.dtsi" |
c3e00a0e PDS |
8 | |
9 | / { | |
10 | compatible = "nvidia,tegra30"; | |
870c81a4 | 11 | interrupt-parent = <&lic>; |
c3e00a0e | 12 | |
58ecb23f | 13 | pcie-controller@00003000 { |
e07e3dbd TR |
14 | compatible = "nvidia,tegra30-pcie"; |
15 | device_type = "pci"; | |
16 | reg = <0x00003000 0x00000800 /* PADS registers */ | |
17 | 0x00003800 0x00000200 /* AFI registers */ | |
18 | 0x10000000 0x10000000>; /* configuration space */ | |
19 | reg-names = "pads", "afi", "cs"; | |
20 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
21 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
22 | interrupt-names = "intr", "msi"; | |
23 | ||
97070bd4 LS |
24 | #interrupt-cells = <1>; |
25 | interrupt-map-mask = <0 0 0 0>; | |
26 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
27 | ||
e07e3dbd TR |
28 | bus-range = <0x00 0xff>; |
29 | #address-cells = <3>; | |
30 | #size-cells = <2>; | |
31 | ||
32 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ | |
33 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ | |
34 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ | |
35 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
36 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
37 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ | |
e07e3dbd TR |
38 | |
39 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, | |
40 | <&tegra_car TEGRA30_CLK_AFI>, | |
e07e3dbd TR |
41 | <&tegra_car TEGRA30_CLK_PLL_E>, |
42 | <&tegra_car TEGRA30_CLK_CML0>; | |
2bd541ff | 43 | clock-names = "pex", "afi", "pll_e", "cml"; |
3393d422 | 44 | resets = <&tegra_car 70>, |
d8b316b2 MZ |
45 | <&tegra_car 72>, |
46 | <&tegra_car 74>; | |
3393d422 | 47 | reset-names = "pex", "afi", "pcie_x"; |
e07e3dbd TR |
48 | status = "disabled"; |
49 | ||
50 | pci@1,0 { | |
51 | device_type = "pci"; | |
52 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; | |
53 | reg = <0x000800 0 0 0 0>; | |
54 | status = "disabled"; | |
55 | ||
56 | #address-cells = <3>; | |
57 | #size-cells = <2>; | |
58 | ranges; | |
59 | ||
60 | nvidia,num-lanes = <2>; | |
61 | }; | |
62 | ||
63 | pci@2,0 { | |
64 | device_type = "pci"; | |
65 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; | |
66 | reg = <0x001000 0 0 0 0>; | |
67 | status = "disabled"; | |
68 | ||
69 | #address-cells = <3>; | |
70 | #size-cells = <2>; | |
71 | ranges; | |
72 | ||
73 | nvidia,num-lanes = <2>; | |
74 | }; | |
75 | ||
76 | pci@3,0 { | |
77 | device_type = "pci"; | |
78 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; | |
79 | reg = <0x001800 0 0 0 0>; | |
80 | status = "disabled"; | |
81 | ||
82 | #address-cells = <3>; | |
83 | #size-cells = <2>; | |
84 | ranges; | |
85 | ||
86 | nvidia,num-lanes = <2>; | |
87 | }; | |
88 | }; | |
89 | ||
58ecb23f | 90 | host1x@50000000 { |
ed39097c TR |
91 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
92 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
93 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
94 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
05849c93 | 95 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
3393d422 SW |
96 | resets = <&tegra_car 28>; |
97 | reset-names = "host1x"; | |
ed39097c TR |
98 | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | ||
102 | ranges = <0x54000000 0x54000000 0x04000000>; | |
103 | ||
58ecb23f | 104 | mpe@54040000 { |
ed39097c TR |
105 | compatible = "nvidia,tegra30-mpe"; |
106 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 107 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 108 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
3393d422 SW |
109 | resets = <&tegra_car 60>; |
110 | reset-names = "mpe"; | |
ed39097c TR |
111 | }; |
112 | ||
58ecb23f | 113 | vi@54080000 { |
ed39097c TR |
114 | compatible = "nvidia,tegra30-vi"; |
115 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 116 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 117 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
3393d422 SW |
118 | resets = <&tegra_car 20>; |
119 | reset-names = "vi"; | |
ed39097c TR |
120 | }; |
121 | ||
58ecb23f | 122 | epp@540c0000 { |
ed39097c TR |
123 | compatible = "nvidia,tegra30-epp"; |
124 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 125 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 126 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
3393d422 SW |
127 | resets = <&tegra_car 19>; |
128 | reset-names = "epp"; | |
ed39097c TR |
129 | }; |
130 | ||
58ecb23f | 131 | isp@54100000 { |
ed39097c TR |
132 | compatible = "nvidia,tegra30-isp"; |
133 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 134 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 135 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
3393d422 SW |
136 | resets = <&tegra_car 23>; |
137 | reset-names = "isp"; | |
ed39097c TR |
138 | }; |
139 | ||
58ecb23f | 140 | gr2d@54140000 { |
ed39097c TR |
141 | compatible = "nvidia,tegra30-gr2d"; |
142 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 143 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
da45d738 | 144 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
3393d422 SW |
145 | resets = <&tegra_car 21>; |
146 | reset-names = "2d"; | |
ed39097c TR |
147 | }; |
148 | ||
58ecb23f | 149 | gr3d@54180000 { |
ed39097c TR |
150 | compatible = "nvidia,tegra30-gr3d"; |
151 | reg = <0x54180000 0x00040000>; | |
c71d3909 TR |
152 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
153 | &tegra_car TEGRA30_CLK_GR3D2>; | |
1cbc733d | 154 | clock-names = "3d", "3d2"; |
3393d422 | 155 | resets = <&tegra_car 24>, |
d8b316b2 | 156 | <&tegra_car 98>; |
3393d422 | 157 | reset-names = "3d", "3d2"; |
ed39097c TR |
158 | }; |
159 | ||
160 | dc@54200000 { | |
05465f4e | 161 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
ed39097c | 162 | reg = <0x54200000 0x00040000>; |
6cecf916 | 163 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
164 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
165 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 166 | clock-names = "dc", "parent"; |
3393d422 SW |
167 | resets = <&tegra_car 27>; |
168 | reset-names = "dc"; | |
ed39097c | 169 | |
6d9adf6f TR |
170 | iommus = <&mc TEGRA_SWGROUP_DC>; |
171 | ||
688b56b4 TR |
172 | nvidia,head = <0>; |
173 | ||
ed39097c TR |
174 | rgb { |
175 | status = "disabled"; | |
176 | }; | |
177 | }; | |
178 | ||
179 | dc@54240000 { | |
180 | compatible = "nvidia,tegra30-dc"; | |
181 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 182 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
183 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
184 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 185 | clock-names = "dc", "parent"; |
3393d422 SW |
186 | resets = <&tegra_car 26>; |
187 | reset-names = "dc"; | |
ed39097c | 188 | |
6d9adf6f TR |
189 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
190 | ||
688b56b4 TR |
191 | nvidia,head = <1>; |
192 | ||
ed39097c TR |
193 | rgb { |
194 | status = "disabled"; | |
195 | }; | |
196 | }; | |
197 | ||
58ecb23f | 198 | hdmi@54280000 { |
ed39097c TR |
199 | compatible = "nvidia,tegra30-hdmi"; |
200 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 201 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
202 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
203 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; | |
1cbc733d | 204 | clock-names = "hdmi", "parent"; |
3393d422 SW |
205 | resets = <&tegra_car 51>; |
206 | reset-names = "hdmi"; | |
ed39097c TR |
207 | status = "disabled"; |
208 | }; | |
209 | ||
58ecb23f | 210 | tvo@542c0000 { |
ed39097c TR |
211 | compatible = "nvidia,tegra30-tvo"; |
212 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 213 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 214 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
ed39097c TR |
215 | status = "disabled"; |
216 | }; | |
217 | ||
58ecb23f | 218 | dsi@54300000 { |
ed39097c TR |
219 | compatible = "nvidia,tegra30-dsi"; |
220 | reg = <0x54300000 0x00040000>; | |
05849c93 | 221 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
3393d422 SW |
222 | resets = <&tegra_car 48>; |
223 | reset-names = "dsi"; | |
ed39097c TR |
224 | status = "disabled"; |
225 | }; | |
226 | }; | |
227 | ||
2cda1880 | 228 | timer@50040600 { |
73368ba0 SW |
229 | compatible = "arm,cortex-a9-twd-timer"; |
230 | reg = <0x50040600 0x20>; | |
870c81a4 | 231 | interrupt-parent = <&intc>; |
6cecf916 | 232 | interrupts = <GIC_PPI 13 |
e7d9b270 | 233 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
05849c93 | 234 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
73368ba0 SW |
235 | }; |
236 | ||
58ecb23f | 237 | intc: interrupt-controller@50041000 { |
c3e00a0e | 238 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
239 | reg = <0x50041000 0x1000 |
240 | 0x50040100 0x0100>; | |
2eaab06e SW |
241 | interrupt-controller; |
242 | #interrupt-cells = <3>; | |
870c81a4 | 243 | interrupt-parent = <&intc>; |
c3e00a0e PDS |
244 | }; |
245 | ||
58ecb23f | 246 | cache-controller@50043000 { |
bb2c1de9 SW |
247 | compatible = "arm,pl310-cache"; |
248 | reg = <0x50043000 0x1000>; | |
249 | arm,data-latency = <6 6 2>; | |
250 | arm,tag-latency = <5 5 2>; | |
251 | cache-unified; | |
252 | cache-level = <2>; | |
253 | }; | |
254 | ||
870c81a4 MZ |
255 | lic: interrupt-controller@60004000 { |
256 | compatible = "nvidia,tegra30-ictlr"; | |
257 | reg = <0x60004000 0x100>, | |
258 | <0x60004100 0x50>, | |
259 | <0x60004200 0x50>, | |
260 | <0x60004300 0x50>, | |
261 | <0x60004400 0x50>; | |
262 | interrupt-controller; | |
263 | #interrupt-cells = <3>; | |
264 | interrupt-parent = <&intc>; | |
265 | }; | |
266 | ||
2f2b7fb2 SW |
267 | timer@60005000 { |
268 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
269 | reg = <0x60005000 0x400>; | |
6cecf916 SW |
270 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
271 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
272 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
273 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
274 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
275 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 276 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
2f2b7fb2 SW |
277 | }; |
278 | ||
58ecb23f | 279 | tegra_car: clock@60006000 { |
95985667 PG |
280 | compatible = "nvidia,tegra30-car"; |
281 | reg = <0x60006000 0x1000>; | |
282 | #clock-cells = <1>; | |
3393d422 | 283 | #reset-cells = <1>; |
95985667 PG |
284 | }; |
285 | ||
b1023134 TR |
286 | flow-controller@60007000 { |
287 | compatible = "nvidia,tegra30-flowctrl"; | |
288 | reg = <0x60007000 0x1000>; | |
289 | }; | |
290 | ||
58ecb23f | 291 | apbdma: dma@6000a000 { |
8051b75a SW |
292 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
293 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
294 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
295 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
296 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
297 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
298 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
299 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
300 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
301 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
302 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
303 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
304 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
305 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
306 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
308 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
309 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
310 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
314 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
315 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
316 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
317 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
318 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
319 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
320 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
321 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
322 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
323 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
324 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
325 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 326 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
3393d422 SW |
327 | resets = <&tegra_car 34>; |
328 | reset-names = "dma"; | |
034d023f | 329 | #dma-cells = <1>; |
8051b75a SW |
330 | }; |
331 | ||
0d5ccb38 | 332 | ahb: ahb@6000c000 { |
c04abb3a | 333 | compatible = "nvidia,tegra30-ahb"; |
0d5ccb38 | 334 | reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ |
c3e00a0e PDS |
335 | }; |
336 | ||
58ecb23f | 337 | gpio: gpio@6000d000 { |
35f210ec | 338 | compatible = "nvidia,tegra30-gpio"; |
95decf84 | 339 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
340 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
341 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
342 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
343 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
344 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
345 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
346 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
347 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
c3e00a0e PDS |
348 | #gpio-cells = <2>; |
349 | gpio-controller; | |
6f74dc9b SW |
350 | #interrupt-cells = <2>; |
351 | interrupt-controller; | |
4f1d8414 | 352 | /* |
17cdddf0 | 353 | gpio-ranges = <&pinmux 0 0 248>; |
4f1d8414 | 354 | */ |
c3e00a0e PDS |
355 | }; |
356 | ||
155dfc7b PDS |
357 | apbmisc@70000800 { |
358 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; | |
359 | reg = <0x70000800 0x64 /* Chip revision */ | |
360 | 0x70000008 0x04>; /* Strapping options */ | |
361 | }; | |
362 | ||
58ecb23f | 363 | pinmux: pinmux@70000868 { |
c04abb3a | 364 | compatible = "nvidia,tegra30-pinmux"; |
322337b8 PR |
365 | reg = <0x70000868 0xd4 /* Pad control registers */ |
366 | 0x70003000 0x3e4>; /* Mux registers */ | |
c04abb3a SW |
367 | }; |
368 | ||
b6551bb9 LD |
369 | /* |
370 | * There are two serial driver i.e. 8250 based simple serial | |
371 | * driver and APB DMA based serial driver for higher baudrate | |
372 | * and performace. To enable the 8250 based driver, the compatible | |
373 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable | |
e1098248 | 374 | * the APB DMA based serial driver, the compatible is |
b6551bb9 LD |
375 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
376 | */ | |
377 | uarta: serial@70006000 { | |
c3e00a0e PDS |
378 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
379 | reg = <0x70006000 0x40>; | |
380 | reg-shift = <2>; | |
6cecf916 | 381 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 382 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
3393d422 SW |
383 | resets = <&tegra_car 6>; |
384 | reset-names = "serial"; | |
034d023f SW |
385 | dmas = <&apbdma 8>, <&apbdma 8>; |
386 | dma-names = "rx", "tx"; | |
223ef78d | 387 | status = "disabled"; |
c3e00a0e PDS |
388 | }; |
389 | ||
b6551bb9 | 390 | uartb: serial@70006040 { |
c3e00a0e PDS |
391 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
392 | reg = <0x70006040 0x40>; | |
393 | reg-shift = <2>; | |
6cecf916 | 394 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 395 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
3393d422 SW |
396 | resets = <&tegra_car 7>; |
397 | reset-names = "serial"; | |
034d023f SW |
398 | dmas = <&apbdma 9>, <&apbdma 9>; |
399 | dma-names = "rx", "tx"; | |
223ef78d | 400 | status = "disabled"; |
c3e00a0e PDS |
401 | }; |
402 | ||
b6551bb9 | 403 | uartc: serial@70006200 { |
c3e00a0e PDS |
404 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
405 | reg = <0x70006200 0x100>; | |
406 | reg-shift = <2>; | |
6cecf916 | 407 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 408 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
3393d422 SW |
409 | resets = <&tegra_car 55>; |
410 | reset-names = "serial"; | |
034d023f SW |
411 | dmas = <&apbdma 10>, <&apbdma 10>; |
412 | dma-names = "rx", "tx"; | |
223ef78d | 413 | status = "disabled"; |
c3e00a0e PDS |
414 | }; |
415 | ||
b6551bb9 | 416 | uartd: serial@70006300 { |
c3e00a0e PDS |
417 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
418 | reg = <0x70006300 0x100>; | |
419 | reg-shift = <2>; | |
6cecf916 | 420 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 421 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
3393d422 SW |
422 | resets = <&tegra_car 65>; |
423 | reset-names = "serial"; | |
034d023f SW |
424 | dmas = <&apbdma 19>, <&apbdma 19>; |
425 | dma-names = "rx", "tx"; | |
223ef78d | 426 | status = "disabled"; |
c3e00a0e PDS |
427 | }; |
428 | ||
b6551bb9 | 429 | uarte: serial@70006400 { |
c3e00a0e PDS |
430 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
431 | reg = <0x70006400 0x100>; | |
432 | reg-shift = <2>; | |
6cecf916 | 433 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 434 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
3393d422 SW |
435 | resets = <&tegra_car 66>; |
436 | reset-names = "serial"; | |
034d023f SW |
437 | dmas = <&apbdma 20>, <&apbdma 20>; |
438 | dma-names = "rx", "tx"; | |
223ef78d | 439 | status = "disabled"; |
c3e00a0e PDS |
440 | }; |
441 | ||
5e35c1f0 MK |
442 | gmi@70009000 { |
443 | compatible = "nvidia,tegra30-gmi"; | |
444 | reg = <0x70009000 0x1000>; | |
445 | #address-cells = <2>; | |
446 | #size-cells = <1>; | |
447 | ranges = <0 0 0x48000000 0x7ffffff>; | |
448 | clocks = <&tegra_car TEGRA30_CLK_NOR>; | |
449 | clock-names = "gmi"; | |
450 | resets = <&tegra_car 42>; | |
451 | reset-names = "gmi"; | |
452 | status = "disabled"; | |
453 | }; | |
454 | ||
58ecb23f | 455 | pwm: pwm@7000a000 { |
140fd977 TR |
456 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
457 | reg = <0x7000a000 0x100>; | |
458 | #pwm-cells = <2>; | |
05849c93 | 459 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
3393d422 SW |
460 | resets = <&tegra_car 17>; |
461 | reset-names = "pwm"; | |
b69cd984 | 462 | status = "disabled"; |
140fd977 TR |
463 | }; |
464 | ||
58ecb23f | 465 | rtc@7000e000 { |
380e04ac SW |
466 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
467 | reg = <0x7000e000 0x100>; | |
6cecf916 | 468 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 469 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
380e04ac SW |
470 | }; |
471 | ||
c04abb3a | 472 | i2c@7000c000 { |
d8b316b2 | 473 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
c04abb3a | 474 | reg = <0x7000c000 0x100>; |
6cecf916 | 475 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
476 | #address-cells = <1>; |
477 | #size-cells = <0>; | |
05849c93 HD |
478 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
479 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 480 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
481 | resets = <&tegra_car 12>; |
482 | reset-names = "i2c"; | |
034d023f SW |
483 | dmas = <&apbdma 21>, <&apbdma 21>; |
484 | dma-names = "rx", "tx"; | |
223ef78d | 485 | status = "disabled"; |
c3e00a0e PDS |
486 | }; |
487 | ||
c04abb3a | 488 | i2c@7000c400 { |
c04abb3a SW |
489 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
490 | reg = <0x7000c400 0x100>; | |
6cecf916 | 491 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
492 | #address-cells = <1>; |
493 | #size-cells = <0>; | |
05849c93 HD |
494 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
495 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 496 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
497 | resets = <&tegra_car 54>; |
498 | reset-names = "i2c"; | |
034d023f SW |
499 | dmas = <&apbdma 22>, <&apbdma 22>; |
500 | dma-names = "rx", "tx"; | |
223ef78d | 501 | status = "disabled"; |
c3e00a0e PDS |
502 | }; |
503 | ||
c04abb3a | 504 | i2c@7000c500 { |
c04abb3a SW |
505 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
506 | reg = <0x7000c500 0x100>; | |
6cecf916 | 507 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
508 | #address-cells = <1>; |
509 | #size-cells = <0>; | |
05849c93 HD |
510 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
511 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 512 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
513 | resets = <&tegra_car 67>; |
514 | reset-names = "i2c"; | |
034d023f SW |
515 | dmas = <&apbdma 23>, <&apbdma 23>; |
516 | dma-names = "rx", "tx"; | |
223ef78d | 517 | status = "disabled"; |
c3e00a0e PDS |
518 | }; |
519 | ||
c04abb3a | 520 | i2c@7000c700 { |
c04abb3a SW |
521 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
522 | reg = <0x7000c700 0x100>; | |
6cecf916 | 523 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
524 | #address-cells = <1>; |
525 | #size-cells = <0>; | |
05849c93 HD |
526 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
527 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
3393d422 SW |
528 | resets = <&tegra_car 103>; |
529 | reset-names = "i2c"; | |
1cbc733d | 530 | clock-names = "div-clk", "fast-clk"; |
034d023f SW |
531 | dmas = <&apbdma 26>, <&apbdma 26>; |
532 | dma-names = "rx", "tx"; | |
223ef78d | 533 | status = "disabled"; |
c3e00a0e PDS |
534 | }; |
535 | ||
c04abb3a | 536 | i2c@7000d000 { |
c04abb3a SW |
537 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
538 | reg = <0x7000d000 0x100>; | |
6cecf916 | 539 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
540 | #address-cells = <1>; |
541 | #size-cells = <0>; | |
05849c93 HD |
542 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
543 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 544 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
545 | resets = <&tegra_car 47>; |
546 | reset-names = "i2c"; | |
034d023f SW |
547 | dmas = <&apbdma 24>, <&apbdma 24>; |
548 | dma-names = "rx", "tx"; | |
223ef78d | 549 | status = "disabled"; |
c04abb3a SW |
550 | }; |
551 | ||
a86b0db3 LD |
552 | spi@7000d400 { |
553 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
554 | reg = <0x7000d400 0x200>; | |
6cecf916 | 555 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
556 | #address-cells = <1>; |
557 | #size-cells = <0>; | |
05849c93 | 558 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
3393d422 SW |
559 | resets = <&tegra_car 41>; |
560 | reset-names = "spi"; | |
034d023f SW |
561 | dmas = <&apbdma 15>, <&apbdma 15>; |
562 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
563 | status = "disabled"; |
564 | }; | |
565 | ||
566 | spi@7000d600 { | |
567 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
568 | reg = <0x7000d600 0x200>; | |
6cecf916 | 569 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
570 | #address-cells = <1>; |
571 | #size-cells = <0>; | |
05849c93 | 572 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
3393d422 SW |
573 | resets = <&tegra_car 44>; |
574 | reset-names = "spi"; | |
034d023f SW |
575 | dmas = <&apbdma 16>, <&apbdma 16>; |
576 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
577 | status = "disabled"; |
578 | }; | |
579 | ||
580 | spi@7000d800 { | |
581 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
57471c8d | 582 | reg = <0x7000d800 0x200>; |
6cecf916 | 583 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
584 | #address-cells = <1>; |
585 | #size-cells = <0>; | |
05849c93 | 586 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
3393d422 SW |
587 | resets = <&tegra_car 46>; |
588 | reset-names = "spi"; | |
034d023f SW |
589 | dmas = <&apbdma 17>, <&apbdma 17>; |
590 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
591 | status = "disabled"; |
592 | }; | |
593 | ||
594 | spi@7000da00 { | |
595 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
596 | reg = <0x7000da00 0x200>; | |
6cecf916 | 597 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
598 | #address-cells = <1>; |
599 | #size-cells = <0>; | |
05849c93 | 600 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
3393d422 SW |
601 | resets = <&tegra_car 68>; |
602 | reset-names = "spi"; | |
034d023f SW |
603 | dmas = <&apbdma 18>, <&apbdma 18>; |
604 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
605 | status = "disabled"; |
606 | }; | |
607 | ||
608 | spi@7000dc00 { | |
609 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
610 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 611 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
612 | #address-cells = <1>; |
613 | #size-cells = <0>; | |
05849c93 | 614 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
3393d422 SW |
615 | resets = <&tegra_car 104>; |
616 | reset-names = "spi"; | |
034d023f SW |
617 | dmas = <&apbdma 27>, <&apbdma 27>; |
618 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
619 | status = "disabled"; |
620 | }; | |
621 | ||
622 | spi@7000de00 { | |
623 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
624 | reg = <0x7000de00 0x200>; | |
6cecf916 | 625 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
626 | #address-cells = <1>; |
627 | #size-cells = <0>; | |
05849c93 | 628 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
3393d422 SW |
629 | resets = <&tegra_car 106>; |
630 | reset-names = "spi"; | |
034d023f SW |
631 | dmas = <&apbdma 28>, <&apbdma 28>; |
632 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
633 | status = "disabled"; |
634 | }; | |
635 | ||
58ecb23f | 636 | kbc@7000e200 { |
699ed4b9 LD |
637 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
638 | reg = <0x7000e200 0x100>; | |
6cecf916 | 639 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 640 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
3393d422 SW |
641 | resets = <&tegra_car 36>; |
642 | reset-names = "kbc"; | |
699ed4b9 LD |
643 | status = "disabled"; |
644 | }; | |
645 | ||
58ecb23f | 646 | pmc@7000e400 { |
2b84e53b | 647 | compatible = "nvidia,tegra30-pmc"; |
c04abb3a | 648 | reg = <0x7000e400 0x400>; |
05849c93 | 649 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 650 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
651 | }; |
652 | ||
a9fe468f | 653 | mc: memory-controller@7000f000 { |
c04abb3a | 654 | compatible = "nvidia,tegra30-mc"; |
a9fe468f TR |
655 | reg = <0x7000f000 0x400>; |
656 | clocks = <&tegra_car TEGRA30_CLK_MC>; | |
657 | clock-names = "mc"; | |
658 | ||
6cecf916 | 659 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a | 660 | |
a9fe468f | 661 | #iommu-cells = <1>; |
c3e00a0e | 662 | }; |
9ee6a5c4 | 663 | |
155dfc7b PDS |
664 | fuse@7000f800 { |
665 | compatible = "nvidia,tegra30-efuse"; | |
666 | reg = <0x7000f800 0x400>; | |
667 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; | |
668 | clock-names = "fuse"; | |
669 | resets = <&tegra_car 39>; | |
670 | reset-names = "fuse"; | |
671 | }; | |
672 | ||
cbee2613 MZ |
673 | hda@70030000 { |
674 | compatible = "nvidia,tegra30-hda"; | |
675 | reg = <0x70030000 0x10000>; | |
676 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
677 | clocks = <&tegra_car TEGRA30_CLK_HDA>, | |
d8b316b2 | 678 | <&tegra_car TEGRA30_CLK_HDA2HDMI>, |
cbee2613 MZ |
679 | <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; |
680 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
681 | resets = <&tegra_car 125>, /* hda */ | |
682 | <&tegra_car 128>, /* hda2hdmi */ | |
683 | <&tegra_car 111>; /* hda2codec_2x */ | |
684 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
685 | status = "disabled"; | |
686 | }; | |
687 | ||
58ecb23f | 688 | ahub@70080000 { |
9ee6a5c4 | 689 | compatible = "nvidia,tegra30-ahub"; |
5ff48887 SW |
690 | reg = <0x70080000 0x200 |
691 | 0x70080200 0x100>; | |
6cecf916 | 692 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 693 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
2bd541ff SW |
694 | <&tegra_car TEGRA30_CLK_APBIF>; |
695 | clock-names = "d_audio", "apbif"; | |
3393d422 SW |
696 | resets = <&tegra_car 106>, /* d_audio */ |
697 | <&tegra_car 107>, /* apbif */ | |
698 | <&tegra_car 30>, /* i2s0 */ | |
699 | <&tegra_car 11>, /* i2s1 */ | |
700 | <&tegra_car 18>, /* i2s2 */ | |
701 | <&tegra_car 101>, /* i2s3 */ | |
702 | <&tegra_car 102>, /* i2s4 */ | |
703 | <&tegra_car 108>, /* dam0 */ | |
704 | <&tegra_car 109>, /* dam1 */ | |
705 | <&tegra_car 110>, /* dam2 */ | |
706 | <&tegra_car 10>; /* spdif */ | |
707 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
708 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
709 | "spdif"; | |
034d023f SW |
710 | dmas = <&apbdma 1>, <&apbdma 1>, |
711 | <&apbdma 2>, <&apbdma 2>, | |
712 | <&apbdma 3>, <&apbdma 3>, | |
713 | <&apbdma 4>, <&apbdma 4>; | |
714 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
715 | "rx3", "tx3"; | |
9ee6a5c4 SW |
716 | ranges; |
717 | #address-cells = <1>; | |
718 | #size-cells = <1>; | |
719 | ||
720 | tegra_i2s0: i2s@70080300 { | |
721 | compatible = "nvidia,tegra30-i2s"; | |
722 | reg = <0x70080300 0x100>; | |
723 | nvidia,ahub-cif-ids = <4 4>; | |
05849c93 | 724 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
3393d422 SW |
725 | resets = <&tegra_car 30>; |
726 | reset-names = "i2s"; | |
223ef78d | 727 | status = "disabled"; |
9ee6a5c4 SW |
728 | }; |
729 | ||
730 | tegra_i2s1: i2s@70080400 { | |
731 | compatible = "nvidia,tegra30-i2s"; | |
732 | reg = <0x70080400 0x100>; | |
733 | nvidia,ahub-cif-ids = <5 5>; | |
05849c93 | 734 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
3393d422 SW |
735 | resets = <&tegra_car 11>; |
736 | reset-names = "i2s"; | |
223ef78d | 737 | status = "disabled"; |
9ee6a5c4 SW |
738 | }; |
739 | ||
740 | tegra_i2s2: i2s@70080500 { | |
741 | compatible = "nvidia,tegra30-i2s"; | |
742 | reg = <0x70080500 0x100>; | |
743 | nvidia,ahub-cif-ids = <6 6>; | |
05849c93 | 744 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
3393d422 SW |
745 | resets = <&tegra_car 18>; |
746 | reset-names = "i2s"; | |
223ef78d | 747 | status = "disabled"; |
9ee6a5c4 SW |
748 | }; |
749 | ||
750 | tegra_i2s3: i2s@70080600 { | |
751 | compatible = "nvidia,tegra30-i2s"; | |
752 | reg = <0x70080600 0x100>; | |
753 | nvidia,ahub-cif-ids = <7 7>; | |
05849c93 | 754 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
3393d422 SW |
755 | resets = <&tegra_car 101>; |
756 | reset-names = "i2s"; | |
223ef78d | 757 | status = "disabled"; |
9ee6a5c4 SW |
758 | }; |
759 | ||
760 | tegra_i2s4: i2s@70080700 { | |
761 | compatible = "nvidia,tegra30-i2s"; | |
762 | reg = <0x70080700 0x100>; | |
763 | nvidia,ahub-cif-ids = <8 8>; | |
05849c93 | 764 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
3393d422 SW |
765 | resets = <&tegra_car 102>; |
766 | reset-names = "i2s"; | |
223ef78d | 767 | status = "disabled"; |
9ee6a5c4 SW |
768 | }; |
769 | }; | |
7868a9bc | 770 | |
c04abb3a SW |
771 | sdhci@78000000 { |
772 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
773 | reg = <0x78000000 0x200>; | |
6cecf916 | 774 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 775 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
3393d422 SW |
776 | resets = <&tegra_car 14>; |
777 | reset-names = "sdhci"; | |
223ef78d | 778 | status = "disabled"; |
7868a9bc | 779 | }; |
ecf43742 | 780 | |
c04abb3a SW |
781 | sdhci@78000200 { |
782 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
783 | reg = <0x78000200 0x200>; | |
6cecf916 | 784 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 785 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
3393d422 SW |
786 | resets = <&tegra_car 9>; |
787 | reset-names = "sdhci"; | |
223ef78d | 788 | status = "disabled"; |
ecf43742 | 789 | }; |
54174a33 | 790 | |
c04abb3a SW |
791 | sdhci@78000400 { |
792 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
793 | reg = <0x78000400 0x200>; | |
6cecf916 | 794 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 795 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
3393d422 SW |
796 | resets = <&tegra_car 69>; |
797 | reset-names = "sdhci"; | |
223ef78d | 798 | status = "disabled"; |
c04abb3a SW |
799 | }; |
800 | ||
801 | sdhci@78000600 { | |
802 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
803 | reg = <0x78000600 0x200>; | |
6cecf916 | 804 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 805 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
3393d422 SW |
806 | resets = <&tegra_car 15>; |
807 | reset-names = "sdhci"; | |
223ef78d | 808 | status = "disabled"; |
c04abb3a SW |
809 | }; |
810 | ||
cc34c9f7 TT |
811 | usb@7d000000 { |
812 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
813 | reg = <0x7d000000 0x4000>; | |
814 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
815 | phy_type = "utmi"; | |
816 | clocks = <&tegra_car TEGRA30_CLK_USBD>; | |
3393d422 SW |
817 | resets = <&tegra_car 22>; |
818 | reset-names = "usb"; | |
cc34c9f7 TT |
819 | nvidia,needs-double-reset; |
820 | nvidia,phy = <&phy1>; | |
821 | status = "disabled"; | |
822 | }; | |
823 | ||
824 | phy1: usb-phy@7d000000 { | |
825 | compatible = "nvidia,tegra30-usb-phy"; | |
826 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; | |
827 | phy_type = "utmi"; | |
828 | clocks = <&tegra_car TEGRA30_CLK_USBD>, | |
829 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
830 | <&tegra_car TEGRA30_CLK_USBD>; | |
831 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
832 | resets = <&tegra_car 22>, <&tegra_car 22>; |
833 | reset-names = "usb", "utmi-pads"; | |
cc34c9f7 TT |
834 | nvidia,hssync-start-delay = <9>; |
835 | nvidia,idle-wait-delay = <17>; | |
836 | nvidia,elastic-limit = <16>; | |
837 | nvidia,term-range-adj = <6>; | |
838 | nvidia,xcvr-setup = <51>; | |
839 | nvidia.xcvr-setup-use-fuses; | |
840 | nvidia,xcvr-lsfslew = <1>; | |
841 | nvidia,xcvr-lsrslew = <1>; | |
842 | nvidia,xcvr-hsslew = <32>; | |
843 | nvidia,hssquelch-level = <2>; | |
844 | nvidia,hsdiscon-level = <5>; | |
308efde2 | 845 | nvidia,has-utmi-pad-registers; |
cc34c9f7 TT |
846 | status = "disabled"; |
847 | }; | |
848 | ||
849 | usb@7d004000 { | |
850 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
851 | reg = <0x7d004000 0x4000>; | |
852 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
fd6441ec | 853 | phy_type = "utmi"; |
cc34c9f7 | 854 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
3393d422 SW |
855 | resets = <&tegra_car 58>; |
856 | reset-names = "usb"; | |
cc34c9f7 TT |
857 | nvidia,phy = <&phy2>; |
858 | status = "disabled"; | |
859 | }; | |
860 | ||
861 | phy2: usb-phy@7d004000 { | |
862 | compatible = "nvidia,tegra30-usb-phy"; | |
fd6441ec EB |
863 | reg = <0x7d004000 0x4000 0x7d000000 0x4000>; |
864 | phy_type = "utmi"; | |
cc34c9f7 TT |
865 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
866 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
fd6441ec EB |
867 | <&tegra_car TEGRA30_CLK_USBD>; |
868 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
869 | resets = <&tegra_car 58>, <&tegra_car 22>; |
870 | reset-names = "usb", "utmi-pads"; | |
fd6441ec EB |
871 | nvidia,hssync-start-delay = <9>; |
872 | nvidia,idle-wait-delay = <17>; | |
873 | nvidia,elastic-limit = <16>; | |
874 | nvidia,term-range-adj = <6>; | |
875 | nvidia,xcvr-setup = <51>; | |
876 | nvidia.xcvr-setup-use-fuses; | |
877 | nvidia,xcvr-lsfslew = <2>; | |
878 | nvidia,xcvr-lsrslew = <2>; | |
879 | nvidia,xcvr-hsslew = <32>; | |
880 | nvidia,hssquelch-level = <2>; | |
881 | nvidia,hsdiscon-level = <5>; | |
cc34c9f7 TT |
882 | status = "disabled"; |
883 | }; | |
884 | ||
885 | usb@7d008000 { | |
886 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
887 | reg = <0x7d008000 0x4000>; | |
888 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
889 | phy_type = "utmi"; | |
890 | clocks = <&tegra_car TEGRA30_CLK_USB3>; | |
3393d422 SW |
891 | resets = <&tegra_car 59>; |
892 | reset-names = "usb"; | |
cc34c9f7 TT |
893 | nvidia,phy = <&phy3>; |
894 | status = "disabled"; | |
895 | }; | |
896 | ||
897 | phy3: usb-phy@7d008000 { | |
898 | compatible = "nvidia,tegra30-usb-phy"; | |
899 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; | |
900 | phy_type = "utmi"; | |
901 | clocks = <&tegra_car TEGRA30_CLK_USB3>, | |
902 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
903 | <&tegra_car TEGRA30_CLK_USBD>; | |
904 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
905 | resets = <&tegra_car 59>, <&tegra_car 22>; |
906 | reset-names = "usb", "utmi-pads"; | |
cc34c9f7 TT |
907 | nvidia,hssync-start-delay = <0>; |
908 | nvidia,idle-wait-delay = <17>; | |
909 | nvidia,elastic-limit = <16>; | |
910 | nvidia,term-range-adj = <6>; | |
911 | nvidia,xcvr-setup = <51>; | |
912 | nvidia.xcvr-setup-use-fuses; | |
913 | nvidia,xcvr-lsfslew = <2>; | |
914 | nvidia,xcvr-lsrslew = <2>; | |
915 | nvidia,xcvr-hsslew = <32>; | |
916 | nvidia,hssquelch-level = <2>; | |
917 | nvidia,hsdiscon-level = <5>; | |
918 | status = "disabled"; | |
919 | }; | |
920 | ||
7d19a34a HD |
921 | cpus { |
922 | #address-cells = <1>; | |
923 | #size-cells = <0>; | |
924 | ||
925 | cpu@0 { | |
926 | device_type = "cpu"; | |
927 | compatible = "arm,cortex-a9"; | |
928 | reg = <0>; | |
929 | }; | |
930 | ||
931 | cpu@1 { | |
932 | device_type = "cpu"; | |
933 | compatible = "arm,cortex-a9"; | |
934 | reg = <1>; | |
935 | }; | |
936 | ||
937 | cpu@2 { | |
938 | device_type = "cpu"; | |
939 | compatible = "arm,cortex-a9"; | |
940 | reg = <2>; | |
941 | }; | |
942 | ||
943 | cpu@3 { | |
944 | device_type = "cpu"; | |
945 | compatible = "arm,cortex-a9"; | |
946 | reg = <3>; | |
947 | }; | |
948 | }; | |
949 | ||
c04abb3a SW |
950 | pmu { |
951 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
952 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
953 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
954 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
955 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
54174a33 | 956 | }; |
c3e00a0e | 957 | }; |