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USB: EHCI: tegra: use reset framework
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 4
1bd0bd49 5#include "skeleton.dtsi"
c3e00a0e
PDS		 6
7/ {
8 compatible = "nvidia,tegra30";
9 interrupt-parent = <&intc>;
10
b6551bb9
LD		 11 aliases {
12 serial0 = &uarta;
13 serial1 = &uartb;
14 serial2 = &uartc;
15 serial3 = &uartd;
16 serial4 = &uarte;
17 };
18
e07e3dbd
TR		 19 pcie-controller {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 38 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 40
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
3393d422
SW		 47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 51 status = "disabled";
52
53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 status = "disabled";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61 ranges;
62
63 nvidia,num-lanes = <2>;
64 };
65
66 pci@2,0 {
67 device_type = "pci";
68 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
83 status = "disabled";
84
85 #address-cells = <3>;
86 #size-cells = <2>;
87 ranges;
88
89 nvidia,num-lanes = <2>;
90 };
91 };
92
ed39097c
TR		 93 host1x {
94 compatible = "nvidia,tegra30-host1x", "simple-bus";
95 reg = <0x50000000 0x00024000>;
6cecf916
SW		 96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
ed39097c
TR		 101
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 ranges = <0x54000000 0x54000000 0x04000000>;
106
107 mpe {
108 compatible = "nvidia,tegra30-mpe";
109 reg = <0x54040000 0x00040000>;
6cecf916 110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 112 resets = <&tegra_car 60>;
113 reset-names = "mpe";
ed39097c
TR		 114 };
115
116 vi {
117 compatible = "nvidia,tegra30-vi";
118 reg = <0x54080000 0x00040000>;
6cecf916 119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 120 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 121 resets = <&tegra_car 20>;
122 reset-names = "vi";
ed39097c
TR		 123 };
124
125 epp {
126 compatible = "nvidia,tegra30-epp";
127 reg = <0x540c0000 0x00040000>;
6cecf916 128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 130 resets = <&tegra_car 19>;
131 reset-names = "epp";
ed39097c
TR		 132 };
133
134 isp {
135 compatible = "nvidia,tegra30-isp";
136 reg = <0x54100000 0x00040000>;
6cecf916 137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 139 resets = <&tegra_car 23>;
140 reset-names = "isp";
ed39097c
TR		 141 };
142
143 gr2d {
144 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>;
6cecf916 146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3393d422
SW		 147 resets = <&tegra_car 21>;
148 reset-names = "2d";
05849c93 149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
ed39097c
TR		 150 };
151
152 gr3d {
153 compatible = "nvidia,tegra30-gr3d";
154 reg = <0x54180000 0x00040000>;
c71d3909
TR		 155 clocks = <&tegra_car TEGRA30_CLK_GR3D
156 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 157 clock-names = "3d", "3d2";
3393d422
SW		 158 resets = <&tegra_car 24>,
159 <&tegra_car 98>;
160 reset-names = "3d", "3d2";
ed39097c
TR		 161 };
162
163 dc@54200000 {
05465f4e 164 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 165 reg = <0x54200000 0x00040000>;
6cecf916 166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
168 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 169 clock-names = "dc", "parent";
3393d422
SW		 170 resets = <&tegra_car 27>;
171 reset-names = "dc";
ed39097c
TR		 172
173 rgb {
174 status = "disabled";
175 };
176 };
177
178 dc@54240000 {
179 compatible = "nvidia,tegra30-dc";
180 reg = <0x54240000 0x00040000>;
6cecf916 181 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 182 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
183 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 184 clock-names = "dc", "parent";
3393d422
SW		 185 resets = <&tegra_car 26>;
186 reset-names = "dc";
ed39097c
TR		 187
188 rgb {
189 status = "disabled";
190 };
191 };
192
193 hdmi {
194 compatible = "nvidia,tegra30-hdmi";
195 reg = <0x54280000 0x00040000>;
6cecf916 196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 199 clock-names = "hdmi", "parent";
3393d422
SW		 200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
ed39097c
TR		 202 status = "disabled";
203 };
204
205 tvo {
206 compatible = "nvidia,tegra30-tvo";
207 reg = <0x542c0000 0x00040000>;
6cecf916 208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 209 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 210 status = "disabled";
211 };
212
213 dsi {
214 compatible = "nvidia,tegra30-dsi";
215 reg = <0x54300000 0x00040000>;
05849c93 216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 217 resets = <&tegra_car 48>;
218 reset-names = "dsi";
ed39097c
TR		 219 status = "disabled";
220 };
221 };
222
73368ba0
SW		 223 timer@50004600 {
224 compatible = "arm,cortex-a9-twd-timer";
225 reg = <0x50040600 0x20>;
6cecf916
SW		 226 interrupts = <GIC_PPI 13
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 229 };
230
f9eb26a4 231 intc: interrupt-controller {
c3e00a0e 232 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 233 reg = <0x50041000 0x1000
234 0x50040100 0x0100>;
2eaab06e
SW		 235 interrupt-controller;
236 #interrupt-cells = <3>;
c3e00a0e
PDS		 237 };
238
bb2c1de9
SW		 239 cache-controller {
240 compatible = "arm,pl310-cache";
241 reg = <0x50043000 0x1000>;
242 arm,data-latency = <6 6 2>;
243 arm,tag-latency = <5 5 2>;
244 cache-unified;
245 cache-level = <2>;
246 };
247
2f2b7fb2
SW		 248 timer@60005000 {
249 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
250 reg = <0x60005000 0x400>;
6cecf916
SW		 251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 258 };
259
95985667
PG		 260 tegra_car: clock {
261 compatible = "nvidia,tegra30-car";
262 reg = <0x60006000 0x1000>;
263 #clock-cells = <1>;
3393d422 264 #reset-cells = <1>;
95985667
PG		 265 };
266
f9eb26a4 267 apbdma: dma {
8051b75a
SW		 268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
269 reg = <0x6000a000 0x1400>;
6cecf916
SW		 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 302 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 303 resets = <&tegra_car 34>;
304 reset-names = "dma";
034d023f 305 #dma-cells = <1>;
8051b75a
SW		 306 };
307
c04abb3a
SW		 308 ahb: ahb {
309 compatible = "nvidia,tegra30-ahb";
310 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 311 };
312
f9eb26a4 313 gpio: gpio {
35f210ec 314 compatible = "nvidia,tegra30-gpio";
95decf84 315 reg = <0x6000d000 0x1000>;
6cecf916
SW		 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 324 #gpio-cells = <2>;
325 gpio-controller;
6f74dc9b
SW		 326 #interrupt-cells = <2>;
327 interrupt-controller;
c3e00a0e
PDS		 328 };
329
c04abb3a
SW		 330 pinmux: pinmux {
331 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 332 reg = <0x70000868 0xd4 /* Pad control registers */
333 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 334 };
335
b6551bb9
LD		 336 /*
337 * There are two serial driver i.e. 8250 based simple serial
338 * driver and APB DMA based serial driver for higher baudrate
339 * and performace. To enable the 8250 based driver, the compatible
340 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
341 * the APB DMA based serial driver, the comptible is
342 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
343 */
344 uarta: serial@70006000 {
c3e00a0e
PDS		 345 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
346 reg = <0x70006000 0x40>;
347 reg-shift = <2>;
6cecf916 348 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 349 nvidia,dma-request-selector = <&apbdma 8>;
05849c93 350 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 351 resets = <&tegra_car 6>;
352 reset-names = "serial";
034d023f
SW		 353 dmas = <&apbdma 8>, <&apbdma 8>;
354 dma-names = "rx", "tx";
223ef78d 355 status = "disabled";
c3e00a0e
PDS		 356 };
357
b6551bb9 358 uartb: serial@70006040 {
c3e00a0e
PDS		 359 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
360 reg = <0x70006040 0x40>;
361 reg-shift = <2>;
6cecf916 362 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 363 nvidia,dma-request-selector = <&apbdma 9>;
05849c93 364 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 365 resets = <&tegra_car 7>;
366 reset-names = "serial";
034d023f
SW		 367 dmas = <&apbdma 9>, <&apbdma 9>;
368 dma-names = "rx", "tx";
223ef78d 369 status = "disabled";
c3e00a0e
PDS		 370 };
371
b6551bb9 372 uartc: serial@70006200 {
c3e00a0e
PDS		 373 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
374 reg = <0x70006200 0x100>;
375 reg-shift = <2>;
6cecf916 376 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 377 nvidia,dma-request-selector = <&apbdma 10>;
05849c93 378 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 379 resets = <&tegra_car 55>;
380 reset-names = "serial";
034d023f
SW		 381 dmas = <&apbdma 10>, <&apbdma 10>;
382 dma-names = "rx", "tx";
223ef78d 383 status = "disabled";
c3e00a0e
PDS		 384 };
385
b6551bb9 386 uartd: serial@70006300 {
c3e00a0e
PDS		 387 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
388 reg = <0x70006300 0x100>;
389 reg-shift = <2>;
6cecf916 390 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 391 nvidia,dma-request-selector = <&apbdma 19>;
05849c93 392 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 393 resets = <&tegra_car 65>;
394 reset-names = "serial";
034d023f
SW		 395 dmas = <&apbdma 19>, <&apbdma 19>;
396 dma-names = "rx", "tx";
223ef78d 397 status = "disabled";
c3e00a0e
PDS		 398 };
399
b6551bb9 400 uarte: serial@70006400 {
c3e00a0e
PDS		 401 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
402 reg = <0x70006400 0x100>;
403 reg-shift = <2>;
6cecf916 404 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 405 nvidia,dma-request-selector = <&apbdma 20>;
05849c93 406 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 407 resets = <&tegra_car 66>;
408 reset-names = "serial";
034d023f
SW		 409 dmas = <&apbdma 20>, <&apbdma 20>;
410 dma-names = "rx", "tx";
223ef78d 411 status = "disabled";
c3e00a0e
PDS		 412 };
413
2b8b15da 414 pwm: pwm {
140fd977
TR		 415 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
416 reg = <0x7000a000 0x100>;
417 #pwm-cells = <2>;
05849c93 418 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 419 resets = <&tegra_car 17>;
420 reset-names = "pwm";
b69cd984 421 status = "disabled";
140fd977
TR		 422 };
423
380e04ac
SW		 424 rtc {
425 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
426 reg = <0x7000e000 0x100>;
6cecf916 427 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 428 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 429 };
430
c04abb3a 431 i2c@7000c000 {
c04abb3a
SW		 432 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
433 reg = <0x7000c000 0x100>;
6cecf916 434 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 435 #address-cells = <1>;
436 #size-cells = <0>;
05849c93
HD		 437 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
438 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 439 clock-names = "div-clk", "fast-clk";
3393d422
SW		 440 resets = <&tegra_car 12>;
441 reset-names = "i2c";
034d023f
SW		 442 dmas = <&apbdma 21>, <&apbdma 21>;
443 dma-names = "rx", "tx";
223ef78d 444 status = "disabled";
c3e00a0e
PDS		 445 };
446
c04abb3a 447 i2c@7000c400 {
c04abb3a
SW		 448 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
449 reg = <0x7000c400 0x100>;
6cecf916 450 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 451 #address-cells = <1>;
452 #size-cells = <0>;
05849c93
HD		 453 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
454 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 455 clock-names = "div-clk", "fast-clk";
3393d422
SW		 456 resets = <&tegra_car 54>;
457 reset-names = "i2c";
034d023f
SW		 458 dmas = <&apbdma 22>, <&apbdma 22>;
459 dma-names = "rx", "tx";
223ef78d 460 status = "disabled";
c3e00a0e
PDS		 461 };
462
c04abb3a 463 i2c@7000c500 {
c04abb3a
SW		 464 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
465 reg = <0x7000c500 0x100>;
6cecf916 466 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 467 #address-cells = <1>;
468 #size-cells = <0>;
05849c93
HD		 469 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
470 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 471 clock-names = "div-clk", "fast-clk";
3393d422
SW		 472 resets = <&tegra_car 67>;
473 reset-names = "i2c";
034d023f
SW		 474 dmas = <&apbdma 23>, <&apbdma 23>;
475 dma-names = "rx", "tx";
223ef78d 476 status = "disabled";
c3e00a0e
PDS		 477 };
478
c04abb3a 479 i2c@7000c700 {
c04abb3a
SW		 480 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
481 reg = <0x7000c700 0x100>;
6cecf916 482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 483 #address-cells = <1>;
484 #size-cells = <0>;
05849c93
HD		 485 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
486 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 487 resets = <&tegra_car 103>;
488 reset-names = "i2c";
1cbc733d 489 clock-names = "div-clk", "fast-clk";
034d023f
SW		 490 dmas = <&apbdma 26>, <&apbdma 26>;
491 dma-names = "rx", "tx";
223ef78d 492 status = "disabled";
c3e00a0e
PDS		 493 };
494
c04abb3a 495 i2c@7000d000 {
c04abb3a
SW		 496 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
497 reg = <0x7000d000 0x100>;
6cecf916 498 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 499 #address-cells = <1>;
500 #size-cells = <0>;
05849c93
HD		 501 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
502 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 503 clock-names = "div-clk", "fast-clk";
3393d422
SW		 504 resets = <&tegra_car 47>;
505 reset-names = "i2c";
034d023f
SW		 506 dmas = <&apbdma 24>, <&apbdma 24>;
507 dma-names = "rx", "tx";
223ef78d 508 status = "disabled";
c04abb3a
SW		 509 };
510
a86b0db3
LD		 511 spi@7000d400 {
512 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
513 reg = <0x7000d400 0x200>;
6cecf916 514 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 515 nvidia,dma-request-selector = <&apbdma 15>;
516 #address-cells = <1>;
517 #size-cells = <0>;
05849c93 518 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 519 resets = <&tegra_car 41>;
520 reset-names = "spi";
034d023f
SW		 521 dmas = <&apbdma 15>, <&apbdma 15>;
522 dma-names = "rx", "tx";
a86b0db3
LD		 523 status = "disabled";
524 };
525
526 spi@7000d600 {
527 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
528 reg = <0x7000d600 0x200>;
6cecf916 529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 530 nvidia,dma-request-selector = <&apbdma 16>;
531 #address-cells = <1>;
532 #size-cells = <0>;
05849c93 533 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 534 resets = <&tegra_car 44>;
535 reset-names = "spi";
034d023f
SW		 536 dmas = <&apbdma 16>, <&apbdma 16>;
537 dma-names = "rx", "tx";
a86b0db3
LD		 538 status = "disabled";
539 };
540
541 spi@7000d800 {
542 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 543 reg = <0x7000d800 0x200>;
6cecf916 544 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 545 nvidia,dma-request-selector = <&apbdma 17>;
546 #address-cells = <1>;
547 #size-cells = <0>;
05849c93 548 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 549 resets = <&tegra_car 46>;
550 reset-names = "spi";
034d023f
SW		 551 dmas = <&apbdma 17>, <&apbdma 17>;
552 dma-names = "rx", "tx";
a86b0db3
LD		 553 status = "disabled";
554 };
555
556 spi@7000da00 {
557 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
558 reg = <0x7000da00 0x200>;
6cecf916 559 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 560 nvidia,dma-request-selector = <&apbdma 18>;
561 #address-cells = <1>;
562 #size-cells = <0>;
05849c93 563 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 564 resets = <&tegra_car 68>;
565 reset-names = "spi";
034d023f
SW		 566 dmas = <&apbdma 18>, <&apbdma 18>;
567 dma-names = "rx", "tx";
a86b0db3
LD		 568 status = "disabled";
569 };
570
571 spi@7000dc00 {
572 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
573 reg = <0x7000dc00 0x200>;
6cecf916 574 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 575 nvidia,dma-request-selector = <&apbdma 27>;
576 #address-cells = <1>;
577 #size-cells = <0>;
05849c93 578 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 579 resets = <&tegra_car 104>;
580 reset-names = "spi";
034d023f
SW		 581 dmas = <&apbdma 27>, <&apbdma 27>;
582 dma-names = "rx", "tx";
a86b0db3
LD		 583 status = "disabled";
584 };
585
586 spi@7000de00 {
587 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
588 reg = <0x7000de00 0x200>;
6cecf916 589 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 590 nvidia,dma-request-selector = <&apbdma 28>;
591 #address-cells = <1>;
592 #size-cells = <0>;
05849c93 593 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 594 resets = <&tegra_car 106>;
595 reset-names = "spi";
034d023f
SW		 596 dmas = <&apbdma 28>, <&apbdma 28>;
597 dma-names = "rx", "tx";
a86b0db3
LD		 598 status = "disabled";
599 };
600
699ed4b9
LD		 601 kbc {
602 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
603 reg = <0x7000e200 0x100>;
6cecf916 604 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 605 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 606 resets = <&tegra_car 36>;
607 reset-names = "kbc";
699ed4b9
LD		 608 status = "disabled";
609 };
610
c04abb3a 611 pmc {
2b84e53b 612 compatible = "nvidia,tegra30-pmc";
c04abb3a 613 reg = <0x7000e400 0x400>;
05849c93 614 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 615 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 616 };
617
a9140aa5 618 memory-controller {
c04abb3a
SW		 619 compatible = "nvidia,tegra30-mc";
620 reg = <0x7000f000 0x010
621 0x7000f03c 0x1b4
622 0x7000f200 0x028
623 0x7000f284 0x17c>;
6cecf916 624 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 625 };
626
3fbf07d8 627 iommu {
c04abb3a
SW		 628 compatible = "nvidia,tegra30-smmu";
629 reg = <0x7000f010 0x02c
630 0x7000f1f0 0x010
631 0x7000f228 0x05c>;
632 nvidia,#asids = <4>; /* # of ASIDs */
633 dma-window = <0 0x40000000>; /* IOVA start & length */
634 nvidia,ahb = <&ahb>;
c3e00a0e 635 };
9ee6a5c4
SW		 636
637 ahub {
638 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 639 reg = <0x70080000 0x200
640 0x70080200 0x100>;
6cecf916 641 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9ee6a5c4 642 nvidia,dma-request-selector = <&apbdma 1>;
05849c93
HD		 643 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
644 <&tegra_car TEGRA30_CLK_APBIF>,
645 <&tegra_car TEGRA30_CLK_I2S0>,
646 <&tegra_car TEGRA30_CLK_I2S1>,
647 <&tegra_car TEGRA30_CLK_I2S2>,
648 <&tegra_car TEGRA30_CLK_I2S3>,
649 <&tegra_car TEGRA30_CLK_I2S4>,
650 <&tegra_car TEGRA30_CLK_DAM0>,
651 <&tegra_car TEGRA30_CLK_DAM1>,
652 <&tegra_car TEGRA30_CLK_DAM2>,
653 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
1cbc733d
PG		 654 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
655 "i2s3", "i2s4", "dam0", "dam1", "dam2",
656 "spdif_in";
3393d422
SW		 657 resets = <&tegra_car 106>, /* d_audio */
658 <&tegra_car 107>, /* apbif */
659 <&tegra_car 30>, /* i2s0 */
660 <&tegra_car 11>, /* i2s1 */
661 <&tegra_car 18>, /* i2s2 */
662 <&tegra_car 101>, /* i2s3 */
663 <&tegra_car 102>, /* i2s4 */
664 <&tegra_car 108>, /* dam0 */
665 <&tegra_car 109>, /* dam1 */
666 <&tegra_car 110>, /* dam2 */
667 <&tegra_car 10>; /* spdif */
668 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
669 "i2s3", "i2s4", "dam0", "dam1", "dam2",
670 "spdif";
034d023f
SW		 671 dmas = <&apbdma 1>, <&apbdma 1>,
672 <&apbdma 2>, <&apbdma 2>,
673 <&apbdma 3>, <&apbdma 3>,
674 <&apbdma 4>, <&apbdma 4>;
675 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
676 "rx3", "tx3";
9ee6a5c4
SW		 677 ranges;
678 #address-cells = <1>;
679 #size-cells = <1>;
680
681 tegra_i2s0: i2s@70080300 {
682 compatible = "nvidia,tegra30-i2s";
683 reg = <0x70080300 0x100>;
684 nvidia,ahub-cif-ids = <4 4>;
05849c93 685 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 686 resets = <&tegra_car 30>;
687 reset-names = "i2s";
223ef78d 688 status = "disabled";
9ee6a5c4
SW		 689 };
690
691 tegra_i2s1: i2s@70080400 {
692 compatible = "nvidia,tegra30-i2s";
693 reg = <0x70080400 0x100>;
694 nvidia,ahub-cif-ids = <5 5>;
05849c93 695 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 696 resets = <&tegra_car 11>;
697 reset-names = "i2s";
223ef78d 698 status = "disabled";
9ee6a5c4
SW		 699 };
700
701 tegra_i2s2: i2s@70080500 {
702 compatible = "nvidia,tegra30-i2s";
703 reg = <0x70080500 0x100>;
704 nvidia,ahub-cif-ids = <6 6>;
05849c93 705 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 706 resets = <&tegra_car 18>;
707 reset-names = "i2s";
223ef78d 708 status = "disabled";
9ee6a5c4
SW		 709 };
710
711 tegra_i2s3: i2s@70080600 {
712 compatible = "nvidia,tegra30-i2s";
713 reg = <0x70080600 0x100>;
714 nvidia,ahub-cif-ids = <7 7>;
05849c93 715 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 716 resets = <&tegra_car 101>;
717 reset-names = "i2s";
223ef78d 718 status = "disabled";
9ee6a5c4
SW		 719 };
720
721 tegra_i2s4: i2s@70080700 {
722 compatible = "nvidia,tegra30-i2s";
723 reg = <0x70080700 0x100>;
724 nvidia,ahub-cif-ids = <8 8>;
05849c93 725 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 726 resets = <&tegra_car 102>;
727 reset-names = "i2s";
223ef78d 728 status = "disabled";
9ee6a5c4
SW		 729 };
730 };
7868a9bc 731
c04abb3a
SW		 732 sdhci@78000000 {
733 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
734 reg = <0x78000000 0x200>;
6cecf916 735 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 736 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 737 resets = <&tegra_car 14>;
738 reset-names = "sdhci";
223ef78d 739 status = "disabled";
7868a9bc 740 };
ecf43742 741
c04abb3a
SW		 742 sdhci@78000200 {
743 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
744 reg = <0x78000200 0x200>;
6cecf916 745 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 746 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 747 resets = <&tegra_car 9>;
748 reset-names = "sdhci";
223ef78d 749 status = "disabled";
ecf43742 750 };
54174a33 751
c04abb3a
SW		 752 sdhci@78000400 {
753 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
754 reg = <0x78000400 0x200>;
6cecf916 755 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 756 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 757 resets = <&tegra_car 69>;
758 reset-names = "sdhci";
223ef78d 759 status = "disabled";
c04abb3a
SW		 760 };
761
762 sdhci@78000600 {
763 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
764 reg = <0x78000600 0x200>;
6cecf916 765 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 766 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 767 resets = <&tegra_car 15>;
768 reset-names = "sdhci";
223ef78d 769 status = "disabled";
c04abb3a
SW		 770 };
771
cc34c9f7
TT		 772 usb@7d000000 {
773 compatible = "nvidia,tegra30-ehci", "usb-ehci";
774 reg = <0x7d000000 0x4000>;
775 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
776 phy_type = "utmi";
777 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 778 resets = <&tegra_car 22>;
779 reset-names = "usb";
cc34c9f7
TT		 780 nvidia,needs-double-reset;
781 nvidia,phy = <&phy1>;
782 status = "disabled";
783 };
784
785 phy1: usb-phy@7d000000 {
786 compatible = "nvidia,tegra30-usb-phy";
787 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
788 phy_type = "utmi";
789 clocks = <&tegra_car TEGRA30_CLK_USBD>,
790 <&tegra_car TEGRA30_CLK_PLL_U>,
791 <&tegra_car TEGRA30_CLK_USBD>;
792 clock-names = "reg", "pll_u", "utmi-pads";
793 nvidia,hssync-start-delay = <9>;
794 nvidia,idle-wait-delay = <17>;
795 nvidia,elastic-limit = <16>;
796 nvidia,term-range-adj = <6>;
797 nvidia,xcvr-setup = <51>;
798 nvidia.xcvr-setup-use-fuses;
799 nvidia,xcvr-lsfslew = <1>;
800 nvidia,xcvr-lsrslew = <1>;
801 nvidia,xcvr-hsslew = <32>;
802 nvidia,hssquelch-level = <2>;
803 nvidia,hsdiscon-level = <5>;
804 status = "disabled";
805 };
806
807 usb@7d004000 {
808 compatible = "nvidia,tegra30-ehci", "usb-ehci";
809 reg = <0x7d004000 0x4000>;
810 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
811 phy_type = "ulpi";
812 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 813 resets = <&tegra_car 58>;
814 reset-names = "usb";
cc34c9f7
TT		 815 nvidia,phy = <&phy2>;
816 status = "disabled";
817 };
818
819 phy2: usb-phy@7d004000 {
820 compatible = "nvidia,tegra30-usb-phy";
821 reg = <0x7d004000 0x4000>;
822 phy_type = "ulpi";
823 clocks = <&tegra_car TEGRA30_CLK_USB2>,
824 <&tegra_car TEGRA30_CLK_PLL_U>,
825 <&tegra_car TEGRA30_CLK_CDEV2>;
826 clock-names = "reg", "pll_u", "ulpi-link";
827 status = "disabled";
828 };
829
830 usb@7d008000 {
831 compatible = "nvidia,tegra30-ehci", "usb-ehci";
832 reg = <0x7d008000 0x4000>;
833 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
834 phy_type = "utmi";
835 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 836 resets = <&tegra_car 59>;
837 reset-names = "usb";
cc34c9f7
TT		 838 nvidia,phy = <&phy3>;
839 status = "disabled";
840 };
841
842 phy3: usb-phy@7d008000 {
843 compatible = "nvidia,tegra30-usb-phy";
844 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
845 phy_type = "utmi";
846 clocks = <&tegra_car TEGRA30_CLK_USB3>,
847 <&tegra_car TEGRA30_CLK_PLL_U>,
848 <&tegra_car TEGRA30_CLK_USBD>;
849 clock-names = "reg", "pll_u", "utmi-pads";
850 nvidia,hssync-start-delay = <0>;
851 nvidia,idle-wait-delay = <17>;
852 nvidia,elastic-limit = <16>;
853 nvidia,term-range-adj = <6>;
854 nvidia,xcvr-setup = <51>;
855 nvidia.xcvr-setup-use-fuses;
856 nvidia,xcvr-lsfslew = <2>;
857 nvidia,xcvr-lsrslew = <2>;
858 nvidia,xcvr-hsslew = <32>;
859 nvidia,hssquelch-level = <2>;
860 nvidia,hsdiscon-level = <5>;
861 status = "disabled";
862 };
863
7d19a34a
HD		 864 cpus {
865 #address-cells = <1>;
866 #size-cells = <0>;
867
868 cpu@0 {
869 device_type = "cpu";
870 compatible = "arm,cortex-a9";
871 reg = <0>;
872 };
873
874 cpu@1 {
875 device_type = "cpu";
876 compatible = "arm,cortex-a9";
877 reg = <1>;
878 };
879
880 cpu@2 {
881 device_type = "cpu";
882 compatible = "arm,cortex-a9";
883 reg = <2>;
884 };
885
886 cpu@3 {
887 device_type = "cpu";
888 compatible = "arm,cortex-a9";
889 reg = <3>;
890 };
891 };
892
c04abb3a
SW		 893 pmu {
894 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 895 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 899 };
c3e00a0e 900};
Ubuntu Eoan Linux kernel mirror