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Commit | Line | Data |
---|---|---|
c3e00a0e PDS |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
4 | compatible = "nvidia,tegra30"; | |
5 | interrupt-parent = <&intc>; | |
6 | ||
b6551bb9 LD |
7 | aliases { |
8 | serial0 = &uarta; | |
9 | serial1 = &uartb; | |
10 | serial2 = &uartc; | |
11 | serial3 = &uartd; | |
12 | serial4 = &uarte; | |
13 | }; | |
14 | ||
ed39097c TR |
15 | host1x { |
16 | compatible = "nvidia,tegra30-host1x", "simple-bus"; | |
17 | reg = <0x50000000 0x00024000>; | |
18 | interrupts = <0 65 0x04 /* mpcore syncpt */ | |
19 | 0 67 0x04>; /* mpcore general */ | |
1cbc733d | 20 | clocks = <&tegra_car 28>; |
ed39097c TR |
21 | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
25 | ranges = <0x54000000 0x54000000 0x04000000>; | |
26 | ||
27 | mpe { | |
28 | compatible = "nvidia,tegra30-mpe"; | |
29 | reg = <0x54040000 0x00040000>; | |
30 | interrupts = <0 68 0x04>; | |
1cbc733d | 31 | clocks = <&tegra_car 60>; |
ed39097c TR |
32 | }; |
33 | ||
34 | vi { | |
35 | compatible = "nvidia,tegra30-vi"; | |
36 | reg = <0x54080000 0x00040000>; | |
37 | interrupts = <0 69 0x04>; | |
1cbc733d | 38 | clocks = <&tegra_car 164>; |
ed39097c TR |
39 | }; |
40 | ||
41 | epp { | |
42 | compatible = "nvidia,tegra30-epp"; | |
43 | reg = <0x540c0000 0x00040000>; | |
44 | interrupts = <0 70 0x04>; | |
1cbc733d | 45 | clocks = <&tegra_car 19>; |
ed39097c TR |
46 | }; |
47 | ||
48 | isp { | |
49 | compatible = "nvidia,tegra30-isp"; | |
50 | reg = <0x54100000 0x00040000>; | |
51 | interrupts = <0 71 0x04>; | |
1cbc733d | 52 | clocks = <&tegra_car 23>; |
ed39097c TR |
53 | }; |
54 | ||
55 | gr2d { | |
56 | compatible = "nvidia,tegra30-gr2d"; | |
57 | reg = <0x54140000 0x00040000>; | |
58 | interrupts = <0 72 0x04>; | |
1cbc733d | 59 | clocks = <&tegra_car 21>; |
ed39097c TR |
60 | }; |
61 | ||
62 | gr3d { | |
63 | compatible = "nvidia,tegra30-gr3d"; | |
64 | reg = <0x54180000 0x00040000>; | |
1cbc733d PG |
65 | clocks = <&tegra_car 24 &tegra_car 98>; |
66 | clock-names = "3d", "3d2"; | |
ed39097c TR |
67 | }; |
68 | ||
69 | dc@54200000 { | |
70 | compatible = "nvidia,tegra30-dc"; | |
71 | reg = <0x54200000 0x00040000>; | |
72 | interrupts = <0 73 0x04>; | |
1cbc733d PG |
73 | clocks = <&tegra_car 27>, <&tegra_car 179>; |
74 | clock-names = "disp1", "parent"; | |
ed39097c TR |
75 | |
76 | rgb { | |
77 | status = "disabled"; | |
78 | }; | |
79 | }; | |
80 | ||
81 | dc@54240000 { | |
82 | compatible = "nvidia,tegra30-dc"; | |
83 | reg = <0x54240000 0x00040000>; | |
84 | interrupts = <0 74 0x04>; | |
1cbc733d PG |
85 | clocks = <&tegra_car 26>, <&tegra_car 179>; |
86 | clock-names = "disp2", "parent"; | |
ed39097c TR |
87 | |
88 | rgb { | |
89 | status = "disabled"; | |
90 | }; | |
91 | }; | |
92 | ||
93 | hdmi { | |
94 | compatible = "nvidia,tegra30-hdmi"; | |
95 | reg = <0x54280000 0x00040000>; | |
96 | interrupts = <0 75 0x04>; | |
1cbc733d PG |
97 | clocks = <&tegra_car 51>, <&tegra_car 189>; |
98 | clock-names = "hdmi", "parent"; | |
ed39097c TR |
99 | status = "disabled"; |
100 | }; | |
101 | ||
102 | tvo { | |
103 | compatible = "nvidia,tegra30-tvo"; | |
104 | reg = <0x542c0000 0x00040000>; | |
105 | interrupts = <0 76 0x04>; | |
1cbc733d | 106 | clocks = <&tegra_car 169>; |
ed39097c TR |
107 | status = "disabled"; |
108 | }; | |
109 | ||
110 | dsi { | |
111 | compatible = "nvidia,tegra30-dsi"; | |
112 | reg = <0x54300000 0x00040000>; | |
1cbc733d | 113 | clocks = <&tegra_car 48>; |
ed39097c TR |
114 | status = "disabled"; |
115 | }; | |
116 | }; | |
117 | ||
73368ba0 SW |
118 | timer@50004600 { |
119 | compatible = "arm,cortex-a9-twd-timer"; | |
120 | reg = <0x50040600 0x20>; | |
121 | interrupts = <1 13 0xf04>; | |
ed3ced37 | 122 | clocks = <&tegra_car 214>; |
73368ba0 SW |
123 | }; |
124 | ||
f9eb26a4 | 125 | intc: interrupt-controller { |
c3e00a0e | 126 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
127 | reg = <0x50041000 0x1000 |
128 | 0x50040100 0x0100>; | |
2eaab06e SW |
129 | interrupt-controller; |
130 | #interrupt-cells = <3>; | |
c3e00a0e PDS |
131 | }; |
132 | ||
bb2c1de9 SW |
133 | cache-controller { |
134 | compatible = "arm,pl310-cache"; | |
135 | reg = <0x50043000 0x1000>; | |
136 | arm,data-latency = <6 6 2>; | |
137 | arm,tag-latency = <5 5 2>; | |
138 | cache-unified; | |
139 | cache-level = <2>; | |
140 | }; | |
141 | ||
2f2b7fb2 SW |
142 | timer@60005000 { |
143 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
144 | reg = <0x60005000 0x400>; | |
145 | interrupts = <0 0 0x04 | |
146 | 0 1 0x04 | |
147 | 0 41 0x04 | |
148 | 0 42 0x04 | |
149 | 0 121 0x04 | |
150 | 0 122 0x04>; | |
151 | }; | |
152 | ||
95985667 PG |
153 | tegra_car: clock { |
154 | compatible = "nvidia,tegra30-car"; | |
155 | reg = <0x60006000 0x1000>; | |
156 | #clock-cells = <1>; | |
157 | }; | |
158 | ||
f9eb26a4 | 159 | apbdma: dma { |
8051b75a SW |
160 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
161 | reg = <0x6000a000 0x1400>; | |
95decf84 SW |
162 | interrupts = <0 104 0x04 |
163 | 0 105 0x04 | |
164 | 0 106 0x04 | |
165 | 0 107 0x04 | |
166 | 0 108 0x04 | |
167 | 0 109 0x04 | |
168 | 0 110 0x04 | |
169 | 0 111 0x04 | |
170 | 0 112 0x04 | |
171 | 0 113 0x04 | |
172 | 0 114 0x04 | |
173 | 0 115 0x04 | |
174 | 0 116 0x04 | |
175 | 0 117 0x04 | |
176 | 0 118 0x04 | |
177 | 0 119 0x04 | |
178 | 0 128 0x04 | |
179 | 0 129 0x04 | |
180 | 0 130 0x04 | |
181 | 0 131 0x04 | |
182 | 0 132 0x04 | |
183 | 0 133 0x04 | |
184 | 0 134 0x04 | |
185 | 0 135 0x04 | |
186 | 0 136 0x04 | |
187 | 0 137 0x04 | |
188 | 0 138 0x04 | |
189 | 0 139 0x04 | |
190 | 0 140 0x04 | |
191 | 0 141 0x04 | |
192 | 0 142 0x04 | |
193 | 0 143 0x04>; | |
1cbc733d | 194 | clocks = <&tegra_car 34>; |
8051b75a SW |
195 | }; |
196 | ||
c04abb3a SW |
197 | ahb: ahb { |
198 | compatible = "nvidia,tegra30-ahb"; | |
199 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ | |
c3e00a0e PDS |
200 | }; |
201 | ||
f9eb26a4 | 202 | gpio: gpio { |
35f210ec | 203 | compatible = "nvidia,tegra30-gpio"; |
95decf84 SW |
204 | reg = <0x6000d000 0x1000>; |
205 | interrupts = <0 32 0x04 | |
206 | 0 33 0x04 | |
207 | 0 34 0x04 | |
208 | 0 35 0x04 | |
209 | 0 55 0x04 | |
210 | 0 87 0x04 | |
211 | 0 89 0x04 | |
212 | 0 125 0x04>; | |
c3e00a0e PDS |
213 | #gpio-cells = <2>; |
214 | gpio-controller; | |
6f74dc9b SW |
215 | #interrupt-cells = <2>; |
216 | interrupt-controller; | |
c3e00a0e PDS |
217 | }; |
218 | ||
c04abb3a SW |
219 | pinmux: pinmux { |
220 | compatible = "nvidia,tegra30-pinmux"; | |
322337b8 PR |
221 | reg = <0x70000868 0xd4 /* Pad control registers */ |
222 | 0x70003000 0x3e4>; /* Mux registers */ | |
c04abb3a SW |
223 | }; |
224 | ||
b6551bb9 LD |
225 | /* |
226 | * There are two serial driver i.e. 8250 based simple serial | |
227 | * driver and APB DMA based serial driver for higher baudrate | |
228 | * and performace. To enable the 8250 based driver, the compatible | |
229 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable | |
230 | * the APB DMA based serial driver, the comptible is | |
231 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". | |
232 | */ | |
233 | uarta: serial@70006000 { | |
c3e00a0e PDS |
234 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
235 | reg = <0x70006000 0x40>; | |
236 | reg-shift = <2>; | |
95decf84 | 237 | interrupts = <0 36 0x04>; |
b6551bb9 | 238 | nvidia,dma-request-selector = <&apbdma 8>; |
1cbc733d | 239 | clocks = <&tegra_car 6>; |
223ef78d | 240 | status = "disabled"; |
c3e00a0e PDS |
241 | }; |
242 | ||
b6551bb9 | 243 | uartb: serial@70006040 { |
c3e00a0e PDS |
244 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
245 | reg = <0x70006040 0x40>; | |
246 | reg-shift = <2>; | |
95decf84 | 247 | interrupts = <0 37 0x04>; |
b6551bb9 | 248 | nvidia,dma-request-selector = <&apbdma 9>; |
1cbc733d | 249 | clocks = <&tegra_car 160>; |
223ef78d | 250 | status = "disabled"; |
c3e00a0e PDS |
251 | }; |
252 | ||
b6551bb9 | 253 | uartc: serial@70006200 { |
c3e00a0e PDS |
254 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
255 | reg = <0x70006200 0x100>; | |
256 | reg-shift = <2>; | |
95decf84 | 257 | interrupts = <0 46 0x04>; |
b6551bb9 | 258 | nvidia,dma-request-selector = <&apbdma 10>; |
1cbc733d | 259 | clocks = <&tegra_car 55>; |
223ef78d | 260 | status = "disabled"; |
c3e00a0e PDS |
261 | }; |
262 | ||
b6551bb9 | 263 | uartd: serial@70006300 { |
c3e00a0e PDS |
264 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
265 | reg = <0x70006300 0x100>; | |
266 | reg-shift = <2>; | |
95decf84 | 267 | interrupts = <0 90 0x04>; |
b6551bb9 | 268 | nvidia,dma-request-selector = <&apbdma 19>; |
1cbc733d | 269 | clocks = <&tegra_car 65>; |
223ef78d | 270 | status = "disabled"; |
c3e00a0e PDS |
271 | }; |
272 | ||
b6551bb9 | 273 | uarte: serial@70006400 { |
c3e00a0e PDS |
274 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
275 | reg = <0x70006400 0x100>; | |
276 | reg-shift = <2>; | |
95decf84 | 277 | interrupts = <0 91 0x04>; |
b6551bb9 | 278 | nvidia,dma-request-selector = <&apbdma 20>; |
1cbc733d | 279 | clocks = <&tegra_car 66>; |
223ef78d | 280 | status = "disabled"; |
c3e00a0e PDS |
281 | }; |
282 | ||
2b8b15da | 283 | pwm: pwm { |
140fd977 TR |
284 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
285 | reg = <0x7000a000 0x100>; | |
286 | #pwm-cells = <2>; | |
1cbc733d | 287 | clocks = <&tegra_car 17>; |
140fd977 TR |
288 | }; |
289 | ||
380e04ac SW |
290 | rtc { |
291 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | |
292 | reg = <0x7000e000 0x100>; | |
293 | interrupts = <0 2 0x04>; | |
294 | }; | |
295 | ||
c04abb3a | 296 | i2c@7000c000 { |
c04abb3a SW |
297 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
298 | reg = <0x7000c000 0x100>; | |
299 | interrupts = <0 38 0x04>; | |
2eaab06e SW |
300 | #address-cells = <1>; |
301 | #size-cells = <0>; | |
1cbc733d PG |
302 | clocks = <&tegra_car 12>, <&tegra_car 182>; |
303 | clock-names = "div-clk", "fast-clk"; | |
223ef78d | 304 | status = "disabled"; |
c3e00a0e PDS |
305 | }; |
306 | ||
c04abb3a | 307 | i2c@7000c400 { |
c04abb3a SW |
308 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
309 | reg = <0x7000c400 0x100>; | |
310 | interrupts = <0 84 0x04>; | |
2eaab06e SW |
311 | #address-cells = <1>; |
312 | #size-cells = <0>; | |
1cbc733d PG |
313 | clocks = <&tegra_car 54>, <&tegra_car 182>; |
314 | clock-names = "div-clk", "fast-clk"; | |
223ef78d | 315 | status = "disabled"; |
c3e00a0e PDS |
316 | }; |
317 | ||
c04abb3a | 318 | i2c@7000c500 { |
c04abb3a SW |
319 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
320 | reg = <0x7000c500 0x100>; | |
321 | interrupts = <0 92 0x04>; | |
2eaab06e SW |
322 | #address-cells = <1>; |
323 | #size-cells = <0>; | |
1cbc733d PG |
324 | clocks = <&tegra_car 67>, <&tegra_car 182>; |
325 | clock-names = "div-clk", "fast-clk"; | |
223ef78d | 326 | status = "disabled"; |
c3e00a0e PDS |
327 | }; |
328 | ||
c04abb3a | 329 | i2c@7000c700 { |
c04abb3a SW |
330 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
331 | reg = <0x7000c700 0x100>; | |
332 | interrupts = <0 120 0x04>; | |
2eaab06e SW |
333 | #address-cells = <1>; |
334 | #size-cells = <0>; | |
1cbc733d PG |
335 | clocks = <&tegra_car 103>, <&tegra_car 182>; |
336 | clock-names = "div-clk", "fast-clk"; | |
223ef78d | 337 | status = "disabled"; |
c3e00a0e PDS |
338 | }; |
339 | ||
c04abb3a | 340 | i2c@7000d000 { |
c04abb3a SW |
341 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
342 | reg = <0x7000d000 0x100>; | |
343 | interrupts = <0 53 0x04>; | |
2eaab06e SW |
344 | #address-cells = <1>; |
345 | #size-cells = <0>; | |
1cbc733d PG |
346 | clocks = <&tegra_car 47>, <&tegra_car 182>; |
347 | clock-names = "div-clk", "fast-clk"; | |
223ef78d | 348 | status = "disabled"; |
c04abb3a SW |
349 | }; |
350 | ||
a86b0db3 LD |
351 | spi@7000d400 { |
352 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
353 | reg = <0x7000d400 0x200>; | |
354 | interrupts = <0 59 0x04>; | |
355 | nvidia,dma-request-selector = <&apbdma 15>; | |
356 | #address-cells = <1>; | |
357 | #size-cells = <0>; | |
1cbc733d | 358 | clocks = <&tegra_car 41>; |
a86b0db3 LD |
359 | status = "disabled"; |
360 | }; | |
361 | ||
362 | spi@7000d600 { | |
363 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
364 | reg = <0x7000d600 0x200>; | |
365 | interrupts = <0 82 0x04>; | |
366 | nvidia,dma-request-selector = <&apbdma 16>; | |
367 | #address-cells = <1>; | |
368 | #size-cells = <0>; | |
1cbc733d | 369 | clocks = <&tegra_car 44>; |
a86b0db3 LD |
370 | status = "disabled"; |
371 | }; | |
372 | ||
373 | spi@7000d800 { | |
374 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
375 | reg = <0x7000d480 0x200>; | |
376 | interrupts = <0 83 0x04>; | |
377 | nvidia,dma-request-selector = <&apbdma 17>; | |
378 | #address-cells = <1>; | |
379 | #size-cells = <0>; | |
1cbc733d | 380 | clocks = <&tegra_car 46>; |
a86b0db3 LD |
381 | status = "disabled"; |
382 | }; | |
383 | ||
384 | spi@7000da00 { | |
385 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
386 | reg = <0x7000da00 0x200>; | |
387 | interrupts = <0 93 0x04>; | |
388 | nvidia,dma-request-selector = <&apbdma 18>; | |
389 | #address-cells = <1>; | |
390 | #size-cells = <0>; | |
1cbc733d | 391 | clocks = <&tegra_car 68>; |
a86b0db3 LD |
392 | status = "disabled"; |
393 | }; | |
394 | ||
395 | spi@7000dc00 { | |
396 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
397 | reg = <0x7000dc00 0x200>; | |
398 | interrupts = <0 94 0x04>; | |
399 | nvidia,dma-request-selector = <&apbdma 27>; | |
400 | #address-cells = <1>; | |
401 | #size-cells = <0>; | |
1cbc733d | 402 | clocks = <&tegra_car 104>; |
a86b0db3 LD |
403 | status = "disabled"; |
404 | }; | |
405 | ||
406 | spi@7000de00 { | |
407 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
408 | reg = <0x7000de00 0x200>; | |
409 | interrupts = <0 79 0x04>; | |
410 | nvidia,dma-request-selector = <&apbdma 28>; | |
411 | #address-cells = <1>; | |
412 | #size-cells = <0>; | |
1cbc733d | 413 | clocks = <&tegra_car 105>; |
a86b0db3 LD |
414 | status = "disabled"; |
415 | }; | |
416 | ||
699ed4b9 LD |
417 | kbc { |
418 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; | |
419 | reg = <0x7000e200 0x100>; | |
420 | interrupts = <0 85 0x04>; | |
421 | clocks = <&tegra_car 36>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
c04abb3a SW |
425 | pmc { |
426 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | |
427 | reg = <0x7000e400 0x400>; | |
428 | }; | |
429 | ||
a9140aa5 | 430 | memory-controller { |
c04abb3a SW |
431 | compatible = "nvidia,tegra30-mc"; |
432 | reg = <0x7000f000 0x010 | |
433 | 0x7000f03c 0x1b4 | |
434 | 0x7000f200 0x028 | |
435 | 0x7000f284 0x17c>; | |
436 | interrupts = <0 77 0x04>; | |
437 | }; | |
438 | ||
3fbf07d8 | 439 | iommu { |
c04abb3a SW |
440 | compatible = "nvidia,tegra30-smmu"; |
441 | reg = <0x7000f010 0x02c | |
442 | 0x7000f1f0 0x010 | |
443 | 0x7000f228 0x05c>; | |
444 | nvidia,#asids = <4>; /* # of ASIDs */ | |
445 | dma-window = <0 0x40000000>; /* IOVA start & length */ | |
446 | nvidia,ahb = <&ahb>; | |
c3e00a0e | 447 | }; |
9ee6a5c4 SW |
448 | |
449 | ahub { | |
450 | compatible = "nvidia,tegra30-ahub"; | |
5ff48887 SW |
451 | reg = <0x70080000 0x200 |
452 | 0x70080200 0x100>; | |
95decf84 | 453 | interrupts = <0 103 0x04>; |
9ee6a5c4 | 454 | nvidia,dma-request-selector = <&apbdma 1>; |
1cbc733d PG |
455 | clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, |
456 | <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, | |
457 | <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, | |
458 | <&tegra_car 110>, <&tegra_car 162>; | |
459 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
460 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
461 | "spdif_in"; | |
9ee6a5c4 SW |
462 | ranges; |
463 | #address-cells = <1>; | |
464 | #size-cells = <1>; | |
465 | ||
466 | tegra_i2s0: i2s@70080300 { | |
467 | compatible = "nvidia,tegra30-i2s"; | |
468 | reg = <0x70080300 0x100>; | |
469 | nvidia,ahub-cif-ids = <4 4>; | |
1cbc733d | 470 | clocks = <&tegra_car 30>; |
223ef78d | 471 | status = "disabled"; |
9ee6a5c4 SW |
472 | }; |
473 | ||
474 | tegra_i2s1: i2s@70080400 { | |
475 | compatible = "nvidia,tegra30-i2s"; | |
476 | reg = <0x70080400 0x100>; | |
477 | nvidia,ahub-cif-ids = <5 5>; | |
1cbc733d | 478 | clocks = <&tegra_car 11>; |
223ef78d | 479 | status = "disabled"; |
9ee6a5c4 SW |
480 | }; |
481 | ||
482 | tegra_i2s2: i2s@70080500 { | |
483 | compatible = "nvidia,tegra30-i2s"; | |
484 | reg = <0x70080500 0x100>; | |
485 | nvidia,ahub-cif-ids = <6 6>; | |
1cbc733d | 486 | clocks = <&tegra_car 18>; |
223ef78d | 487 | status = "disabled"; |
9ee6a5c4 SW |
488 | }; |
489 | ||
490 | tegra_i2s3: i2s@70080600 { | |
491 | compatible = "nvidia,tegra30-i2s"; | |
492 | reg = <0x70080600 0x100>; | |
493 | nvidia,ahub-cif-ids = <7 7>; | |
1cbc733d | 494 | clocks = <&tegra_car 101>; |
223ef78d | 495 | status = "disabled"; |
9ee6a5c4 SW |
496 | }; |
497 | ||
498 | tegra_i2s4: i2s@70080700 { | |
499 | compatible = "nvidia,tegra30-i2s"; | |
500 | reg = <0x70080700 0x100>; | |
501 | nvidia,ahub-cif-ids = <8 8>; | |
1cbc733d | 502 | clocks = <&tegra_car 102>; |
223ef78d | 503 | status = "disabled"; |
9ee6a5c4 SW |
504 | }; |
505 | }; | |
7868a9bc | 506 | |
c04abb3a SW |
507 | sdhci@78000000 { |
508 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
509 | reg = <0x78000000 0x200>; | |
510 | interrupts = <0 14 0x04>; | |
1cbc733d | 511 | clocks = <&tegra_car 14>; |
223ef78d | 512 | status = "disabled"; |
7868a9bc | 513 | }; |
ecf43742 | 514 | |
c04abb3a SW |
515 | sdhci@78000200 { |
516 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
517 | reg = <0x78000200 0x200>; | |
518 | interrupts = <0 15 0x04>; | |
1cbc733d | 519 | clocks = <&tegra_car 9>; |
223ef78d | 520 | status = "disabled"; |
ecf43742 | 521 | }; |
54174a33 | 522 | |
c04abb3a SW |
523 | sdhci@78000400 { |
524 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
525 | reg = <0x78000400 0x200>; | |
526 | interrupts = <0 19 0x04>; | |
1cbc733d | 527 | clocks = <&tegra_car 69>; |
223ef78d | 528 | status = "disabled"; |
c04abb3a SW |
529 | }; |
530 | ||
531 | sdhci@78000600 { | |
532 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
533 | reg = <0x78000600 0x200>; | |
534 | interrupts = <0 31 0x04>; | |
1cbc733d | 535 | clocks = <&tegra_car 15>; |
223ef78d | 536 | status = "disabled"; |
c04abb3a SW |
537 | }; |
538 | ||
7d19a34a HD |
539 | cpus { |
540 | #address-cells = <1>; | |
541 | #size-cells = <0>; | |
542 | ||
543 | cpu@0 { | |
544 | device_type = "cpu"; | |
545 | compatible = "arm,cortex-a9"; | |
546 | reg = <0>; | |
547 | }; | |
548 | ||
549 | cpu@1 { | |
550 | device_type = "cpu"; | |
551 | compatible = "arm,cortex-a9"; | |
552 | reg = <1>; | |
553 | }; | |
554 | ||
555 | cpu@2 { | |
556 | device_type = "cpu"; | |
557 | compatible = "arm,cortex-a9"; | |
558 | reg = <2>; | |
559 | }; | |
560 | ||
561 | cpu@3 { | |
562 | device_type = "cpu"; | |
563 | compatible = "arm,cortex-a9"; | |
564 | reg = <3>; | |
565 | }; | |
566 | }; | |
567 | ||
c04abb3a SW |
568 | pmu { |
569 | compatible = "arm,cortex-a9-pmu"; | |
570 | interrupts = <0 144 0x04 | |
571 | 0 145 0x04 | |
572 | 0 146 0x04 | |
573 | 0 147 0x04>; | |
54174a33 | 574 | }; |
c3e00a0e | 575 | }; |