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Commit | Line | Data |
---|---|---|
c3e00a0e PDS |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
4 | compatible = "nvidia,tegra30"; | |
5 | interrupt-parent = <&intc>; | |
6 | ||
5ab134ad JL |
7 | cache-controller@50043000 { |
8 | compatible = "arm,pl310-cache"; | |
9 | reg = <0x50043000 0x1000>; | |
10 | arm,data-latency = <6 6 2>; | |
11 | arm,tag-latency = <5 5 2>; | |
12 | cache-unified; | |
13 | cache-level = <2>; | |
14 | }; | |
15 | ||
f9eb26a4 | 16 | intc: interrupt-controller { |
c3e00a0e | 17 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
18 | reg = <0x50041000 0x1000 |
19 | 0x50040100 0x0100>; | |
2eaab06e SW |
20 | interrupt-controller; |
21 | #interrupt-cells = <3>; | |
c3e00a0e PDS |
22 | }; |
23 | ||
f9eb26a4 | 24 | apbdma: dma { |
8051b75a SW |
25 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
26 | reg = <0x6000a000 0x1400>; | |
95decf84 SW |
27 | interrupts = <0 104 0x04 |
28 | 0 105 0x04 | |
29 | 0 106 0x04 | |
30 | 0 107 0x04 | |
31 | 0 108 0x04 | |
32 | 0 109 0x04 | |
33 | 0 110 0x04 | |
34 | 0 111 0x04 | |
35 | 0 112 0x04 | |
36 | 0 113 0x04 | |
37 | 0 114 0x04 | |
38 | 0 115 0x04 | |
39 | 0 116 0x04 | |
40 | 0 117 0x04 | |
41 | 0 118 0x04 | |
42 | 0 119 0x04 | |
43 | 0 128 0x04 | |
44 | 0 129 0x04 | |
45 | 0 130 0x04 | |
46 | 0 131 0x04 | |
47 | 0 132 0x04 | |
48 | 0 133 0x04 | |
49 | 0 134 0x04 | |
50 | 0 135 0x04 | |
51 | 0 136 0x04 | |
52 | 0 137 0x04 | |
53 | 0 138 0x04 | |
54 | 0 139 0x04 | |
55 | 0 140 0x04 | |
56 | 0 141 0x04 | |
57 | 0 142 0x04 | |
58 | 0 143 0x04>; | |
8051b75a SW |
59 | }; |
60 | ||
c04abb3a SW |
61 | ahb: ahb { |
62 | compatible = "nvidia,tegra30-ahb"; | |
63 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ | |
c3e00a0e PDS |
64 | }; |
65 | ||
f9eb26a4 | 66 | gpio: gpio { |
c3e00a0e | 67 | compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; |
95decf84 SW |
68 | reg = <0x6000d000 0x1000>; |
69 | interrupts = <0 32 0x04 | |
70 | 0 33 0x04 | |
71 | 0 34 0x04 | |
72 | 0 35 0x04 | |
73 | 0 55 0x04 | |
74 | 0 87 0x04 | |
75 | 0 89 0x04 | |
76 | 0 125 0x04>; | |
c3e00a0e PDS |
77 | #gpio-cells = <2>; |
78 | gpio-controller; | |
6f74dc9b SW |
79 | #interrupt-cells = <2>; |
80 | interrupt-controller; | |
c3e00a0e PDS |
81 | }; |
82 | ||
c04abb3a SW |
83 | pinmux: pinmux { |
84 | compatible = "nvidia,tegra30-pinmux"; | |
85 | reg = <0x70000868 0xd0 /* Pad control registers */ | |
86 | 0x70003000 0x3e0>; /* Mux registers */ | |
87 | }; | |
88 | ||
c3e00a0e PDS |
89 | serial@70006000 { |
90 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
91 | reg = <0x70006000 0x40>; | |
92 | reg-shift = <2>; | |
95decf84 | 93 | interrupts = <0 36 0x04>; |
223ef78d | 94 | status = "disabled"; |
c3e00a0e PDS |
95 | }; |
96 | ||
97 | serial@70006040 { | |
98 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
99 | reg = <0x70006040 0x40>; | |
100 | reg-shift = <2>; | |
95decf84 | 101 | interrupts = <0 37 0x04>; |
223ef78d | 102 | status = "disabled"; |
c3e00a0e PDS |
103 | }; |
104 | ||
105 | serial@70006200 { | |
106 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
107 | reg = <0x70006200 0x100>; | |
108 | reg-shift = <2>; | |
95decf84 | 109 | interrupts = <0 46 0x04>; |
223ef78d | 110 | status = "disabled"; |
c3e00a0e PDS |
111 | }; |
112 | ||
113 | serial@70006300 { | |
114 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
115 | reg = <0x70006300 0x100>; | |
116 | reg-shift = <2>; | |
95decf84 | 117 | interrupts = <0 90 0x04>; |
223ef78d | 118 | status = "disabled"; |
c3e00a0e PDS |
119 | }; |
120 | ||
121 | serial@70006400 { | |
122 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
123 | reg = <0x70006400 0x100>; | |
124 | reg-shift = <2>; | |
95decf84 | 125 | interrupts = <0 91 0x04>; |
223ef78d | 126 | status = "disabled"; |
c3e00a0e PDS |
127 | }; |
128 | ||
2b8b15da | 129 | pwm: pwm { |
140fd977 TR |
130 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
131 | reg = <0x7000a000 0x100>; | |
132 | #pwm-cells = <2>; | |
133 | }; | |
134 | ||
c04abb3a | 135 | i2c@7000c000 { |
c04abb3a SW |
136 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
137 | reg = <0x7000c000 0x100>; | |
138 | interrupts = <0 38 0x04>; | |
2eaab06e SW |
139 | #address-cells = <1>; |
140 | #size-cells = <0>; | |
223ef78d | 141 | status = "disabled"; |
c3e00a0e PDS |
142 | }; |
143 | ||
c04abb3a | 144 | i2c@7000c400 { |
c04abb3a SW |
145 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
146 | reg = <0x7000c400 0x100>; | |
147 | interrupts = <0 84 0x04>; | |
2eaab06e SW |
148 | #address-cells = <1>; |
149 | #size-cells = <0>; | |
223ef78d | 150 | status = "disabled"; |
c3e00a0e PDS |
151 | }; |
152 | ||
c04abb3a | 153 | i2c@7000c500 { |
c04abb3a SW |
154 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
155 | reg = <0x7000c500 0x100>; | |
156 | interrupts = <0 92 0x04>; | |
2eaab06e SW |
157 | #address-cells = <1>; |
158 | #size-cells = <0>; | |
223ef78d | 159 | status = "disabled"; |
c3e00a0e PDS |
160 | }; |
161 | ||
c04abb3a | 162 | i2c@7000c700 { |
c04abb3a SW |
163 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
164 | reg = <0x7000c700 0x100>; | |
165 | interrupts = <0 120 0x04>; | |
2eaab06e SW |
166 | #address-cells = <1>; |
167 | #size-cells = <0>; | |
223ef78d | 168 | status = "disabled"; |
c3e00a0e PDS |
169 | }; |
170 | ||
c04abb3a | 171 | i2c@7000d000 { |
c04abb3a SW |
172 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
173 | reg = <0x7000d000 0x100>; | |
174 | interrupts = <0 53 0x04>; | |
2eaab06e SW |
175 | #address-cells = <1>; |
176 | #size-cells = <0>; | |
223ef78d | 177 | status = "disabled"; |
c04abb3a SW |
178 | }; |
179 | ||
180 | pmc { | |
181 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | |
182 | reg = <0x7000e400 0x400>; | |
183 | }; | |
184 | ||
a9140aa5 | 185 | memory-controller { |
c04abb3a SW |
186 | compatible = "nvidia,tegra30-mc"; |
187 | reg = <0x7000f000 0x010 | |
188 | 0x7000f03c 0x1b4 | |
189 | 0x7000f200 0x028 | |
190 | 0x7000f284 0x17c>; | |
191 | interrupts = <0 77 0x04>; | |
192 | }; | |
193 | ||
194 | smmu { | |
195 | compatible = "nvidia,tegra30-smmu"; | |
196 | reg = <0x7000f010 0x02c | |
197 | 0x7000f1f0 0x010 | |
198 | 0x7000f228 0x05c>; | |
199 | nvidia,#asids = <4>; /* # of ASIDs */ | |
200 | dma-window = <0 0x40000000>; /* IOVA start & length */ | |
201 | nvidia,ahb = <&ahb>; | |
c3e00a0e | 202 | }; |
9ee6a5c4 SW |
203 | |
204 | ahub { | |
205 | compatible = "nvidia,tegra30-ahub"; | |
5ff48887 SW |
206 | reg = <0x70080000 0x200 |
207 | 0x70080200 0x100>; | |
95decf84 | 208 | interrupts = <0 103 0x04>; |
9ee6a5c4 SW |
209 | nvidia,dma-request-selector = <&apbdma 1>; |
210 | ||
211 | ranges; | |
212 | #address-cells = <1>; | |
213 | #size-cells = <1>; | |
214 | ||
215 | tegra_i2s0: i2s@70080300 { | |
216 | compatible = "nvidia,tegra30-i2s"; | |
217 | reg = <0x70080300 0x100>; | |
218 | nvidia,ahub-cif-ids = <4 4>; | |
223ef78d | 219 | status = "disabled"; |
9ee6a5c4 SW |
220 | }; |
221 | ||
222 | tegra_i2s1: i2s@70080400 { | |
223 | compatible = "nvidia,tegra30-i2s"; | |
224 | reg = <0x70080400 0x100>; | |
225 | nvidia,ahub-cif-ids = <5 5>; | |
223ef78d | 226 | status = "disabled"; |
9ee6a5c4 SW |
227 | }; |
228 | ||
229 | tegra_i2s2: i2s@70080500 { | |
230 | compatible = "nvidia,tegra30-i2s"; | |
231 | reg = <0x70080500 0x100>; | |
232 | nvidia,ahub-cif-ids = <6 6>; | |
223ef78d | 233 | status = "disabled"; |
9ee6a5c4 SW |
234 | }; |
235 | ||
236 | tegra_i2s3: i2s@70080600 { | |
237 | compatible = "nvidia,tegra30-i2s"; | |
238 | reg = <0x70080600 0x100>; | |
239 | nvidia,ahub-cif-ids = <7 7>; | |
223ef78d | 240 | status = "disabled"; |
9ee6a5c4 SW |
241 | }; |
242 | ||
243 | tegra_i2s4: i2s@70080700 { | |
244 | compatible = "nvidia,tegra30-i2s"; | |
245 | reg = <0x70080700 0x100>; | |
246 | nvidia,ahub-cif-ids = <8 8>; | |
223ef78d | 247 | status = "disabled"; |
9ee6a5c4 SW |
248 | }; |
249 | }; | |
7868a9bc | 250 | |
c04abb3a SW |
251 | sdhci@78000000 { |
252 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
253 | reg = <0x78000000 0x200>; | |
254 | interrupts = <0 14 0x04>; | |
223ef78d | 255 | status = "disabled"; |
7868a9bc | 256 | }; |
ecf43742 | 257 | |
c04abb3a SW |
258 | sdhci@78000200 { |
259 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
260 | reg = <0x78000200 0x200>; | |
261 | interrupts = <0 15 0x04>; | |
223ef78d | 262 | status = "disabled"; |
ecf43742 | 263 | }; |
54174a33 | 264 | |
c04abb3a SW |
265 | sdhci@78000400 { |
266 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
267 | reg = <0x78000400 0x200>; | |
268 | interrupts = <0 19 0x04>; | |
223ef78d | 269 | status = "disabled"; |
c04abb3a SW |
270 | }; |
271 | ||
272 | sdhci@78000600 { | |
273 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
274 | reg = <0x78000600 0x200>; | |
275 | interrupts = <0 31 0x04>; | |
223ef78d | 276 | status = "disabled"; |
c04abb3a SW |
277 | }; |
278 | ||
279 | pmu { | |
280 | compatible = "arm,cortex-a9-pmu"; | |
281 | interrupts = <0 144 0x04 | |
282 | 0 145 0x04 | |
283 | 0 146 0x04 | |
284 | 0 147 0x04>; | |
54174a33 | 285 | }; |
c3e00a0e | 286 | }; |