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ARM: tegra: Enable HDMI support on Dalmore
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
a47c662a 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
c3e00a0e
PDS		 7
8/ {
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
11
b6551bb9
LD		 12 aliases {
13 serial0 = &uarta;
14 serial1 = &uartb;
15 serial2 = &uartc;
16 serial3 = &uartd;
17 serial4 = &uarte;
18 };
19
58ecb23f 20 pcie-controller@00003000 {
e07e3dbd
TR		 21 compatible = "nvidia,tegra30-pcie";
22 device_type = "pci";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
30
31 bus-range = <0x00 0xff>;
32 #address-cells = <3>;
33 #size-cells = <2>;
34
35 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
36 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
37 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
38 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 39 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
40 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 41
42 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
43 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 46 clock-names = "pex", "afi", "pll_e", "cml";
3393d422
SW		 47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 51 status = "disabled";
52
53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 status = "disabled";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61 ranges;
62
63 nvidia,num-lanes = <2>;
64 };
65
66 pci@2,0 {
67 device_type = "pci";
68 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
83 status = "disabled";
84
85 #address-cells = <3>;
86 #size-cells = <2>;
87 ranges;
88
89 nvidia,num-lanes = <2>;
90 };
91 };
92
58ecb23f 93 host1x@50000000 {
ed39097c
TR		 94 compatible = "nvidia,tegra30-host1x", "simple-bus";
95 reg = <0x50000000 0x00024000>;
6cecf916
SW		 96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
ed39097c
TR		 101
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 ranges = <0x54000000 0x54000000 0x04000000>;
106
58ecb23f 107 mpe@54040000 {
ed39097c
TR		 108 compatible = "nvidia,tegra30-mpe";
109 reg = <0x54040000 0x00040000>;
6cecf916 110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 112 resets = <&tegra_car 60>;
113 reset-names = "mpe";
ed39097c
TR		 114 };
115
58ecb23f 116 vi@54080000 {
ed39097c
TR		 117 compatible = "nvidia,tegra30-vi";
118 reg = <0x54080000 0x00040000>;
6cecf916 119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 120 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 121 resets = <&tegra_car 20>;
122 reset-names = "vi";
ed39097c
TR		 123 };
124
58ecb23f 125 epp@540c0000 {
ed39097c
TR		 126 compatible = "nvidia,tegra30-epp";
127 reg = <0x540c0000 0x00040000>;
6cecf916 128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 130 resets = <&tegra_car 19>;
131 reset-names = "epp";
ed39097c
TR		 132 };
133
58ecb23f 134 isp@54100000 {
ed39097c
TR		 135 compatible = "nvidia,tegra30-isp";
136 reg = <0x54100000 0x00040000>;
6cecf916 137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 139 resets = <&tegra_car 23>;
140 reset-names = "isp";
ed39097c
TR		 141 };
142
58ecb23f 143 gr2d@54140000 {
ed39097c
TR		 144 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>;
6cecf916 146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3393d422
SW		 147 resets = <&tegra_car 21>;
148 reset-names = "2d";
05849c93 149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
ed39097c
TR		 150 };
151
58ecb23f 152 gr3d@54180000 {
ed39097c
TR		 153 compatible = "nvidia,tegra30-gr3d";
154 reg = <0x54180000 0x00040000>;
c71d3909
TR		 155 clocks = <&tegra_car TEGRA30_CLK_GR3D
156 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 157 clock-names = "3d", "3d2";
3393d422
SW		 158 resets = <&tegra_car 24>,
159 <&tegra_car 98>;
160 reset-names = "3d", "3d2";
ed39097c
TR		 161 };
162
163 dc@54200000 {
05465f4e 164 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 165 reg = <0x54200000 0x00040000>;
6cecf916 166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
168 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 169 clock-names = "dc", "parent";
3393d422
SW		 170 resets = <&tegra_car 27>;
171 reset-names = "dc";
ed39097c
TR		 172
173 rgb {
174 status = "disabled";
175 };
176 };
177
178 dc@54240000 {
179 compatible = "nvidia,tegra30-dc";
180 reg = <0x54240000 0x00040000>;
6cecf916 181 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 182 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
183 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 184 clock-names = "dc", "parent";
3393d422
SW		 185 resets = <&tegra_car 26>;
186 reset-names = "dc";
ed39097c
TR		 187
188 rgb {
189 status = "disabled";
190 };
191 };
192
58ecb23f 193 hdmi@54280000 {
ed39097c
TR		 194 compatible = "nvidia,tegra30-hdmi";
195 reg = <0x54280000 0x00040000>;
6cecf916 196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 199 clock-names = "hdmi", "parent";
3393d422
SW		 200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
ed39097c
TR		 202 status = "disabled";
203 };
204
58ecb23f 205 tvo@542c0000 {
ed39097c
TR		 206 compatible = "nvidia,tegra30-tvo";
207 reg = <0x542c0000 0x00040000>;
6cecf916 208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 209 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 210 status = "disabled";
211 };
212
58ecb23f 213 dsi@54300000 {
ed39097c
TR		 214 compatible = "nvidia,tegra30-dsi";
215 reg = <0x54300000 0x00040000>;
05849c93 216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 217 resets = <&tegra_car 48>;
218 reset-names = "dsi";
ed39097c
TR		 219 status = "disabled";
220 };
221 };
222
73368ba0
SW		 223 timer@50004600 {
224 compatible = "arm,cortex-a9-twd-timer";
225 reg = <0x50040600 0x20>;
6cecf916
SW		 226 interrupts = <GIC_PPI 13
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 229 };
230
58ecb23f 231 intc: interrupt-controller@50041000 {
c3e00a0e 232 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 233 reg = <0x50041000 0x1000
234 0x50040100 0x0100>;
2eaab06e
SW		 235 interrupt-controller;
236 #interrupt-cells = <3>;
c3e00a0e
PDS		 237 };
238
58ecb23f 239 cache-controller@50043000 {
bb2c1de9
SW		 240 compatible = "arm,pl310-cache";
241 reg = <0x50043000 0x1000>;
242 arm,data-latency = <6 6 2>;
243 arm,tag-latency = <5 5 2>;
244 cache-unified;
245 cache-level = <2>;
246 };
247
2f2b7fb2
SW		 248 timer@60005000 {
249 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
250 reg = <0x60005000 0x400>;
6cecf916
SW		 251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 258 };
259
58ecb23f 260 tegra_car: clock@60006000 {
95985667
PG		 261 compatible = "nvidia,tegra30-car";
262 reg = <0x60006000 0x1000>;
263 #clock-cells = <1>;
3393d422 264 #reset-cells = <1>;
95985667
PG		 265 };
266
58ecb23f 267 apbdma: dma@6000a000 {
8051b75a
SW		 268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
269 reg = <0x6000a000 0x1400>;
6cecf916
SW		 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 302 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 303 resets = <&tegra_car 34>;
304 reset-names = "dma";
034d023f 305 #dma-cells = <1>;
8051b75a
SW		 306 };
307
58ecb23f 308 ahb: ahb@6000c004 {
c04abb3a
SW		 309 compatible = "nvidia,tegra30-ahb";
310 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 311 };
312
58ecb23f 313 gpio: gpio@6000d000 {
35f210ec 314 compatible = "nvidia,tegra30-gpio";
95decf84 315 reg = <0x6000d000 0x1000>;
6cecf916
SW		 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 324 #gpio-cells = <2>;
325 gpio-controller;
6f74dc9b
SW		 326 #interrupt-cells = <2>;
327 interrupt-controller;
c3e00a0e
PDS		 328 };
329
58ecb23f 330 pinmux: pinmux@70000868 {
c04abb3a 331 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 332 reg = <0x70000868 0xd4 /* Pad control registers */
333 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 334 };
335
b6551bb9
LD		 336 /*
337 * There are two serial driver i.e. 8250 based simple serial
338 * driver and APB DMA based serial driver for higher baudrate
339 * and performace. To enable the 8250 based driver, the compatible
340 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
341 * the APB DMA based serial driver, the comptible is
342 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
343 */
344 uarta: serial@70006000 {
c3e00a0e
PDS		 345 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
346 reg = <0x70006000 0x40>;
347 reg-shift = <2>;
6cecf916 348 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 349 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 350 resets = <&tegra_car 6>;
351 reset-names = "serial";
034d023f
SW		 352 dmas = <&apbdma 8>, <&apbdma 8>;
353 dma-names = "rx", "tx";
223ef78d 354 status = "disabled";
c3e00a0e
PDS		 355 };
356
b6551bb9 357 uartb: serial@70006040 {
c3e00a0e
PDS		 358 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
359 reg = <0x70006040 0x40>;
360 reg-shift = <2>;
6cecf916 361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 362 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 363 resets = <&tegra_car 7>;
364 reset-names = "serial";
034d023f
SW		 365 dmas = <&apbdma 9>, <&apbdma 9>;
366 dma-names = "rx", "tx";
223ef78d 367 status = "disabled";
c3e00a0e
PDS		 368 };
369
b6551bb9 370 uartc: serial@70006200 {
c3e00a0e
PDS		 371 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
372 reg = <0x70006200 0x100>;
373 reg-shift = <2>;
6cecf916 374 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 375 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 376 resets = <&tegra_car 55>;
377 reset-names = "serial";
034d023f
SW		 378 dmas = <&apbdma 10>, <&apbdma 10>;
379 dma-names = "rx", "tx";
223ef78d 380 status = "disabled";
c3e00a0e
PDS		 381 };
382
b6551bb9 383 uartd: serial@70006300 {
c3e00a0e
PDS		 384 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
385 reg = <0x70006300 0x100>;
386 reg-shift = <2>;
6cecf916 387 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 388 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 389 resets = <&tegra_car 65>;
390 reset-names = "serial";
034d023f
SW		 391 dmas = <&apbdma 19>, <&apbdma 19>;
392 dma-names = "rx", "tx";
223ef78d 393 status = "disabled";
c3e00a0e
PDS		 394 };
395
b6551bb9 396 uarte: serial@70006400 {
c3e00a0e
PDS		 397 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
398 reg = <0x70006400 0x100>;
399 reg-shift = <2>;
6cecf916 400 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 401 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 402 resets = <&tegra_car 66>;
403 reset-names = "serial";
034d023f
SW		 404 dmas = <&apbdma 20>, <&apbdma 20>;
405 dma-names = "rx", "tx";
223ef78d 406 status = "disabled";
c3e00a0e
PDS		 407 };
408
58ecb23f 409 pwm: pwm@7000a000 {
140fd977
TR		 410 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
411 reg = <0x7000a000 0x100>;
412 #pwm-cells = <2>;
05849c93 413 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 414 resets = <&tegra_car 17>;
415 reset-names = "pwm";
b69cd984 416 status = "disabled";
140fd977
TR		 417 };
418
58ecb23f 419 rtc@7000e000 {
380e04ac
SW		 420 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
421 reg = <0x7000e000 0x100>;
6cecf916 422 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 423 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 424 };
425
c04abb3a 426 i2c@7000c000 {
c04abb3a
SW		 427 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
428 reg = <0x7000c000 0x100>;
6cecf916 429 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 430 #address-cells = <1>;
431 #size-cells = <0>;
05849c93
HD		 432 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
433 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 434 clock-names = "div-clk", "fast-clk";
3393d422
SW		 435 resets = <&tegra_car 12>;
436 reset-names = "i2c";
034d023f
SW		 437 dmas = <&apbdma 21>, <&apbdma 21>;
438 dma-names = "rx", "tx";
223ef78d 439 status = "disabled";
c3e00a0e
PDS		 440 };
441
c04abb3a 442 i2c@7000c400 {
c04abb3a
SW		 443 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
444 reg = <0x7000c400 0x100>;
6cecf916 445 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 446 #address-cells = <1>;
447 #size-cells = <0>;
05849c93
HD		 448 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
449 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 450 clock-names = "div-clk", "fast-clk";
3393d422
SW		 451 resets = <&tegra_car 54>;
452 reset-names = "i2c";
034d023f
SW		 453 dmas = <&apbdma 22>, <&apbdma 22>;
454 dma-names = "rx", "tx";
223ef78d 455 status = "disabled";
c3e00a0e
PDS		 456 };
457
c04abb3a 458 i2c@7000c500 {
c04abb3a
SW		 459 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
460 reg = <0x7000c500 0x100>;
6cecf916 461 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 462 #address-cells = <1>;
463 #size-cells = <0>;
05849c93
HD		 464 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
465 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 466 clock-names = "div-clk", "fast-clk";
3393d422
SW		 467 resets = <&tegra_car 67>;
468 reset-names = "i2c";
034d023f
SW		 469 dmas = <&apbdma 23>, <&apbdma 23>;
470 dma-names = "rx", "tx";
223ef78d 471 status = "disabled";
c3e00a0e
PDS		 472 };
473
c04abb3a 474 i2c@7000c700 {
c04abb3a
SW		 475 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
476 reg = <0x7000c700 0x100>;
6cecf916 477 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 478 #address-cells = <1>;
479 #size-cells = <0>;
05849c93
HD		 480 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
481 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 482 resets = <&tegra_car 103>;
483 reset-names = "i2c";
1cbc733d 484 clock-names = "div-clk", "fast-clk";
034d023f
SW		 485 dmas = <&apbdma 26>, <&apbdma 26>;
486 dma-names = "rx", "tx";
223ef78d 487 status = "disabled";
c3e00a0e
PDS		 488 };
489
c04abb3a 490 i2c@7000d000 {
c04abb3a
SW		 491 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
492 reg = <0x7000d000 0x100>;
6cecf916 493 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 494 #address-cells = <1>;
495 #size-cells = <0>;
05849c93
HD		 496 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
497 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 498 clock-names = "div-clk", "fast-clk";
3393d422
SW		 499 resets = <&tegra_car 47>;
500 reset-names = "i2c";
034d023f
SW		 501 dmas = <&apbdma 24>, <&apbdma 24>;
502 dma-names = "rx", "tx";
223ef78d 503 status = "disabled";
c04abb3a
SW		 504 };
505
a86b0db3
LD		 506 spi@7000d400 {
507 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
508 reg = <0x7000d400 0x200>;
6cecf916 509 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 510 #address-cells = <1>;
511 #size-cells = <0>;
05849c93 512 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 513 resets = <&tegra_car 41>;
514 reset-names = "spi";
034d023f
SW		 515 dmas = <&apbdma 15>, <&apbdma 15>;
516 dma-names = "rx", "tx";
a86b0db3
LD		 517 status = "disabled";
518 };
519
520 spi@7000d600 {
521 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
522 reg = <0x7000d600 0x200>;
6cecf916 523 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 524 #address-cells = <1>;
525 #size-cells = <0>;
05849c93 526 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 527 resets = <&tegra_car 44>;
528 reset-names = "spi";
034d023f
SW		 529 dmas = <&apbdma 16>, <&apbdma 16>;
530 dma-names = "rx", "tx";
a86b0db3
LD		 531 status = "disabled";
532 };
533
534 spi@7000d800 {
535 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 536 reg = <0x7000d800 0x200>;
6cecf916 537 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 538 #address-cells = <1>;
539 #size-cells = <0>;
05849c93 540 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 541 resets = <&tegra_car 46>;
542 reset-names = "spi";
034d023f
SW		 543 dmas = <&apbdma 17>, <&apbdma 17>;
544 dma-names = "rx", "tx";
a86b0db3
LD		 545 status = "disabled";
546 };
547
548 spi@7000da00 {
549 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
550 reg = <0x7000da00 0x200>;
6cecf916 551 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 552 #address-cells = <1>;
553 #size-cells = <0>;
05849c93 554 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 555 resets = <&tegra_car 68>;
556 reset-names = "spi";
034d023f
SW		 557 dmas = <&apbdma 18>, <&apbdma 18>;
558 dma-names = "rx", "tx";
a86b0db3
LD		 559 status = "disabled";
560 };
561
562 spi@7000dc00 {
563 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
564 reg = <0x7000dc00 0x200>;
6cecf916 565 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 566 #address-cells = <1>;
567 #size-cells = <0>;
05849c93 568 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 569 resets = <&tegra_car 104>;
570 reset-names = "spi";
034d023f
SW		 571 dmas = <&apbdma 27>, <&apbdma 27>;
572 dma-names = "rx", "tx";
a86b0db3
LD		 573 status = "disabled";
574 };
575
576 spi@7000de00 {
577 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
578 reg = <0x7000de00 0x200>;
6cecf916 579 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 580 #address-cells = <1>;
581 #size-cells = <0>;
05849c93 582 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 583 resets = <&tegra_car 106>;
584 reset-names = "spi";
034d023f
SW		 585 dmas = <&apbdma 28>, <&apbdma 28>;
586 dma-names = "rx", "tx";
a86b0db3
LD		 587 status = "disabled";
588 };
589
58ecb23f 590 kbc@7000e200 {
699ed4b9
LD		 591 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
592 reg = <0x7000e200 0x100>;
6cecf916 593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 594 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 595 resets = <&tegra_car 36>;
596 reset-names = "kbc";
699ed4b9
LD		 597 status = "disabled";
598 };
599
58ecb23f 600 pmc@7000e400 {
2b84e53b 601 compatible = "nvidia,tegra30-pmc";
c04abb3a 602 reg = <0x7000e400 0x400>;
05849c93 603 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 604 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 605 };
606
58ecb23f 607 memory-controller@7000f000 {
c04abb3a
SW		 608 compatible = "nvidia,tegra30-mc";
609 reg = <0x7000f000 0x010
610 0x7000f03c 0x1b4
611 0x7000f200 0x028
612 0x7000f284 0x17c>;
6cecf916 613 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 614 };
615
58ecb23f 616 iommu@7000f010 {
c04abb3a
SW		 617 compatible = "nvidia,tegra30-smmu";
618 reg = <0x7000f010 0x02c
619 0x7000f1f0 0x010
620 0x7000f228 0x05c>;
621 nvidia,#asids = <4>; /* # of ASIDs */
622 dma-window = <0 0x40000000>; /* IOVA start & length */
623 nvidia,ahb = <&ahb>;
c3e00a0e 624 };
9ee6a5c4 625
58ecb23f 626 ahub@70080000 {
9ee6a5c4 627 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 628 reg = <0x70080000 0x200
629 0x70080200 0x100>;
6cecf916 630 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 631 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 632 <&tegra_car TEGRA30_CLK_APBIF>;
633 clock-names = "d_audio", "apbif";
3393d422
SW		 634 resets = <&tegra_car 106>, /* d_audio */
635 <&tegra_car 107>, /* apbif */
636 <&tegra_car 30>, /* i2s0 */
637 <&tegra_car 11>, /* i2s1 */
638 <&tegra_car 18>, /* i2s2 */
639 <&tegra_car 101>, /* i2s3 */
640 <&tegra_car 102>, /* i2s4 */
641 <&tegra_car 108>, /* dam0 */
642 <&tegra_car 109>, /* dam1 */
643 <&tegra_car 110>, /* dam2 */
644 <&tegra_car 10>; /* spdif */
645 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
646 "i2s3", "i2s4", "dam0", "dam1", "dam2",
647 "spdif";
034d023f
SW		 648 dmas = <&apbdma 1>, <&apbdma 1>,
649 <&apbdma 2>, <&apbdma 2>,
650 <&apbdma 3>, <&apbdma 3>,
651 <&apbdma 4>, <&apbdma 4>;
652 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
653 "rx3", "tx3";
9ee6a5c4
SW		 654 ranges;
655 #address-cells = <1>;
656 #size-cells = <1>;
657
658 tegra_i2s0: i2s@70080300 {
659 compatible = "nvidia,tegra30-i2s";
660 reg = <0x70080300 0x100>;
661 nvidia,ahub-cif-ids = <4 4>;
05849c93 662 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 663 resets = <&tegra_car 30>;
664 reset-names = "i2s";
223ef78d 665 status = "disabled";
9ee6a5c4
SW		 666 };
667
668 tegra_i2s1: i2s@70080400 {
669 compatible = "nvidia,tegra30-i2s";
670 reg = <0x70080400 0x100>;
671 nvidia,ahub-cif-ids = <5 5>;
05849c93 672 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 673 resets = <&tegra_car 11>;
674 reset-names = "i2s";
223ef78d 675 status = "disabled";
9ee6a5c4
SW		 676 };
677
678 tegra_i2s2: i2s@70080500 {
679 compatible = "nvidia,tegra30-i2s";
680 reg = <0x70080500 0x100>;
681 nvidia,ahub-cif-ids = <6 6>;
05849c93 682 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 683 resets = <&tegra_car 18>;
684 reset-names = "i2s";
223ef78d 685 status = "disabled";
9ee6a5c4
SW		 686 };
687
688 tegra_i2s3: i2s@70080600 {
689 compatible = "nvidia,tegra30-i2s";
690 reg = <0x70080600 0x100>;
691 nvidia,ahub-cif-ids = <7 7>;
05849c93 692 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 693 resets = <&tegra_car 101>;
694 reset-names = "i2s";
223ef78d 695 status = "disabled";
9ee6a5c4
SW		 696 };
697
698 tegra_i2s4: i2s@70080700 {
699 compatible = "nvidia,tegra30-i2s";
700 reg = <0x70080700 0x100>;
701 nvidia,ahub-cif-ids = <8 8>;
05849c93 702 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 703 resets = <&tegra_car 102>;
704 reset-names = "i2s";
223ef78d 705 status = "disabled";
9ee6a5c4
SW		 706 };
707 };
7868a9bc 708
c04abb3a
SW		 709 sdhci@78000000 {
710 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
711 reg = <0x78000000 0x200>;
6cecf916 712 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 713 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 714 resets = <&tegra_car 14>;
715 reset-names = "sdhci";
223ef78d 716 status = "disabled";
7868a9bc 717 };
ecf43742 718
c04abb3a
SW		 719 sdhci@78000200 {
720 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
721 reg = <0x78000200 0x200>;
6cecf916 722 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 723 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 724 resets = <&tegra_car 9>;
725 reset-names = "sdhci";
223ef78d 726 status = "disabled";
ecf43742 727 };
54174a33 728
c04abb3a
SW		 729 sdhci@78000400 {
730 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
731 reg = <0x78000400 0x200>;
6cecf916 732 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 733 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 734 resets = <&tegra_car 69>;
735 reset-names = "sdhci";
223ef78d 736 status = "disabled";
c04abb3a
SW		 737 };
738
739 sdhci@78000600 {
740 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
741 reg = <0x78000600 0x200>;
6cecf916 742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 743 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 744 resets = <&tegra_car 15>;
745 reset-names = "sdhci";
223ef78d 746 status = "disabled";
c04abb3a
SW		 747 };
748
cc34c9f7
TT		 749 usb@7d000000 {
750 compatible = "nvidia,tegra30-ehci", "usb-ehci";
751 reg = <0x7d000000 0x4000>;
752 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
753 phy_type = "utmi";
754 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 755 resets = <&tegra_car 22>;
756 reset-names = "usb";
cc34c9f7
TT		 757 nvidia,needs-double-reset;
758 nvidia,phy = <&phy1>;
759 status = "disabled";
760 };
761
762 phy1: usb-phy@7d000000 {
763 compatible = "nvidia,tegra30-usb-phy";
764 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
765 phy_type = "utmi";
766 clocks = <&tegra_car TEGRA30_CLK_USBD>,
767 <&tegra_car TEGRA30_CLK_PLL_U>,
768 <&tegra_car TEGRA30_CLK_USBD>;
769 clock-names = "reg", "pll_u", "utmi-pads";
770 nvidia,hssync-start-delay = <9>;
771 nvidia,idle-wait-delay = <17>;
772 nvidia,elastic-limit = <16>;
773 nvidia,term-range-adj = <6>;
774 nvidia,xcvr-setup = <51>;
775 nvidia.xcvr-setup-use-fuses;
776 nvidia,xcvr-lsfslew = <1>;
777 nvidia,xcvr-lsrslew = <1>;
778 nvidia,xcvr-hsslew = <32>;
779 nvidia,hssquelch-level = <2>;
780 nvidia,hsdiscon-level = <5>;
781 status = "disabled";
782 };
783
784 usb@7d004000 {
785 compatible = "nvidia,tegra30-ehci", "usb-ehci";
786 reg = <0x7d004000 0x4000>;
787 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
788 phy_type = "ulpi";
789 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 790 resets = <&tegra_car 58>;
791 reset-names = "usb";
cc34c9f7
TT		 792 nvidia,phy = <&phy2>;
793 status = "disabled";
794 };
795
796 phy2: usb-phy@7d004000 {
797 compatible = "nvidia,tegra30-usb-phy";
798 reg = <0x7d004000 0x4000>;
799 phy_type = "ulpi";
800 clocks = <&tegra_car TEGRA30_CLK_USB2>,
801 <&tegra_car TEGRA30_CLK_PLL_U>,
802 <&tegra_car TEGRA30_CLK_CDEV2>;
803 clock-names = "reg", "pll_u", "ulpi-link";
804 status = "disabled";
805 };
806
807 usb@7d008000 {
808 compatible = "nvidia,tegra30-ehci", "usb-ehci";
809 reg = <0x7d008000 0x4000>;
810 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
811 phy_type = "utmi";
812 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 813 resets = <&tegra_car 59>;
814 reset-names = "usb";
cc34c9f7
TT		 815 nvidia,phy = <&phy3>;
816 status = "disabled";
817 };
818
819 phy3: usb-phy@7d008000 {
820 compatible = "nvidia,tegra30-usb-phy";
821 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
822 phy_type = "utmi";
823 clocks = <&tegra_car TEGRA30_CLK_USB3>,
824 <&tegra_car TEGRA30_CLK_PLL_U>,
825 <&tegra_car TEGRA30_CLK_USBD>;
826 clock-names = "reg", "pll_u", "utmi-pads";
827 nvidia,hssync-start-delay = <0>;
828 nvidia,idle-wait-delay = <17>;
829 nvidia,elastic-limit = <16>;
830 nvidia,term-range-adj = <6>;
831 nvidia,xcvr-setup = <51>;
832 nvidia.xcvr-setup-use-fuses;
833 nvidia,xcvr-lsfslew = <2>;
834 nvidia,xcvr-lsrslew = <2>;
835 nvidia,xcvr-hsslew = <32>;
836 nvidia,hssquelch-level = <2>;
837 nvidia,hsdiscon-level = <5>;
838 status = "disabled";
839 };
840
7d19a34a
HD		 841 cpus {
842 #address-cells = <1>;
843 #size-cells = <0>;
844
845 cpu@0 {
846 device_type = "cpu";
847 compatible = "arm,cortex-a9";
848 reg = <0>;
849 };
850
851 cpu@1 {
852 device_type = "cpu";
853 compatible = "arm,cortex-a9";
854 reg = <1>;
855 };
856
857 cpu@2 {
858 device_type = "cpu";
859 compatible = "arm,cortex-a9";
860 reg = <2>;
861 };
862
863 cpu@3 {
864 device_type = "cpu";
865 compatible = "arm,cortex-a9";
866 reg = <3>;
867 };
868 };
869
c04abb3a
SW		 870 pmu {
871 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 872 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 876 };
c3e00a0e 877};
Ubuntu Eoan Linux kernel mirror