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8e678e06 | 1 | /* |
77896e4d | 2 | * Device Tree Source for UniPhier LD4 SoC |
8e678e06 | 3 | * |
77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
8e678e06 MY |
6 | * |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
2752bcaa | 46 | /include/ "skeleton.dtsi" |
8e678e06 MY |
47 | |
48 | / { | |
77896e4d | 49 | compatible = "socionext,uniphier-ld4"; |
8e678e06 MY |
50 | |
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | ||
55 | cpu@0 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0>; | |
3bdba5ac | 59 | enable-method = "psci"; |
7c62f299 | 60 | next-level-cache = <&l2>; |
8e678e06 MY |
61 | }; |
62 | }; | |
63 | ||
2752bcaa MY |
64 | psci { |
65 | compatible = "arm,psci-0.2"; | |
66 | method = "smc"; | |
67 | }; | |
68 | ||
8e678e06 | 69 | clocks { |
2752bcaa MY |
70 | refclk: ref { |
71 | compatible = "fixed-clock"; | |
72 | #clock-cells = <0>; | |
73 | clock-frequency = <24576000>; | |
74 | }; | |
75 | ||
8e678e06 MY |
76 | arm_timer_clk: arm_timer_clk { |
77 | #clock-cells = <0>; | |
78 | compatible = "fixed-clock"; | |
79 | clock-frequency = <50000000>; | |
80 | }; | |
81 | }; | |
68f46897 | 82 | |
2752bcaa MY |
83 | soc { |
84 | compatible = "simple-bus"; | |
629b557a | 85 | #address-cells = <1>; |
2752bcaa MY |
86 | #size-cells = <1>; |
87 | ranges; | |
88 | interrupt-parent = <&intc>; | |
68f46897 | 89 | |
2752bcaa MY |
90 | l2: l2-cache@500c0000 { |
91 | compatible = "socionext,uniphier-system-cache"; | |
92 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, | |
93 | <0x506c0000 0x400>; | |
94 | interrupts = <0 174 4>, <0 175 4>; | |
95 | cache-unified; | |
96 | cache-size = <(512 * 1024)>; | |
97 | cache-sets = <256>; | |
98 | cache-line-size = <128>; | |
99 | cache-level = <2>; | |
100 | }; | |
8e678e06 | 101 | |
2752bcaa MY |
102 | serial0: serial@54006800 { |
103 | compatible = "socionext,uniphier-uart"; | |
104 | status = "disabled"; | |
105 | reg = <0x54006800 0x40>; | |
106 | interrupts = <0 33 4>; | |
107 | pinctrl-names = "default"; | |
108 | pinctrl-0 = <&pinctrl_uart0>; | |
109 | clocks = <&peri_clk 0>; | |
110 | }; | |
3fbf02a8 | 111 | |
2752bcaa MY |
112 | serial1: serial@54006900 { |
113 | compatible = "socionext,uniphier-uart"; | |
114 | status = "disabled"; | |
115 | reg = <0x54006900 0x40>; | |
116 | interrupts = <0 35 4>; | |
117 | pinctrl-names = "default"; | |
118 | pinctrl-0 = <&pinctrl_uart1>; | |
119 | clocks = <&peri_clk 1>; | |
120 | }; | |
3fbf02a8 | 121 | |
2752bcaa MY |
122 | serial2: serial@54006a00 { |
123 | compatible = "socionext,uniphier-uart"; | |
124 | status = "disabled"; | |
125 | reg = <0x54006a00 0x40>; | |
126 | interrupts = <0 37 4>; | |
127 | pinctrl-names = "default"; | |
128 | pinctrl-0 = <&pinctrl_uart2>; | |
129 | clocks = <&peri_clk 2>; | |
130 | }; | |
3fbf02a8 | 131 | |
2752bcaa MY |
132 | serial3: serial@54006b00 { |
133 | compatible = "socionext,uniphier-uart"; | |
134 | status = "disabled"; | |
135 | reg = <0x54006b00 0x40>; | |
136 | interrupts = <0 29 4>; | |
137 | pinctrl-names = "default"; | |
138 | pinctrl-0 = <&pinctrl_uart3>; | |
139 | clocks = <&peri_clk 3>; | |
140 | }; | |
55d945b2 | 141 | |
2752bcaa MY |
142 | i2c0: i2c@58400000 { |
143 | compatible = "socionext,uniphier-i2c"; | |
144 | status = "disabled"; | |
145 | reg = <0x58400000 0x40>; | |
146 | #address-cells = <1>; | |
147 | #size-cells = <0>; | |
148 | interrupts = <0 41 1>; | |
149 | pinctrl-names = "default"; | |
150 | pinctrl-0 = <&pinctrl_i2c0>; | |
151 | clocks = <&peri_clk 4>; | |
152 | clock-frequency = <100000>; | |
153 | }; | |
8e678e06 | 154 | |
2752bcaa MY |
155 | i2c1: i2c@58480000 { |
156 | compatible = "socionext,uniphier-i2c"; | |
157 | status = "disabled"; | |
158 | reg = <0x58480000 0x40>; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | interrupts = <0 42 1>; | |
162 | pinctrl-names = "default"; | |
163 | pinctrl-0 = <&pinctrl_i2c1>; | |
164 | clocks = <&peri_clk 5>; | |
165 | clock-frequency = <100000>; | |
166 | }; | |
8e678e06 | 167 | |
2752bcaa MY |
168 | /* chip-internal connection for DMD */ |
169 | i2c2: i2c@58500000 { | |
170 | compatible = "socionext,uniphier-i2c"; | |
171 | reg = <0x58500000 0x40>; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | interrupts = <0 43 1>; | |
175 | pinctrl-names = "default"; | |
176 | pinctrl-0 = <&pinctrl_i2c2>; | |
177 | clocks = <&peri_clk 6>; | |
178 | clock-frequency = <400000>; | |
179 | }; | |
61f838c7 | 180 | |
2752bcaa MY |
181 | i2c3: i2c@58580000 { |
182 | compatible = "socionext,uniphier-i2c"; | |
183 | status = "disabled"; | |
184 | reg = <0x58580000 0x40>; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | interrupts = <0 44 1>; | |
188 | pinctrl-names = "default"; | |
189 | pinctrl-0 = <&pinctrl_i2c3>; | |
190 | clocks = <&peri_clk 7>; | |
191 | clock-frequency = <100000>; | |
192 | }; | |
62237230 | 193 | |
2752bcaa MY |
194 | system_bus: system-bus@58c00000 { |
195 | compatible = "socionext,uniphier-system-bus"; | |
196 | status = "disabled"; | |
197 | reg = <0x58c00000 0x400>; | |
198 | #address-cells = <2>; | |
199 | #size-cells = <1>; | |
200 | pinctrl-names = "default"; | |
201 | pinctrl-0 = <&pinctrl_system_bus>; | |
202 | }; | |
ad0561d4 | 203 | |
2752bcaa MY |
204 | smpctrl@59800000 { |
205 | compatible = "socionext,uniphier-smpctrl"; | |
206 | reg = <0x59801000 0x400>; | |
207 | }; | |
ad0561d4 | 208 | |
2752bcaa MY |
209 | mioctrl@59810000 { |
210 | compatible = "socionext,uniphier-ld4-mioctrl", | |
211 | "simple-mfd", "syscon"; | |
212 | reg = <0x59810000 0x800>; | |
ad0561d4 | 213 | |
2752bcaa MY |
214 | mio_clk: clock { |
215 | compatible = "socionext,uniphier-ld4-mio-clock"; | |
216 | #clock-cells = <1>; | |
217 | }; | |
ad0561d4 | 218 | |
2752bcaa MY |
219 | mio_rst: reset { |
220 | compatible = "socionext,uniphier-ld4-mio-reset"; | |
221 | #reset-cells = <1>; | |
222 | }; | |
223 | }; | |
ad0561d4 | 224 | |
2752bcaa MY |
225 | perictrl@59820000 { |
226 | compatible = "socionext,uniphier-ld4-perictrl", | |
227 | "simple-mfd", "syscon"; | |
228 | reg = <0x59820000 0x200>; | |
229 | ||
230 | peri_clk: clock { | |
231 | compatible = "socionext,uniphier-ld4-peri-clock"; | |
232 | #clock-cells = <1>; | |
233 | }; | |
234 | ||
235 | peri_rst: reset { | |
236 | compatible = "socionext,uniphier-ld4-peri-reset"; | |
237 | #reset-cells = <1>; | |
238 | }; | |
239 | }; | |
240 | ||
241 | usb0: usb@5a800100 { | |
242 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
243 | status = "disabled"; | |
244 | reg = <0x5a800100 0x100>; | |
245 | interrupts = <0 80 4>; | |
246 | pinctrl-names = "default"; | |
247 | pinctrl-0 = <&pinctrl_usb0>; | |
248 | clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; | |
249 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, | |
250 | <&mio_rst 12>; | |
251 | }; | |
252 | ||
253 | usb1: usb@5a810100 { | |
254 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
255 | status = "disabled"; | |
256 | reg = <0x5a810100 0x100>; | |
257 | interrupts = <0 81 4>; | |
258 | pinctrl-names = "default"; | |
259 | pinctrl-0 = <&pinctrl_usb1>; | |
260 | clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; | |
261 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, | |
262 | <&mio_rst 13>; | |
263 | }; | |
ad0561d4 | 264 | |
2752bcaa MY |
265 | usb2: usb@5a820100 { |
266 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
267 | status = "disabled"; | |
268 | reg = <0x5a820100 0x100>; | |
269 | interrupts = <0 82 4>; | |
270 | pinctrl-names = "default"; | |
271 | pinctrl-0 = <&pinctrl_usb2>; | |
272 | clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; | |
273 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, | |
274 | <&mio_rst 14>; | |
275 | }; | |
276 | ||
277 | soc-glue@5f800000 { | |
278 | compatible = "socionext,uniphier-ld4-soc-glue", | |
279 | "simple-mfd", "syscon"; | |
280 | reg = <0x5f800000 0x2000>; | |
281 | ||
282 | pinctrl: pinctrl { | |
283 | compatible = "socionext,uniphier-ld4-pinctrl"; | |
284 | }; | |
285 | }; | |
286 | ||
287 | timer@60000200 { | |
288 | compatible = "arm,cortex-a9-global-timer"; | |
289 | reg = <0x60000200 0x20>; | |
290 | interrupts = <1 11 0x104>; | |
291 | clocks = <&arm_timer_clk>; | |
292 | }; | |
293 | ||
294 | timer@60000600 { | |
295 | compatible = "arm,cortex-a9-twd-timer"; | |
296 | reg = <0x60000600 0x20>; | |
297 | interrupts = <1 13 0x104>; | |
298 | clocks = <&arm_timer_clk>; | |
299 | }; | |
300 | ||
301 | intc: interrupt-controller@60001000 { | |
302 | compatible = "arm,cortex-a9-gic"; | |
303 | reg = <0x60001000 0x1000>, | |
304 | <0x60000100 0x100>; | |
305 | #interrupt-cells = <3>; | |
306 | interrupt-controller; | |
307 | }; | |
308 | ||
309 | sysctrl@61840000 { | |
310 | compatible = "socionext,uniphier-ld4-sysctrl", | |
311 | "simple-mfd", "syscon"; | |
312 | reg = <0x61840000 0x10000>; | |
313 | ||
314 | sys_clk: clock { | |
315 | compatible = "socionext,uniphier-ld4-clock"; | |
316 | #clock-cells = <1>; | |
317 | }; | |
318 | ||
319 | sys_rst: reset { | |
320 | compatible = "socionext,uniphier-ld4-reset"; | |
321 | #reset-cells = <1>; | |
322 | }; | |
323 | }; | |
324 | }; | |
ad0561d4 | 325 | }; |
2752bcaa MY |
326 | |
327 | /include/ "uniphier-pinctrl.dtsi" |