[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / uniphier-ph1-sld3.dtsi

/*
 * Device Tree Source for UniPhier PH1-sLD3 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,ph1-sld3";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <36864000>;
		};

		iobus_clk: iobus_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <100000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		extbus: extbus {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <1>;
		};

		timer@20000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@20000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@20001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x20001000 0x1000>,
			      <0x20000100 0x100>;
		};

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(512 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58600000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58600000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <400000>;
		};

		system-bus-controller@58c00000 {
			compatible = "socionext,uniphier-system-bus-controller";
			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 80 4>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 81 4>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 82 4>;
		};

		usb3: usb@5a830100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a830100 0x100>;
			interrupts = <0 83 4>;
		};
	};
};
Commit	Line	Data
8e678e06 MY	1	/*
	2	* Device Tree Source for UniPhier PH1-sLD3 SoC
	3	*
	4	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	/include/ "skeleton.dtsi"
	46
	47	/ {
	48	compatible = "socionext,ph1-sld3";
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53	enable-method = "socionext,uniphier-smp";
	54
	55	cpu@0 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	reg = <0>;
7c62f299	59	next-level-cache = <&l2>;
8e678e06 MY	60	};
	61
	62	cpu@1 {
	63	device_type = "cpu";
	64	compatible = "arm,cortex-a9";
	65	reg = <1>;
7c62f299	66	next-level-cache = <&l2>;
8e678e06 MY	67	};
	68	};
	69
	70	clocks {
	71	arm_timer_clk: arm_timer_clk {
	72	#clock-cells = <0>;
	73	compatible = "fixed-clock";
	74	clock-frequency = <50000000>;
	75	};
1bf42507 MY	76
	77	uart_clk: uart_clk {
	78	#clock-cells = <0>;
	79	compatible = "fixed-clock";
	80	clock-frequency = <36864000>;
	81	};
68f46897 MY	82
	83	iobus_clk: iobus_clk {
	84	#clock-cells = <0>;
	85	compatible = "fixed-clock";
	86	clock-frequency = <100000000>;
	87	};
8e678e06 MY	88	};
	89
	90	soc {
	91	compatible = "simple-bus";
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	ranges;
	95	interrupt-parent = <&intc>;
	96
	97	extbus: extbus {
	98	compatible = "simple-bus";
	99	#address-cells = <2>;
	100	#size-cells = <1>;
	101	};
	102
	103	timer@20000200 {
	104	compatible = "arm,cortex-a9-global-timer";
	105	reg = <0x20000200 0x20>;
	106	interrupts = <1 11 0x304>;
	107	clocks = <&arm_timer_clk>;
	108	};
	109
	110	timer@20000600 {
	111	compatible = "arm,cortex-a9-twd-timer";
	112	reg = <0x20000600 0x20>;
	113	interrupts = <1 13 0x304>;
	114	clocks = <&arm_timer_clk>;
	115	};
	116
	117	intc: interrupt-controller@20001000 {
	118	compatible = "arm,cortex-a9-gic";
	119	#interrupt-cells = <3>;
	120	interrupt-controller;
	121	reg = <0x20001000 0x1000>,
	122	<0x20000100 0x100>;
	123	};
	124
7c62f299 MY	125	l2: l2-cache@500c0000 {
	126	compatible = "socionext,uniphier-system-cache";
	127	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	128	<0x506c0000 0x400>;
	129	interrupts = <0 174 4>, <0 175 4>;
	130	cache-unified;
	131	cache-size = <(512 * 1024)>;
	132	cache-sets = <256>;
	133	cache-line-size = <128>;
	134	cache-level = <2>;
	135	};
	136
1bf42507 MY	137	serial0: serial@54006800 {
	138	compatible = "socionext,uniphier-uart";
	139	status = "disabled";
	140	reg = <0x54006800 0x40>;
	141	interrupts = <0 33 4>;
	142	clocks = <&uart_clk>;
	143	fifo-size = <64>;
	144	};
	145
	146	serial1: serial@54006900 {
	147	compatible = "socionext,uniphier-uart";
	148	status = "disabled";
	149	reg = <0x54006900 0x40>;
	150	interrupts = <0 35 4>;
	151	clocks = <&uart_clk>;
	152	fifo-size = <64>;
	153	};
	154
	155	serial2: serial@54006a00 {
	156	compatible = "socionext,uniphier-uart";
	157	status = "disabled";
	158	reg = <0x54006a00 0x40>;
	159	interrupts = <0 37 4>;
	160	clocks = <&uart_clk>;
	161	fifo-size = <64>;
	162	};
	163
68f46897 MY	164	i2c0: i2c@58400000 {
	165	compatible = "socionext,uniphier-i2c";
	166	status = "disabled";
	167	reg = <0x58400000 0x40>;
	168	#address-cells = <1>;
	169	#size-cells = <0>;
	170	interrupts = <0 41 1>;
	171	clocks = <&iobus_clk>;
	172	clock-frequency = <100000>;
	173	};
	174
	175	i2c1: i2c@58480000 {
	176	compatible = "socionext,uniphier-i2c";
	177	status = "disabled";
	178	reg = <0x58480000 0x40>;
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181	interrupts = <0 42 1>;
	182	clocks = <&iobus_clk>;
	183	clock-frequency = <100000>;
	184	};
	185
	186	i2c2: i2c@58500000 {
	187	compatible = "socionext,uniphier-i2c";
	188	status = "disabled";
	189	reg = <0x58500000 0x40>;
	190	#address-cells = <1>;
	191	#size-cells = <0>;
	192	interrupts = <0 43 1>;
	193	clocks = <&iobus_clk>;
	194	clock-frequency = <100000>;
	195	};
	196
	197	i2c3: i2c@58580000 {
	198	compatible = "socionext,uniphier-i2c";
	199	status = "disabled";
	200	reg = <0x58580000 0x40>;
	201	#address-cells = <1>;
	202	#size-cells = <0>;
	203	interrupts = <0 44 1>;
	204	clocks = <&iobus_clk>;
	205	clock-frequency = <100000>;
	206	};
	207
	208	/* chip-internal connection for DMD */
	209	i2c4: i2c@58600000 {
	210	compatible = "socionext,uniphier-i2c";
	211	reg = <0x58600000 0x40>;
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	interrupts = <0 45 1>;
	215	clocks = <&iobus_clk>;
	216	clock-frequency = <400000>;
	217	};
	218
1b38b0e3 MY	219	system-bus-controller@58c00000 {
	220	compatible = "socionext,uniphier-system-bus-controller";
	221	reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
8e678e06	222	};
3fbf02a8 MY	223
	224	usb0: usb@5a800100 {
	225	compatible = "socionext,uniphier-ehci", "generic-ehci";
	226	status = "disabled";
	227	reg = <0x5a800100 0x100>;
	228	interrupts = <0 80 4>;
	229	};
	230
	231	usb1: usb@5a810100 {
	232	compatible = "socionext,uniphier-ehci", "generic-ehci";
	233	status = "disabled";
	234	reg = <0x5a810100 0x100>;
	235	interrupts = <0 81 4>;
	236	};
	237
	238	usb2: usb@5a820100 {
	239	compatible = "socionext,uniphier-ehci", "generic-ehci";
	240	status = "disabled";
	241	reg = <0x5a820100 0x100>;
	242	interrupts = <0 82 4>;
	243	};
	244
	245	usb3: usb@5a830100 {
	246	compatible = "socionext,uniphier-ehci", "generic-ehci";
	247	status = "disabled";
	248	reg = <0x5a830100 0x100>;
	249	interrupts = <0 83 4>;
	250	};
8e678e06 MY	251	};
8e678e06 MY	252	};