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474e5ac6 | 1 | /* |
77896e4d | 2 | * Device Tree Source for UniPhier Pro5 SoC |
474e5ac6 | 3 | * |
77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
474e5ac6 MY |
6 | * |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
2752bcaa | 46 | /include/ "skeleton.dtsi" |
474e5ac6 MY |
47 | |
48 | / { | |
77896e4d | 49 | compatible = "socionext,uniphier-pro5"; |
474e5ac6 MY |
50 | |
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
474e5ac6 MY |
54 | |
55 | cpu@0 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0>; | |
35167e27 | 59 | clocks = <&sys_clk 32>; |
3bdba5ac | 60 | enable-method = "psci"; |
7c62f299 | 61 | next-level-cache = <&l2>; |
35167e27 | 62 | operating-points-v2 = <&cpu_opp>; |
474e5ac6 MY |
63 | }; |
64 | ||
65 | cpu@1 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a9"; | |
68 | reg = <1>; | |
35167e27 | 69 | clocks = <&sys_clk 32>; |
3bdba5ac | 70 | enable-method = "psci"; |
7c62f299 | 71 | next-level-cache = <&l2>; |
35167e27 MY |
72 | operating-points-v2 = <&cpu_opp>; |
73 | }; | |
74 | }; | |
75 | ||
76 | cpu_opp: opp_table { | |
77 | compatible = "operating-points-v2"; | |
78 | opp-shared; | |
79 | ||
80 | opp@100000000 { | |
81 | opp-hz = /bits/ 64 <100000000>; | |
82 | clock-latency-ns = <300>; | |
83 | }; | |
84 | opp@116667000 { | |
85 | opp-hz = /bits/ 64 <116667000>; | |
86 | clock-latency-ns = <300>; | |
87 | }; | |
88 | opp@150000000 { | |
89 | opp-hz = /bits/ 64 <150000000>; | |
90 | clock-latency-ns = <300>; | |
91 | }; | |
92 | opp@175000000 { | |
93 | opp-hz = /bits/ 64 <175000000>; | |
94 | clock-latency-ns = <300>; | |
95 | }; | |
96 | opp@200000000 { | |
97 | opp-hz = /bits/ 64 <200000000>; | |
98 | clock-latency-ns = <300>; | |
99 | }; | |
100 | opp@233334000 { | |
101 | opp-hz = /bits/ 64 <233334000>; | |
102 | clock-latency-ns = <300>; | |
103 | }; | |
104 | opp@300000000 { | |
105 | opp-hz = /bits/ 64 <300000000>; | |
106 | clock-latency-ns = <300>; | |
107 | }; | |
108 | opp@350000000 { | |
109 | opp-hz = /bits/ 64 <350000000>; | |
110 | clock-latency-ns = <300>; | |
111 | }; | |
112 | opp@400000000 { | |
113 | opp-hz = /bits/ 64 <400000000>; | |
114 | clock-latency-ns = <300>; | |
115 | }; | |
116 | opp@466667000 { | |
117 | opp-hz = /bits/ 64 <466667000>; | |
118 | clock-latency-ns = <300>; | |
119 | }; | |
120 | opp@600000000 { | |
121 | opp-hz = /bits/ 64 <600000000>; | |
122 | clock-latency-ns = <300>; | |
123 | }; | |
124 | opp@700000000 { | |
125 | opp-hz = /bits/ 64 <700000000>; | |
126 | clock-latency-ns = <300>; | |
127 | }; | |
128 | opp@800000000 { | |
129 | opp-hz = /bits/ 64 <800000000>; | |
130 | clock-latency-ns = <300>; | |
131 | }; | |
132 | opp@933334000 { | |
133 | opp-hz = /bits/ 64 <933334000>; | |
134 | clock-latency-ns = <300>; | |
135 | }; | |
136 | opp@1200000000 { | |
137 | opp-hz = /bits/ 64 <1200000000>; | |
138 | clock-latency-ns = <300>; | |
139 | }; | |
140 | opp@1400000000 { | |
141 | opp-hz = /bits/ 64 <1400000000>; | |
142 | clock-latency-ns = <300>; | |
474e5ac6 MY |
143 | }; |
144 | }; | |
145 | ||
2752bcaa MY |
146 | psci { |
147 | compatible = "arm,psci-0.2"; | |
148 | method = "smc"; | |
149 | }; | |
150 | ||
474e5ac6 | 151 | clocks { |
2752bcaa MY |
152 | refclk: ref { |
153 | compatible = "fixed-clock"; | |
154 | #clock-cells = <0>; | |
155 | clock-frequency = <20000000>; | |
156 | }; | |
157 | ||
474e5ac6 MY |
158 | arm_timer_clk: arm_timer_clk { |
159 | #clock-cells = <0>; | |
160 | compatible = "fixed-clock"; | |
161 | clock-frequency = <50000000>; | |
162 | }; | |
474e5ac6 MY |
163 | }; |
164 | ||
2752bcaa MY |
165 | soc { |
166 | compatible = "simple-bus"; | |
167 | #address-cells = <1>; | |
168 | #size-cells = <1>; | |
169 | ranges; | |
170 | interrupt-parent = <&intc>; | |
474e5ac6 | 171 | |
2752bcaa MY |
172 | l2: l2-cache@500c0000 { |
173 | compatible = "socionext,uniphier-system-cache"; | |
174 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
175 | <0x506c0000 0x400>; | |
176 | interrupts = <0 190 4>, <0 191 4>; | |
177 | cache-unified; | |
178 | cache-size = <(2 * 1024 * 1024)>; | |
179 | cache-sets = <512>; | |
180 | cache-line-size = <128>; | |
181 | cache-level = <2>; | |
182 | next-level-cache = <&l3>; | |
183 | }; | |
474e5ac6 | 184 | |
2752bcaa MY |
185 | l3: l3-cache@500c8000 { |
186 | compatible = "socionext,uniphier-system-cache"; | |
187 | reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, | |
188 | <0x506c8000 0x400>; | |
189 | interrupts = <0 174 4>, <0 175 4>; | |
190 | cache-unified; | |
191 | cache-size = <(2 * 1024 * 1024)>; | |
192 | cache-sets = <512>; | |
193 | cache-line-size = <256>; | |
194 | cache-level = <3>; | |
195 | }; | |
474e5ac6 | 196 | |
2752bcaa MY |
197 | serial0: serial@54006800 { |
198 | compatible = "socionext,uniphier-uart"; | |
199 | status = "disabled"; | |
200 | reg = <0x54006800 0x40>; | |
201 | interrupts = <0 33 4>; | |
202 | pinctrl-names = "default"; | |
203 | pinctrl-0 = <&pinctrl_uart0>; | |
204 | clocks = <&peri_clk 0>; | |
205 | }; | |
474e5ac6 | 206 | |
2752bcaa MY |
207 | serial1: serial@54006900 { |
208 | compatible = "socionext,uniphier-uart"; | |
209 | status = "disabled"; | |
210 | reg = <0x54006900 0x40>; | |
211 | interrupts = <0 35 4>; | |
212 | pinctrl-names = "default"; | |
213 | pinctrl-0 = <&pinctrl_uart1>; | |
214 | clocks = <&peri_clk 1>; | |
215 | }; | |
474e5ac6 | 216 | |
2752bcaa MY |
217 | serial2: serial@54006a00 { |
218 | compatible = "socionext,uniphier-uart"; | |
219 | status = "disabled"; | |
220 | reg = <0x54006a00 0x40>; | |
221 | interrupts = <0 37 4>; | |
222 | pinctrl-names = "default"; | |
223 | pinctrl-0 = <&pinctrl_uart2>; | |
224 | clocks = <&peri_clk 2>; | |
225 | }; | |
474e5ac6 | 226 | |
2752bcaa MY |
227 | serial3: serial@54006b00 { |
228 | compatible = "socionext,uniphier-uart"; | |
229 | status = "disabled"; | |
230 | reg = <0x54006b00 0x40>; | |
231 | interrupts = <0 177 4>; | |
232 | pinctrl-names = "default"; | |
233 | pinctrl-0 = <&pinctrl_uart3>; | |
234 | clocks = <&peri_clk 3>; | |
235 | }; | |
474e5ac6 | 236 | |
2752bcaa MY |
237 | i2c0: i2c@58780000 { |
238 | compatible = "socionext,uniphier-fi2c"; | |
239 | status = "disabled"; | |
240 | reg = <0x58780000 0x80>; | |
241 | #address-cells = <1>; | |
242 | #size-cells = <0>; | |
243 | interrupts = <0 41 4>; | |
244 | pinctrl-names = "default"; | |
245 | pinctrl-0 = <&pinctrl_i2c0>; | |
246 | clocks = <&peri_clk 4>; | |
247 | clock-frequency = <100000>; | |
248 | }; | |
474e5ac6 | 249 | |
2752bcaa MY |
250 | i2c1: i2c@58781000 { |
251 | compatible = "socionext,uniphier-fi2c"; | |
252 | status = "disabled"; | |
253 | reg = <0x58781000 0x80>; | |
254 | #address-cells = <1>; | |
255 | #size-cells = <0>; | |
256 | interrupts = <0 42 4>; | |
257 | pinctrl-names = "default"; | |
258 | pinctrl-0 = <&pinctrl_i2c1>; | |
259 | clocks = <&peri_clk 5>; | |
260 | clock-frequency = <100000>; | |
261 | }; | |
474e5ac6 | 262 | |
2752bcaa MY |
263 | i2c2: i2c@58782000 { |
264 | compatible = "socionext,uniphier-fi2c"; | |
265 | status = "disabled"; | |
266 | reg = <0x58782000 0x80>; | |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | interrupts = <0 43 4>; | |
270 | pinctrl-names = "default"; | |
271 | pinctrl-0 = <&pinctrl_i2c2>; | |
272 | clocks = <&peri_clk 6>; | |
273 | clock-frequency = <100000>; | |
274 | }; | |
61f838c7 | 275 | |
2752bcaa MY |
276 | i2c3: i2c@58783000 { |
277 | compatible = "socionext,uniphier-fi2c"; | |
278 | status = "disabled"; | |
279 | reg = <0x58783000 0x80>; | |
280 | #address-cells = <1>; | |
281 | #size-cells = <0>; | |
282 | interrupts = <0 44 4>; | |
283 | pinctrl-names = "default"; | |
284 | pinctrl-0 = <&pinctrl_i2c3>; | |
285 | clocks = <&peri_clk 7>; | |
286 | clock-frequency = <100000>; | |
287 | }; | |
ad0561d4 | 288 | |
2752bcaa | 289 | /* i2c4 does not exist */ |
ad0561d4 | 290 | |
2752bcaa MY |
291 | /* chip-internal connection for DMD */ |
292 | i2c5: i2c@58785000 { | |
293 | compatible = "socionext,uniphier-fi2c"; | |
294 | reg = <0x58785000 0x80>; | |
295 | #address-cells = <1>; | |
296 | #size-cells = <0>; | |
297 | interrupts = <0 25 4>; | |
298 | clocks = <&peri_clk 9>; | |
299 | clock-frequency = <400000>; | |
300 | }; | |
ad0561d4 | 301 | |
2752bcaa MY |
302 | /* chip-internal connection for HDMI */ |
303 | i2c6: i2c@58786000 { | |
304 | compatible = "socionext,uniphier-fi2c"; | |
305 | reg = <0x58786000 0x80>; | |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | interrupts = <0 26 4>; | |
309 | clocks = <&peri_clk 10>; | |
310 | clock-frequency = <400000>; | |
311 | }; | |
ad0561d4 | 312 | |
2752bcaa MY |
313 | system_bus: system-bus@58c00000 { |
314 | compatible = "socionext,uniphier-system-bus"; | |
315 | status = "disabled"; | |
316 | reg = <0x58c00000 0x400>; | |
317 | #address-cells = <2>; | |
318 | #size-cells = <1>; | |
319 | pinctrl-names = "default"; | |
320 | pinctrl-0 = <&pinctrl_system_bus>; | |
321 | }; | |
ad0561d4 | 322 | |
2752bcaa MY |
323 | smpctrl@59800000 { |
324 | compatible = "socionext,uniphier-smpctrl"; | |
325 | reg = <0x59801000 0x400>; | |
326 | }; | |
327 | ||
328 | sdctrl@59810000 { | |
329 | compatible = "socionext,uniphier-pro5-sdctrl", | |
330 | "simple-mfd", "syscon"; | |
331 | reg = <0x59810000 0x800>; | |
332 | ||
333 | sd_clk: clock { | |
334 | compatible = "socionext,uniphier-pro5-sd-clock"; | |
335 | #clock-cells = <1>; | |
336 | }; | |
337 | ||
338 | sd_rst: reset { | |
339 | compatible = "socionext,uniphier-pro5-sd-reset"; | |
340 | #reset-cells = <1>; | |
341 | }; | |
342 | }; | |
ad0561d4 | 343 | |
2752bcaa MY |
344 | perictrl@59820000 { |
345 | compatible = "socionext,uniphier-pro5-perictrl", | |
346 | "simple-mfd", "syscon"; | |
347 | reg = <0x59820000 0x200>; | |
348 | ||
349 | peri_clk: clock { | |
350 | compatible = "socionext,uniphier-pro5-peri-clock"; | |
351 | #clock-cells = <1>; | |
352 | }; | |
353 | ||
354 | peri_rst: reset { | |
355 | compatible = "socionext,uniphier-pro5-peri-reset"; | |
356 | #reset-cells = <1>; | |
357 | }; | |
358 | }; | |
359 | ||
360 | soc-glue@5f800000 { | |
361 | compatible = "socionext,uniphier-pro5-soc-glue", | |
362 | "simple-mfd", "syscon"; | |
363 | reg = <0x5f800000 0x2000>; | |
364 | ||
365 | pinctrl: pinctrl { | |
366 | compatible = "socionext,uniphier-pro5-pinctrl"; | |
367 | }; | |
368 | }; | |
369 | ||
370 | timer@60000200 { | |
371 | compatible = "arm,cortex-a9-global-timer"; | |
372 | reg = <0x60000200 0x20>; | |
373 | interrupts = <1 11 0x304>; | |
374 | clocks = <&arm_timer_clk>; | |
375 | }; | |
376 | ||
377 | timer@60000600 { | |
378 | compatible = "arm,cortex-a9-twd-timer"; | |
379 | reg = <0x60000600 0x20>; | |
380 | interrupts = <1 13 0x304>; | |
381 | clocks = <&arm_timer_clk>; | |
382 | }; | |
383 | ||
384 | intc: interrupt-controller@60001000 { | |
385 | compatible = "arm,cortex-a9-gic"; | |
386 | reg = <0x60001000 0x1000>, | |
387 | <0x60000100 0x100>; | |
388 | #interrupt-cells = <3>; | |
389 | interrupt-controller; | |
390 | }; | |
391 | ||
392 | sysctrl@61840000 { | |
393 | compatible = "socionext,uniphier-pro5-sysctrl", | |
394 | "simple-mfd", "syscon"; | |
395 | reg = <0x61840000 0x10000>; | |
396 | ||
397 | sys_clk: clock { | |
398 | compatible = "socionext,uniphier-pro5-clock"; | |
399 | #clock-cells = <1>; | |
400 | }; | |
401 | ||
402 | sys_rst: reset { | |
403 | compatible = "socionext,uniphier-pro5-reset"; | |
404 | #reset-cells = <1>; | |
405 | }; | |
406 | }; | |
407 | }; | |
ad0561d4 | 408 | }; |
2752bcaa MY |
409 | |
410 | /include/ "uniphier-pinctrl.dtsi" |