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Commit | Line | Data |
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474e5ac6 | 1 | /* |
77896e4d | 2 | * Device Tree Source for UniPhier Pro5 SoC |
474e5ac6 | 3 | * |
77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
474e5ac6 MY |
6 | * |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
629b557a | 46 | /include/ "uniphier-common32.dtsi" |
474e5ac6 MY |
47 | |
48 | / { | |
77896e4d | 49 | compatible = "socionext,uniphier-pro5"; |
474e5ac6 MY |
50 | |
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
474e5ac6 MY |
54 | |
55 | cpu@0 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0>; | |
3bdba5ac | 59 | enable-method = "psci"; |
7c62f299 | 60 | next-level-cache = <&l2>; |
474e5ac6 MY |
61 | }; |
62 | ||
63 | cpu@1 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a9"; | |
66 | reg = <1>; | |
3bdba5ac | 67 | enable-method = "psci"; |
7c62f299 | 68 | next-level-cache = <&l2>; |
474e5ac6 MY |
69 | }; |
70 | }; | |
71 | ||
72 | clocks { | |
73 | arm_timer_clk: arm_timer_clk { | |
74 | #clock-cells = <0>; | |
75 | compatible = "fixed-clock"; | |
76 | clock-frequency = <50000000>; | |
77 | }; | |
474e5ac6 | 78 | }; |
629b557a | 79 | }; |
474e5ac6 | 80 | |
629b557a MY |
81 | &soc { |
82 | l2: l2-cache@500c0000 { | |
83 | compatible = "socionext,uniphier-system-cache"; | |
84 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; | |
85 | interrupts = <0 190 4>, <0 191 4>; | |
86 | cache-unified; | |
87 | cache-size = <(2 * 1024 * 1024)>; | |
88 | cache-sets = <512>; | |
89 | cache-line-size = <128>; | |
90 | cache-level = <2>; | |
91 | next-level-cache = <&l3>; | |
92 | }; | |
474e5ac6 | 93 | |
629b557a MY |
94 | l3: l3-cache@500c8000 { |
95 | compatible = "socionext,uniphier-system-cache"; | |
96 | reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; | |
97 | interrupts = <0 174 4>, <0 175 4>; | |
98 | cache-unified; | |
99 | cache-size = <(2 * 1024 * 1024)>; | |
100 | cache-sets = <512>; | |
101 | cache-line-size = <256>; | |
102 | cache-level = <3>; | |
103 | }; | |
474e5ac6 | 104 | |
629b557a MY |
105 | i2c0: i2c@58780000 { |
106 | compatible = "socionext,uniphier-fi2c"; | |
107 | status = "disabled"; | |
108 | reg = <0x58780000 0x80>; | |
109 | #address-cells = <1>; | |
110 | #size-cells = <0>; | |
111 | interrupts = <0 41 4>; | |
112 | pinctrl-names = "default"; | |
113 | pinctrl-0 = <&pinctrl_i2c0>; | |
ad0561d4 | 114 | clocks = <&peri_clk 4>; |
629b557a MY |
115 | clock-frequency = <100000>; |
116 | }; | |
474e5ac6 | 117 | |
629b557a MY |
118 | i2c1: i2c@58781000 { |
119 | compatible = "socionext,uniphier-fi2c"; | |
120 | status = "disabled"; | |
121 | reg = <0x58781000 0x80>; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <0>; | |
124 | interrupts = <0 42 4>; | |
125 | pinctrl-names = "default"; | |
126 | pinctrl-0 = <&pinctrl_i2c1>; | |
ad0561d4 | 127 | clocks = <&peri_clk 5>; |
629b557a MY |
128 | clock-frequency = <100000>; |
129 | }; | |
474e5ac6 | 130 | |
629b557a MY |
131 | i2c2: i2c@58782000 { |
132 | compatible = "socionext,uniphier-fi2c"; | |
133 | status = "disabled"; | |
134 | reg = <0x58782000 0x80>; | |
135 | #address-cells = <1>; | |
136 | #size-cells = <0>; | |
137 | interrupts = <0 43 4>; | |
138 | pinctrl-names = "default"; | |
139 | pinctrl-0 = <&pinctrl_i2c2>; | |
ad0561d4 | 140 | clocks = <&peri_clk 6>; |
629b557a MY |
141 | clock-frequency = <100000>; |
142 | }; | |
474e5ac6 | 143 | |
629b557a MY |
144 | i2c3: i2c@58783000 { |
145 | compatible = "socionext,uniphier-fi2c"; | |
146 | status = "disabled"; | |
147 | reg = <0x58783000 0x80>; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | interrupts = <0 44 4>; | |
151 | pinctrl-names = "default"; | |
152 | pinctrl-0 = <&pinctrl_i2c3>; | |
ad0561d4 | 153 | clocks = <&peri_clk 7>; |
629b557a MY |
154 | clock-frequency = <100000>; |
155 | }; | |
474e5ac6 | 156 | |
629b557a | 157 | /* i2c4 does not exist */ |
474e5ac6 | 158 | |
629b557a MY |
159 | /* chip-internal connection for DMD */ |
160 | i2c5: i2c@58785000 { | |
161 | compatible = "socionext,uniphier-fi2c"; | |
162 | reg = <0x58785000 0x80>; | |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
165 | interrupts = <0 25 4>; | |
ad0561d4 | 166 | clocks = <&peri_clk 9>; |
629b557a MY |
167 | clock-frequency = <400000>; |
168 | }; | |
474e5ac6 | 169 | |
629b557a MY |
170 | /* chip-internal connection for HDMI */ |
171 | i2c6: i2c@58786000 { | |
172 | compatible = "socionext,uniphier-fi2c"; | |
173 | reg = <0x58786000 0x80>; | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | interrupts = <0 26 4>; | |
ad0561d4 | 177 | clocks = <&peri_clk 10>; |
629b557a | 178 | clock-frequency = <400000>; |
474e5ac6 MY |
179 | }; |
180 | }; | |
181 | ||
61f838c7 MY |
182 | &refclk { |
183 | clock-frequency = <20000000>; | |
184 | }; | |
185 | ||
ad0561d4 | 186 | &mio_clk { |
1bdb60ef | 187 | compatible = "socionext,uniphier-pro5-sd-clock"; |
ad0561d4 MY |
188 | }; |
189 | ||
190 | &mio_rst { | |
1bdb60ef | 191 | compatible = "socionext,uniphier-pro5-sd-reset"; |
ad0561d4 MY |
192 | }; |
193 | ||
194 | &peri_clk { | |
195 | compatible = "socionext,uniphier-pro5-peri-clock"; | |
196 | }; | |
197 | ||
198 | &peri_rst { | |
199 | compatible = "socionext,uniphier-pro5-peri-reset"; | |
200 | }; | |
201 | ||
629b557a | 202 | &pinctrl { |
ebe161d3 | 203 | compatible = "socionext,uniphier-pro5-pinctrl"; |
629b557a | 204 | }; |
ad0561d4 MY |
205 | |
206 | &sys_clk { | |
207 | compatible = "socionext,uniphier-pro5-clock"; | |
208 | }; | |
209 | ||
210 | &sys_rst { | |
211 | compatible = "socionext,uniphier-pro5-reset"; | |
212 | }; |