[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / uniphier-sld3.dtsi

/*
 * Device Tree Source for UniPhier sLD3 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,uniphier-sld3";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24576000>;
		};

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		timer@20000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@20000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@20001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x20001000 0x1000>,
			      <0x20000100 0x100>;
		};

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(512 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			clocks = <&sys_clk 0>;
			fifo-size = <64>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			clocks = <&sys_clk 0>;
			fifo-size = <64>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			clocks = <&sys_clk 0>;
			fifo-size = <64>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58600000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58600000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			mio_clk: clock {
				compatible = "socionext,uniphier-sld3-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-sld3-mio-reset";
				#reset-cells = <1>;
			};
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 80 4>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 81 4>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 82 4>;
		};

		usb3: usb@5a830100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a830100 0x100>;
			interrupts = <0 83 4>;
		};

		sysctrl@f1840000 {
			compatible = "socionext,uniphier-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0xf1840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-sld3-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-sld3-reset";
				#reset-cells = <1>;
			};
		};
	};
};
Commit	Line	Data
8e678e06	1	/*
77896e4d	2	* Device Tree Source for UniPhier sLD3 SoC
8e678e06	3	*
77896e4d MY	4	* Copyright (C) 2015-2016 Socionext Inc.
77896e4d MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8e678e06 MY	6	*
	7	* This file is dual-licensed: you can use it either under the terms
	8	* of the GPL or the X11 license, at your option. Note that this dual
	9	* licensing only applies to this file, and not this project as a
	10	* whole.
	11	*
	12	* a) This file is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of the
	15	* License, or (at your option) any later version.
	16	*
	17	* This file is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* Or, alternatively,
	23	*
	24	* b) Permission is hereby granted, free of charge, to any person
	25	* obtaining a copy of this software and associated documentation
	26	* files (the "Software"), to deal in the Software without
	27	* restriction, including without limitation the rights to use,
	28	* copy, modify, merge, publish, distribute, sublicense, and/or
	29	* sell copies of the Software, and to permit persons to whom the
	30	* Software is furnished to do so, subject to the following
	31	* conditions:
	32	*
	33	* The above copyright notice and this permission notice shall be
	34	* included in all copies or substantial portions of the Software.
	35	*
	36	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	37	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	38	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	39	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	40	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	41	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	42	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	43	* OTHER DEALINGS IN THE SOFTWARE.
	44	*/
	45
	46	/include/ "skeleton.dtsi"
	47
	48	/ {
77896e4d	49	compatible = "socionext,uniphier-sld3";
8e678e06 MY	50
	51	cpus {
	52	#address-cells = <1>;
	53	#size-cells = <0>;
8e678e06 MY	54
	55	cpu@0 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	reg = <0>;
3bdba5ac	59	enable-method = "psci";
7c62f299	60	next-level-cache = <&l2>;
8e678e06 MY	61	};
	62
	63	cpu@1 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a9";
	66	reg = <1>;
3bdba5ac	67	enable-method = "psci";
7c62f299	68	next-level-cache = <&l2>;
8e678e06 MY	69	};
	70	};
	71
3bdba5ac MY	72	psci {
	73	compatible = "arm,psci-0.2";
	74	method = "smc";
	75	};
	76
8e678e06	77	clocks {
61f838c7 MY	78	refclk: ref {
	79	#clock-cells = <0>;
	80	compatible = "fixed-clock";
	81	clock-frequency = <24576000>;
	82	};
	83
8e678e06 MY	84	arm_timer_clk: arm_timer_clk {
	85	#clock-cells = <0>;
	86	compatible = "fixed-clock";
	87	clock-frequency = <50000000>;
	88	};
	89	};
	90
	91	soc {
	92	compatible = "simple-bus";
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
	96	interrupt-parent = <&intc>;
	97
8e678e06 MY	98	timer@20000200 {
	99	compatible = "arm,cortex-a9-global-timer";
	100	reg = <0x20000200 0x20>;
	101	interrupts = <1 11 0x304>;
	102	clocks = <&arm_timer_clk>;
	103	};
	104
	105	timer@20000600 {
	106	compatible = "arm,cortex-a9-twd-timer";
	107	reg = <0x20000600 0x20>;
	108	interrupts = <1 13 0x304>;
	109	clocks = <&arm_timer_clk>;
	110	};
	111
	112	intc: interrupt-controller@20001000 {
	113	compatible = "arm,cortex-a9-gic";
	114	#interrupt-cells = <3>;
	115	interrupt-controller;
	116	reg = <0x20001000 0x1000>,
	117	<0x20000100 0x100>;
	118	};
	119
7c62f299 MY	120	l2: l2-cache@500c0000 {
	121	compatible = "socionext,uniphier-system-cache";
	122	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	123	<0x506c0000 0x400>;
	124	interrupts = <0 174 4>, <0 175 4>;
	125	cache-unified;
	126	cache-size = <(512 * 1024)>;
	127	cache-sets = <256>;
	128	cache-line-size = <128>;
	129	cache-level = <2>;
	130	};
	131
1bf42507 MY	132	serial0: serial@54006800 {
	133	compatible = "socionext,uniphier-uart";
	134	status = "disabled";
	135	reg = <0x54006800 0x40>;
	136	interrupts = <0 33 4>;
ad0561d4	137	clocks = <&sys_clk 0>;
1bf42507 MY	138	fifo-size = <64>;
	139	};
	140
	141	serial1: serial@54006900 {
	142	compatible = "socionext,uniphier-uart";
	143	status = "disabled";
	144	reg = <0x54006900 0x40>;
	145	interrupts = <0 35 4>;
ad0561d4	146	clocks = <&sys_clk 0>;
1bf42507 MY	147	fifo-size = <64>;
	148	};
	149
	150	serial2: serial@54006a00 {
	151	compatible = "socionext,uniphier-uart";
	152	status = "disabled";
	153	reg = <0x54006a00 0x40>;
	154	interrupts = <0 37 4>;
ad0561d4	155	clocks = <&sys_clk 0>;
1bf42507 MY	156	fifo-size = <64>;
	157	};
	158
68f46897 MY	159	i2c0: i2c@58400000 {
	160	compatible = "socionext,uniphier-i2c";
	161	status = "disabled";
	162	reg = <0x58400000 0x40>;
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165	interrupts = <0 41 1>;
ad0561d4	166	clocks = <&sys_clk 1>;
68f46897 MY	167	clock-frequency = <100000>;
	168	};
	169
	170	i2c1: i2c@58480000 {
	171	compatible = "socionext,uniphier-i2c";
	172	status = "disabled";
	173	reg = <0x58480000 0x40>;
	174	#address-cells = <1>;
	175	#size-cells = <0>;
	176	interrupts = <0 42 1>;
ad0561d4	177	clocks = <&sys_clk 1>;
68f46897 MY	178	clock-frequency = <100000>;
	179	};
	180
	181	i2c2: i2c@58500000 {
	182	compatible = "socionext,uniphier-i2c";
	183	status = "disabled";
	184	reg = <0x58500000 0x40>;
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	interrupts = <0 43 1>;
ad0561d4	188	clocks = <&sys_clk 1>;
68f46897 MY	189	clock-frequency = <100000>;
	190	};
	191
	192	i2c3: i2c@58580000 {
	193	compatible = "socionext,uniphier-i2c";
	194	status = "disabled";
	195	reg = <0x58580000 0x40>;
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198	interrupts = <0 44 1>;
ad0561d4	199	clocks = <&sys_clk 1>;
68f46897 MY	200	clock-frequency = <100000>;
	201	};
	202
	203	/* chip-internal connection for DMD */
	204	i2c4: i2c@58600000 {
	205	compatible = "socionext,uniphier-i2c";
	206	reg = <0x58600000 0x40>;
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	interrupts = <0 45 1>;
ad0561d4	210	clocks = <&sys_clk 1>;
68f46897 MY	211	clock-frequency = <400000>;
	212	};
	213
14bae133 MY	214	system_bus: system-bus@58c00000 {
	215	compatible = "socionext,uniphier-system-bus";
	216	status = "disabled";
	217	reg = <0x58c00000 0x400>;
	218	#address-cells = <2>;
	219	#size-cells = <1>;
	220	};
	221
	222	smpctrl@59800000 {
	223	compatible = "socionext,uniphier-smpctrl";
	224	reg = <0x59801000 0x400>;
8e678e06	225	};
3fbf02a8	226
ad0561d4 MY	227	mioctrl@59810000 {
	228	compatible = "socionext,uniphier-mioctrl",
	229	"simple-mfd", "syscon";
	230	reg = <0x59810000 0x800>;
	231
	232	mio_clk: clock {
	233	compatible = "socionext,uniphier-sld3-mio-clock";
	234	#clock-cells = <1>;
	235	};
	236
	237	mio_rst: reset {
	238	compatible = "socionext,uniphier-sld3-mio-reset";
	239	#reset-cells = <1>;
	240	};
	241	};
	242
3fbf02a8 MY	243	usb0: usb@5a800100 {
	244	compatible = "socionext,uniphier-ehci", "generic-ehci";
	245	status = "disabled";
	246	reg = <0x5a800100 0x100>;
	247	interrupts = <0 80 4>;
	248	};
	249
	250	usb1: usb@5a810100 {
	251	compatible = "socionext,uniphier-ehci", "generic-ehci";
	252	status = "disabled";
	253	reg = <0x5a810100 0x100>;
	254	interrupts = <0 81 4>;
	255	};
	256
	257	usb2: usb@5a820100 {
	258	compatible = "socionext,uniphier-ehci", "generic-ehci";
	259	status = "disabled";
	260	reg = <0x5a820100 0x100>;
	261	interrupts = <0 82 4>;
	262	};
	263
	264	usb3: usb@5a830100 {
	265	compatible = "socionext,uniphier-ehci", "generic-ehci";
	266	status = "disabled";
	267	reg = <0x5a830100 0x100>;
	268	interrupts = <0 83 4>;
	269	};
ad0561d4 MY	270
	271	sysctrl@f1840000 {
	272	compatible = "socionext,uniphier-sysctrl",
	273	"simple-mfd", "syscon";
6c0dceaa	274	reg = <0xf1840000 0x10000>;
ad0561d4 MY	275
	276	sys_clk: clock {
	277	compatible = "socionext,uniphier-sld3-clock";
	278	#clock-cells = <1>;
	279	};
	280
	281	sys_rst: reset {
	282	compatible = "socionext,uniphier-sld3-reset";
	283	#reset-cells = <1>;
	284	};
	285	};
8e678e06 MY	286	};
8e678e06 MY	287	};