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Commit | Line | Data |
---|---|---|
375faa93 PM |
1 | /* |
2 | * ARM Ltd. Versatile Express | |
3 | * | |
4 | * CoreTile Express A15x2 A7x3 | |
5 | * Cortex-A15_A7 MPCore (V2P-CA15_A7) | |
6 | * | |
7 | * HBI-0249A | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | / { | |
13 | model = "V2P-CA15_CA7"; | |
14 | arm,hbi = <0x249>; | |
842839a3 | 15 | arm,vexpress,site = <0xf>; |
375faa93 PM |
16 | compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; |
17 | interrupt-parent = <&gic>; | |
18 | #address-cells = <2>; | |
19 | #size-cells = <2>; | |
20 | ||
21 | chosen { }; | |
22 | ||
23 | aliases { | |
24 | serial0 = &v2m_serial0; | |
25 | serial1 = &v2m_serial1; | |
26 | serial2 = &v2m_serial2; | |
27 | serial3 = &v2m_serial3; | |
28 | i2c0 = &v2m_i2c_dvi; | |
29 | i2c1 = &v2m_i2c_pcie; | |
30 | }; | |
31 | ||
32 | cpus { | |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | ||
36 | cpu0: cpu@0 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a15"; | |
39 | reg = <0>; | |
a2bdc32a | 40 | cci-control-port = <&cci_control1>; |
d2e5c871 | 41 | cpu-idle-states = <&CLUSTER_SLEEP_BIG>; |
375faa93 PM |
42 | }; |
43 | ||
44 | cpu1: cpu@1 { | |
45 | device_type = "cpu"; | |
46 | compatible = "arm,cortex-a15"; | |
47 | reg = <1>; | |
a2bdc32a | 48 | cci-control-port = <&cci_control1>; |
d2e5c871 | 49 | cpu-idle-states = <&CLUSTER_SLEEP_BIG>; |
375faa93 PM |
50 | }; |
51 | ||
375faa93 PM |
52 | cpu2: cpu@2 { |
53 | device_type = "cpu"; | |
54 | compatible = "arm,cortex-a7"; | |
55 | reg = <0x100>; | |
a2bdc32a | 56 | cci-control-port = <&cci_control2>; |
d2e5c871 | 57 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
375faa93 PM |
58 | }; |
59 | ||
60 | cpu3: cpu@3 { | |
61 | device_type = "cpu"; | |
62 | compatible = "arm,cortex-a7"; | |
63 | reg = <0x101>; | |
a2bdc32a | 64 | cci-control-port = <&cci_control2>; |
d2e5c871 | 65 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
375faa93 PM |
66 | }; |
67 | ||
68 | cpu4: cpu@4 { | |
69 | device_type = "cpu"; | |
70 | compatible = "arm,cortex-a7"; | |
71 | reg = <0x102>; | |
a2bdc32a | 72 | cci-control-port = <&cci_control2>; |
d2e5c871 LP |
73 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
74 | }; | |
75 | ||
76 | idle-states { | |
77 | CLUSTER_SLEEP_BIG: cluster-sleep-big { | |
78 | compatible = "arm,idle-state"; | |
79 | local-timer-stop; | |
80 | entry-latency-us = <1000>; | |
81 | exit-latency-us = <700>; | |
82 | min-residency-us = <2000>; | |
83 | }; | |
84 | ||
85 | CLUSTER_SLEEP_LITTLE: cluster-sleep-little { | |
86 | compatible = "arm,idle-state"; | |
87 | local-timer-stop; | |
88 | entry-latency-us = <1000>; | |
89 | exit-latency-us = <500>; | |
90 | min-residency-us = <2500>; | |
91 | }; | |
375faa93 | 92 | }; |
375faa93 PM |
93 | }; |
94 | ||
95 | memory@80000000 { | |
96 | device_type = "memory"; | |
97 | reg = <0 0x80000000 0 0x40000000>; | |
98 | }; | |
99 | ||
100 | wdt@2a490000 { | |
101 | compatible = "arm,sp805", "arm,primecell"; | |
102 | reg = <0 0x2a490000 0 0x1000>; | |
aab7da70 | 103 | interrupts = <0 98 4>; |
842839a3 PM |
104 | clocks = <&oscclk6a>, <&oscclk6a>; |
105 | clock-names = "wdogclk", "apb_pclk"; | |
375faa93 PM |
106 | }; |
107 | ||
108 | hdlcd@2b000000 { | |
109 | compatible = "arm,hdlcd"; | |
110 | reg = <0 0x2b000000 0 0x1000>; | |
111 | interrupts = <0 85 4>; | |
842839a3 PM |
112 | clocks = <&oscclk5>; |
113 | clock-names = "pxlclk"; | |
375faa93 PM |
114 | }; |
115 | ||
116 | memory-controller@2b0a0000 { | |
117 | compatible = "arm,pl341", "arm,primecell"; | |
118 | reg = <0 0x2b0a0000 0 0x1000>; | |
842839a3 PM |
119 | clocks = <&oscclk6a>; |
120 | clock-names = "apb_pclk"; | |
375faa93 PM |
121 | }; |
122 | ||
123 | gic: interrupt-controller@2c001000 { | |
124 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
125 | #interrupt-cells = <3>; | |
126 | #address-cells = <0>; | |
127 | interrupt-controller; | |
128 | reg = <0 0x2c001000 0 0x1000>, | |
129 | <0 0x2c002000 0 0x1000>, | |
130 | <0 0x2c004000 0 0x2000>, | |
131 | <0 0x2c006000 0 0x2000>; | |
132 | interrupts = <1 9 0xf04>; | |
133 | }; | |
134 | ||
a2bdc32a JMT |
135 | cci@2c090000 { |
136 | compatible = "arm,cci-400"; | |
137 | #address-cells = <1>; | |
138 | #size-cells = <1>; | |
139 | reg = <0 0x2c090000 0 0x1000>; | |
140 | ranges = <0x0 0x0 0x2c090000 0x10000>; | |
141 | ||
142 | cci_control1: slave-if@4000 { | |
143 | compatible = "arm,cci-400-ctrl-if"; | |
144 | interface-type = "ace"; | |
145 | reg = <0x4000 0x1000>; | |
146 | }; | |
147 | ||
148 | cci_control2: slave-if@5000 { | |
149 | compatible = "arm,cci-400-ctrl-if"; | |
150 | interface-type = "ace"; | |
151 | reg = <0x5000 0x1000>; | |
152 | }; | |
153 | }; | |
154 | ||
375faa93 PM |
155 | memory-controller@7ffd0000 { |
156 | compatible = "arm,pl354", "arm,primecell"; | |
157 | reg = <0 0x7ffd0000 0 0x1000>; | |
158 | interrupts = <0 86 4>, | |
159 | <0 87 4>; | |
842839a3 PM |
160 | clocks = <&oscclk6a>; |
161 | clock-names = "apb_pclk"; | |
375faa93 PM |
162 | }; |
163 | ||
164 | dma@7ff00000 { | |
165 | compatible = "arm,pl330", "arm,primecell"; | |
166 | reg = <0 0x7ff00000 0 0x1000>; | |
167 | interrupts = <0 92 4>, | |
168 | <0 88 4>, | |
169 | <0 89 4>, | |
170 | <0 90 4>, | |
171 | <0 91 4>; | |
842839a3 PM |
172 | clocks = <&oscclk6a>; |
173 | clock-names = "apb_pclk"; | |
375faa93 PM |
174 | }; |
175 | ||
ceca0e1c PM |
176 | scc@7fff0000 { |
177 | compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; | |
178 | reg = <0 0x7fff0000 0 0x1000>; | |
179 | interrupts = <0 95 4>; | |
180 | }; | |
181 | ||
375faa93 PM |
182 | timer { |
183 | compatible = "arm,armv7-timer"; | |
184 | interrupts = <1 13 0xf08>, | |
185 | <1 14 0xf08>, | |
186 | <1 11 0xf08>, | |
187 | <1 10 0xf08>; | |
188 | }; | |
189 | ||
190 | pmu { | |
7e16063b | 191 | compatible = "arm,cortex-a15-pmu"; |
375faa93 PM |
192 | interrupts = <0 68 4>, |
193 | <0 69 4>; | |
194 | }; | |
195 | ||
842839a3 PM |
196 | oscclk6a: oscclk6a { |
197 | /* Reference 24MHz clock */ | |
198 | compatible = "fixed-clock"; | |
199 | #clock-cells = <0>; | |
200 | clock-frequency = <24000000>; | |
201 | clock-output-names = "oscclk6a"; | |
202 | }; | |
203 | ||
204 | dcc { | |
205 | compatible = "arm,vexpress,config-bus"; | |
206 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
207 | ||
208 | osc@0 { | |
209 | /* A15 PLL 0 reference clock */ | |
210 | compatible = "arm,vexpress-osc"; | |
211 | arm,vexpress-sysreg,func = <1 0>; | |
212 | freq-range = <17000000 50000000>; | |
213 | #clock-cells = <0>; | |
214 | clock-output-names = "oscclk0"; | |
215 | }; | |
216 | ||
217 | osc@1 { | |
218 | /* A15 PLL 1 reference clock */ | |
219 | compatible = "arm,vexpress-osc"; | |
220 | arm,vexpress-sysreg,func = <1 1>; | |
221 | freq-range = <17000000 50000000>; | |
222 | #clock-cells = <0>; | |
223 | clock-output-names = "oscclk1"; | |
224 | }; | |
225 | ||
226 | osc@2 { | |
227 | /* A7 PLL 0 reference clock */ | |
228 | compatible = "arm,vexpress-osc"; | |
229 | arm,vexpress-sysreg,func = <1 2>; | |
230 | freq-range = <17000000 50000000>; | |
231 | #clock-cells = <0>; | |
232 | clock-output-names = "oscclk2"; | |
233 | }; | |
234 | ||
235 | osc@3 { | |
236 | /* A7 PLL 1 reference clock */ | |
237 | compatible = "arm,vexpress-osc"; | |
238 | arm,vexpress-sysreg,func = <1 3>; | |
239 | freq-range = <17000000 50000000>; | |
240 | #clock-cells = <0>; | |
241 | clock-output-names = "oscclk3"; | |
242 | }; | |
243 | ||
244 | osc@4 { | |
245 | /* External AXI master clock */ | |
246 | compatible = "arm,vexpress-osc"; | |
247 | arm,vexpress-sysreg,func = <1 4>; | |
248 | freq-range = <20000000 40000000>; | |
249 | #clock-cells = <0>; | |
250 | clock-output-names = "oscclk4"; | |
251 | }; | |
252 | ||
253 | oscclk5: osc@5 { | |
254 | /* HDLCD PLL reference clock */ | |
255 | compatible = "arm,vexpress-osc"; | |
256 | arm,vexpress-sysreg,func = <1 5>; | |
257 | freq-range = <23750000 165000000>; | |
258 | #clock-cells = <0>; | |
259 | clock-output-names = "oscclk5"; | |
260 | }; | |
261 | ||
262 | smbclk: osc@6 { | |
263 | /* Static memory controller clock */ | |
264 | compatible = "arm,vexpress-osc"; | |
265 | arm,vexpress-sysreg,func = <1 6>; | |
266 | freq-range = <20000000 40000000>; | |
267 | #clock-cells = <0>; | |
268 | clock-output-names = "oscclk6"; | |
269 | }; | |
270 | ||
271 | osc@7 { | |
272 | /* SYS PLL reference clock */ | |
273 | compatible = "arm,vexpress-osc"; | |
274 | arm,vexpress-sysreg,func = <1 7>; | |
275 | freq-range = <17000000 50000000>; | |
276 | #clock-cells = <0>; | |
277 | clock-output-names = "oscclk7"; | |
278 | }; | |
279 | ||
280 | osc@8 { | |
281 | /* DDR2 PLL reference clock */ | |
282 | compatible = "arm,vexpress-osc"; | |
283 | arm,vexpress-sysreg,func = <1 8>; | |
284 | freq-range = <20000000 50000000>; | |
285 | #clock-cells = <0>; | |
286 | clock-output-names = "oscclk8"; | |
287 | }; | |
288 | ||
289 | volt@0 { | |
290 | /* A15 CPU core voltage */ | |
291 | compatible = "arm,vexpress-volt"; | |
292 | arm,vexpress-sysreg,func = <2 0>; | |
293 | regulator-name = "A15 Vcore"; | |
294 | regulator-min-microvolt = <800000>; | |
295 | regulator-max-microvolt = <1050000>; | |
296 | regulator-always-on; | |
297 | label = "A15 Vcore"; | |
298 | }; | |
299 | ||
300 | volt@1 { | |
301 | /* A7 CPU core voltage */ | |
302 | compatible = "arm,vexpress-volt"; | |
303 | arm,vexpress-sysreg,func = <2 1>; | |
304 | regulator-name = "A7 Vcore"; | |
305 | regulator-min-microvolt = <800000>; | |
306 | regulator-max-microvolt = <1050000>; | |
307 | regulator-always-on; | |
308 | label = "A7 Vcore"; | |
309 | }; | |
310 | ||
311 | amp@0 { | |
312 | /* Total current for the two A15 cores */ | |
313 | compatible = "arm,vexpress-amp"; | |
314 | arm,vexpress-sysreg,func = <3 0>; | |
315 | label = "A15 Icore"; | |
316 | }; | |
317 | ||
318 | amp@1 { | |
319 | /* Total current for the three A7 cores */ | |
320 | compatible = "arm,vexpress-amp"; | |
321 | arm,vexpress-sysreg,func = <3 1>; | |
322 | label = "A7 Icore"; | |
323 | }; | |
324 | ||
325 | temp@0 { | |
326 | /* DCC internal temperature */ | |
327 | compatible = "arm,vexpress-temp"; | |
328 | arm,vexpress-sysreg,func = <4 0>; | |
329 | label = "DCC"; | |
330 | }; | |
331 | ||
332 | power@0 { | |
333 | /* Total power for the two A15 cores */ | |
334 | compatible = "arm,vexpress-power"; | |
335 | arm,vexpress-sysreg,func = <12 0>; | |
336 | label = "A15 Pcore"; | |
337 | }; | |
3b9334ac | 338 | |
842839a3 PM |
339 | power@1 { |
340 | /* Total power for the three A7 cores */ | |
341 | compatible = "arm,vexpress-power"; | |
342 | arm,vexpress-sysreg,func = <12 1>; | |
343 | label = "A7 Pcore"; | |
344 | }; | |
345 | ||
346 | energy@0 { | |
347 | /* Total energy for the two A15 cores */ | |
348 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 349 | arm,vexpress-sysreg,func = <13 0>, <13 1>; |
842839a3 PM |
350 | label = "A15 Jcore"; |
351 | }; | |
352 | ||
353 | energy@2 { | |
354 | /* Total energy for the three A7 cores */ | |
355 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 356 | arm,vexpress-sysreg,func = <13 2>, <13 3>; |
842839a3 PM |
357 | label = "A7 Jcore"; |
358 | }; | |
359 | }; | |
360 | ||
0bec8d82 MP |
361 | etb@0,20010000 { |
362 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
363 | reg = <0 0x20010000 0 0x1000>; | |
364 | ||
0bec8d82 MP |
365 | clocks = <&oscclk6a>; |
366 | clock-names = "apb_pclk"; | |
367 | port { | |
368 | etb_in_port: endpoint@0 { | |
369 | slave-mode; | |
370 | remote-endpoint = <&replicator_out_port0>; | |
371 | }; | |
372 | }; | |
373 | }; | |
374 | ||
375 | tpiu@0,20030000 { | |
376 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
377 | reg = <0 0x20030000 0 0x1000>; | |
378 | ||
379 | clocks = <&oscclk6a>; | |
380 | clock-names = "apb_pclk"; | |
381 | port { | |
382 | tpiu_in_port: endpoint@0 { | |
383 | slave-mode; | |
384 | remote-endpoint = <&replicator_out_port1>; | |
385 | }; | |
386 | }; | |
387 | }; | |
388 | ||
389 | replicator { | |
390 | /* non-configurable replicators don't show up on the | |
391 | * AMBA bus. As such no need to add "arm,primecell". | |
392 | */ | |
393 | compatible = "arm,coresight-replicator"; | |
394 | ||
395 | ports { | |
396 | #address-cells = <1>; | |
397 | #size-cells = <0>; | |
398 | ||
399 | /* replicator output ports */ | |
400 | port@0 { | |
401 | reg = <0>; | |
402 | replicator_out_port0: endpoint { | |
403 | remote-endpoint = <&etb_in_port>; | |
404 | }; | |
405 | }; | |
406 | ||
407 | port@1 { | |
408 | reg = <1>; | |
409 | replicator_out_port1: endpoint { | |
410 | remote-endpoint = <&tpiu_in_port>; | |
411 | }; | |
412 | }; | |
413 | ||
414 | /* replicator input port */ | |
415 | port@2 { | |
416 | reg = <0>; | |
417 | replicator_in_port0: endpoint { | |
418 | slave-mode; | |
419 | remote-endpoint = <&funnel_out_port0>; | |
420 | }; | |
421 | }; | |
422 | }; | |
423 | }; | |
424 | ||
425 | funnel@0,20040000 { | |
426 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
427 | reg = <0 0x20040000 0 0x1000>; | |
428 | ||
429 | clocks = <&oscclk6a>; | |
430 | clock-names = "apb_pclk"; | |
431 | ports { | |
432 | #address-cells = <1>; | |
433 | #size-cells = <0>; | |
434 | ||
435 | /* funnel output port */ | |
436 | port@0 { | |
437 | reg = <0>; | |
438 | funnel_out_port0: endpoint { | |
439 | remote-endpoint = | |
440 | <&replicator_in_port0>; | |
441 | }; | |
442 | }; | |
443 | ||
444 | /* funnel input ports */ | |
445 | port@1 { | |
446 | reg = <0>; | |
447 | funnel_in_port0: endpoint { | |
448 | slave-mode; | |
449 | remote-endpoint = <&ptm0_out_port>; | |
450 | }; | |
451 | }; | |
452 | ||
453 | port@2 { | |
454 | reg = <1>; | |
455 | funnel_in_port1: endpoint { | |
456 | slave-mode; | |
457 | remote-endpoint = <&ptm1_out_port>; | |
458 | }; | |
459 | }; | |
460 | ||
461 | port@3 { | |
462 | reg = <2>; | |
463 | funnel_in_port2: endpoint { | |
464 | slave-mode; | |
465 | remote-endpoint = <&etm0_out_port>; | |
466 | }; | |
467 | }; | |
468 | ||
469 | /* Input port #3 is for ITM, not supported here */ | |
470 | ||
471 | port@4 { | |
472 | reg = <4>; | |
473 | funnel_in_port4: endpoint { | |
474 | slave-mode; | |
475 | remote-endpoint = <&etm1_out_port>; | |
476 | }; | |
477 | }; | |
478 | ||
479 | port@5 { | |
480 | reg = <5>; | |
481 | funnel_in_port5: endpoint { | |
482 | slave-mode; | |
483 | remote-endpoint = <&etm2_out_port>; | |
484 | }; | |
485 | }; | |
486 | }; | |
487 | }; | |
488 | ||
489 | ptm@0,2201c000 { | |
490 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
491 | reg = <0 0x2201c000 0 0x1000>; | |
492 | ||
493 | cpu = <&cpu0>; | |
494 | clocks = <&oscclk6a>; | |
495 | clock-names = "apb_pclk"; | |
496 | port { | |
497 | ptm0_out_port: endpoint { | |
498 | remote-endpoint = <&funnel_in_port0>; | |
499 | }; | |
500 | }; | |
501 | }; | |
502 | ||
503 | ptm@0,2201d000 { | |
504 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
505 | reg = <0 0x2201d000 0 0x1000>; | |
506 | ||
507 | cpu = <&cpu1>; | |
508 | clocks = <&oscclk6a>; | |
509 | clock-names = "apb_pclk"; | |
510 | port { | |
511 | ptm1_out_port: endpoint { | |
512 | remote-endpoint = <&funnel_in_port1>; | |
513 | }; | |
514 | }; | |
515 | }; | |
516 | ||
517 | etm@0,2203c000 { | |
518 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
519 | reg = <0 0x2203c000 0 0x1000>; | |
520 | ||
521 | cpu = <&cpu2>; | |
522 | clocks = <&oscclk6a>; | |
523 | clock-names = "apb_pclk"; | |
524 | port { | |
525 | etm0_out_port: endpoint { | |
526 | remote-endpoint = <&funnel_in_port2>; | |
527 | }; | |
528 | }; | |
529 | }; | |
530 | ||
531 | etm@0,2203d000 { | |
532 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
533 | reg = <0 0x2203d000 0 0x1000>; | |
534 | ||
535 | cpu = <&cpu3>; | |
536 | clocks = <&oscclk6a>; | |
537 | clock-names = "apb_pclk"; | |
538 | port { | |
539 | etm1_out_port: endpoint { | |
540 | remote-endpoint = <&funnel_in_port4>; | |
541 | }; | |
542 | }; | |
543 | }; | |
544 | ||
545 | etm@0,2203e000 { | |
546 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
547 | reg = <0 0x2203e000 0 0x1000>; | |
548 | ||
549 | cpu = <&cpu4>; | |
550 | clocks = <&oscclk6a>; | |
551 | clock-names = "apb_pclk"; | |
552 | port { | |
553 | etm2_out_port: endpoint { | |
554 | remote-endpoint = <&funnel_in_port5>; | |
555 | }; | |
556 | }; | |
557 | }; | |
558 | ||
433683a6 PM |
559 | smb { |
560 | compatible = "simple-bus"; | |
561 | ||
562 | #address-cells = <2>; | |
563 | #size-cells = <1>; | |
375faa93 PM |
564 | ranges = <0 0 0 0x08000000 0x04000000>, |
565 | <1 0 0 0x14000000 0x04000000>, | |
566 | <2 0 0 0x18000000 0x04000000>, | |
567 | <3 0 0 0x1c000000 0x04000000>, | |
568 | <4 0 0 0x0c000000 0x04000000>, | |
569 | <5 0 0 0x10000000 0x04000000>; | |
570 | ||
433683a6 | 571 | #interrupt-cells = <1>; |
375faa93 PM |
572 | interrupt-map-mask = <0 0 63>; |
573 | interrupt-map = <0 0 0 &gic 0 0 4>, | |
574 | <0 0 1 &gic 0 1 4>, | |
575 | <0 0 2 &gic 0 2 4>, | |
576 | <0 0 3 &gic 0 3 4>, | |
577 | <0 0 4 &gic 0 4 4>, | |
578 | <0 0 5 &gic 0 5 4>, | |
579 | <0 0 6 &gic 0 6 4>, | |
580 | <0 0 7 &gic 0 7 4>, | |
581 | <0 0 8 &gic 0 8 4>, | |
582 | <0 0 9 &gic 0 9 4>, | |
583 | <0 0 10 &gic 0 10 4>, | |
584 | <0 0 11 &gic 0 11 4>, | |
585 | <0 0 12 &gic 0 12 4>, | |
586 | <0 0 13 &gic 0 13 4>, | |
587 | <0 0 14 &gic 0 14 4>, | |
588 | <0 0 15 &gic 0 15 4>, | |
589 | <0 0 16 &gic 0 16 4>, | |
590 | <0 0 17 &gic 0 17 4>, | |
591 | <0 0 18 &gic 0 18 4>, | |
592 | <0 0 19 &gic 0 19 4>, | |
593 | <0 0 20 &gic 0 20 4>, | |
594 | <0 0 21 &gic 0 21 4>, | |
595 | <0 0 22 &gic 0 22 4>, | |
596 | <0 0 23 &gic 0 23 4>, | |
597 | <0 0 24 &gic 0 24 4>, | |
598 | <0 0 25 &gic 0 25 4>, | |
599 | <0 0 26 &gic 0 26 4>, | |
600 | <0 0 27 &gic 0 27 4>, | |
601 | <0 0 28 &gic 0 28 4>, | |
602 | <0 0 29 &gic 0 29 4>, | |
603 | <0 0 30 &gic 0 30 4>, | |
604 | <0 0 31 &gic 0 31 4>, | |
605 | <0 0 32 &gic 0 32 4>, | |
606 | <0 0 33 &gic 0 33 4>, | |
607 | <0 0 34 &gic 0 34 4>, | |
608 | <0 0 35 &gic 0 35 4>, | |
609 | <0 0 36 &gic 0 36 4>, | |
610 | <0 0 37 &gic 0 37 4>, | |
611 | <0 0 38 &gic 0 38 4>, | |
612 | <0 0 39 &gic 0 39 4>, | |
613 | <0 0 40 &gic 0 40 4>, | |
614 | <0 0 41 &gic 0 41 4>, | |
615 | <0 0 42 &gic 0 42 4>; | |
433683a6 PM |
616 | |
617 | /include/ "vexpress-v2m-rs1.dtsi" | |
375faa93 PM |
618 | }; |
619 | }; |