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Commit | Line | Data |
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bfd5200c PM |
1 | /* |
2 | * ARM Ltd. Versatile Express | |
3 | * | |
4 | * CoreTile Express A5x2 | |
5 | * Cortex-A5 MPCore (V2P-CA5s) | |
6 | * | |
7 | * HBI-0225B | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | / { | |
13 | model = "V2P-CA5s"; | |
14 | arm,hbi = <0x225>; | |
842839a3 | 15 | arm,vexpress,site = <0xf>; |
bfd5200c PM |
16 | compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; |
17 | interrupt-parent = <&gic>; | |
18 | #address-cells = <1>; | |
19 | #size-cells = <1>; | |
20 | ||
21 | chosen { }; | |
22 | ||
23 | aliases { | |
24 | serial0 = &v2m_serial0; | |
25 | serial1 = &v2m_serial1; | |
26 | serial2 = &v2m_serial2; | |
27 | serial3 = &v2m_serial3; | |
28 | i2c0 = &v2m_i2c_dvi; | |
29 | i2c1 = &v2m_i2c_pcie; | |
30 | }; | |
31 | ||
32 | cpus { | |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | ||
36 | cpu@0 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a5"; | |
39 | reg = <0>; | |
40 | next-level-cache = <&L2>; | |
41 | }; | |
42 | ||
43 | cpu@1 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a5"; | |
46 | reg = <1>; | |
47 | next-level-cache = <&L2>; | |
48 | }; | |
49 | }; | |
50 | ||
51 | memory@80000000 { | |
52 | device_type = "memory"; | |
53 | reg = <0x80000000 0x40000000>; | |
54 | }; | |
55 | ||
56 | hdlcd@2a110000 { | |
57 | compatible = "arm,hdlcd"; | |
58 | reg = <0x2a110000 0x1000>; | |
59 | interrupts = <0 85 4>; | |
842839a3 PM |
60 | clocks = <&oscclk3>; |
61 | clock-names = "pxlclk"; | |
bfd5200c PM |
62 | }; |
63 | ||
64 | memory-controller@2a150000 { | |
65 | compatible = "arm,pl341", "arm,primecell"; | |
66 | reg = <0x2a150000 0x1000>; | |
842839a3 PM |
67 | clocks = <&oscclk1>; |
68 | clock-names = "apb_pclk"; | |
bfd5200c PM |
69 | }; |
70 | ||
71 | memory-controller@2a190000 { | |
72 | compatible = "arm,pl354", "arm,primecell"; | |
73 | reg = <0x2a190000 0x1000>; | |
74 | interrupts = <0 86 4>, | |
75 | <0 87 4>; | |
842839a3 PM |
76 | clocks = <&oscclk1>; |
77 | clock-names = "apb_pclk"; | |
bfd5200c PM |
78 | }; |
79 | ||
80 | scu@2c000000 { | |
81 | compatible = "arm,cortex-a5-scu"; | |
82 | reg = <0x2c000000 0x58>; | |
83 | }; | |
84 | ||
85 | timer@2c000600 { | |
86 | compatible = "arm,cortex-a5-twd-timer"; | |
e29b65db PM |
87 | reg = <0x2c000600 0x20>; |
88 | interrupts = <1 13 0x304>; | |
89 | }; | |
90 | ||
91 | watchdog@2c000620 { | |
92 | compatible = "arm,cortex-a5-twd-wdt"; | |
93 | reg = <0x2c000620 0x20>; | |
94 | interrupts = <1 14 0x304>; | |
bfd5200c PM |
95 | }; |
96 | ||
97 | gic: interrupt-controller@2c001000 { | |
e29b65db | 98 | compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; |
bfd5200c PM |
99 | #interrupt-cells = <3>; |
100 | #address-cells = <0>; | |
101 | interrupt-controller; | |
102 | reg = <0x2c001000 0x1000>, | |
103 | <0x2c000100 0x100>; | |
104 | }; | |
105 | ||
106 | L2: cache-controller@2c0f0000 { | |
107 | compatible = "arm,pl310-cache"; | |
108 | reg = <0x2c0f0000 0x1000>; | |
109 | interrupts = <0 84 4>; | |
110 | cache-level = <2>; | |
111 | }; | |
112 | ||
113 | pmu { | |
114 | compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; | |
115 | interrupts = <0 68 4>, | |
116 | <0 69 4>; | |
117 | }; | |
118 | ||
842839a3 PM |
119 | dcc { |
120 | compatible = "arm,vexpress,config-bus"; | |
121 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
122 | ||
123 | osc@0 { | |
124 | /* CPU and internal AXI reference clock */ | |
125 | compatible = "arm,vexpress-osc"; | |
126 | arm,vexpress-sysreg,func = <1 0>; | |
127 | freq-range = <50000000 100000000>; | |
128 | #clock-cells = <0>; | |
129 | clock-output-names = "oscclk0"; | |
130 | }; | |
131 | ||
132 | oscclk1: osc@1 { | |
133 | /* Multiplexed AXI master clock */ | |
134 | compatible = "arm,vexpress-osc"; | |
135 | arm,vexpress-sysreg,func = <1 1>; | |
136 | freq-range = <5000000 50000000>; | |
137 | #clock-cells = <0>; | |
138 | clock-output-names = "oscclk1"; | |
139 | }; | |
140 | ||
141 | osc@2 { | |
142 | /* DDR2 */ | |
143 | compatible = "arm,vexpress-osc"; | |
144 | arm,vexpress-sysreg,func = <1 2>; | |
145 | freq-range = <80000000 120000000>; | |
146 | #clock-cells = <0>; | |
147 | clock-output-names = "oscclk2"; | |
148 | }; | |
149 | ||
150 | oscclk3: osc@3 { | |
151 | /* HDLCD */ | |
152 | compatible = "arm,vexpress-osc"; | |
153 | arm,vexpress-sysreg,func = <1 3>; | |
154 | freq-range = <23750000 165000000>; | |
155 | #clock-cells = <0>; | |
156 | clock-output-names = "oscclk3"; | |
157 | }; | |
158 | ||
159 | osc@4 { | |
160 | /* Test chip gate configuration */ | |
161 | compatible = "arm,vexpress-osc"; | |
162 | arm,vexpress-sysreg,func = <1 4>; | |
163 | freq-range = <80000000 80000000>; | |
164 | #clock-cells = <0>; | |
165 | clock-output-names = "oscclk4"; | |
166 | }; | |
167 | ||
168 | smbclk: osc@5 { | |
169 | /* SMB clock */ | |
170 | compatible = "arm,vexpress-osc"; | |
171 | arm,vexpress-sysreg,func = <1 5>; | |
172 | freq-range = <25000000 60000000>; | |
173 | #clock-cells = <0>; | |
174 | clock-output-names = "oscclk5"; | |
175 | }; | |
176 | ||
177 | temp@0 { | |
178 | /* DCC internal operating temperature */ | |
179 | compatible = "arm,vexpress-temp"; | |
180 | arm,vexpress-sysreg,func = <4 0>; | |
181 | label = "DCC"; | |
182 | }; | |
183 | }; | |
184 | ||
433683a6 PM |
185 | smb { |
186 | compatible = "simple-bus"; | |
187 | ||
188 | #address-cells = <2>; | |
189 | #size-cells = <1>; | |
bfd5200c PM |
190 | ranges = <0 0 0x08000000 0x04000000>, |
191 | <1 0 0x14000000 0x04000000>, | |
192 | <2 0 0x18000000 0x04000000>, | |
193 | <3 0 0x1c000000 0x04000000>, | |
194 | <4 0 0x0c000000 0x04000000>, | |
195 | <5 0 0x10000000 0x04000000>; | |
196 | ||
433683a6 | 197 | #interrupt-cells = <1>; |
bfd5200c PM |
198 | interrupt-map-mask = <0 0 63>; |
199 | interrupt-map = <0 0 0 &gic 0 0 4>, | |
200 | <0 0 1 &gic 0 1 4>, | |
201 | <0 0 2 &gic 0 2 4>, | |
202 | <0 0 3 &gic 0 3 4>, | |
203 | <0 0 4 &gic 0 4 4>, | |
204 | <0 0 5 &gic 0 5 4>, | |
205 | <0 0 6 &gic 0 6 4>, | |
206 | <0 0 7 &gic 0 7 4>, | |
207 | <0 0 8 &gic 0 8 4>, | |
208 | <0 0 9 &gic 0 9 4>, | |
209 | <0 0 10 &gic 0 10 4>, | |
210 | <0 0 11 &gic 0 11 4>, | |
211 | <0 0 12 &gic 0 12 4>, | |
212 | <0 0 13 &gic 0 13 4>, | |
213 | <0 0 14 &gic 0 14 4>, | |
214 | <0 0 15 &gic 0 15 4>, | |
215 | <0 0 16 &gic 0 16 4>, | |
216 | <0 0 17 &gic 0 17 4>, | |
217 | <0 0 18 &gic 0 18 4>, | |
218 | <0 0 19 &gic 0 19 4>, | |
219 | <0 0 20 &gic 0 20 4>, | |
220 | <0 0 21 &gic 0 21 4>, | |
221 | <0 0 22 &gic 0 22 4>, | |
222 | <0 0 23 &gic 0 23 4>, | |
223 | <0 0 24 &gic 0 24 4>, | |
224 | <0 0 25 &gic 0 25 4>, | |
225 | <0 0 26 &gic 0 26 4>, | |
226 | <0 0 27 &gic 0 27 4>, | |
227 | <0 0 28 &gic 0 28 4>, | |
228 | <0 0 29 &gic 0 29 4>, | |
229 | <0 0 30 &gic 0 30 4>, | |
230 | <0 0 31 &gic 0 31 4>, | |
231 | <0 0 32 &gic 0 32 4>, | |
232 | <0 0 33 &gic 0 33 4>, | |
233 | <0 0 34 &gic 0 34 4>, | |
234 | <0 0 35 &gic 0 35 4>, | |
235 | <0 0 36 &gic 0 36 4>, | |
236 | <0 0 37 &gic 0 37 4>, | |
237 | <0 0 38 &gic 0 38 4>, | |
238 | <0 0 39 &gic 0 39 4>, | |
239 | <0 0 40 &gic 0 40 4>, | |
240 | <0 0 41 &gic 0 41 4>, | |
241 | <0 0 42 &gic 0 42 4>; | |
433683a6 PM |
242 | |
243 | /include/ "vexpress-v2m-rs1.dtsi" | |
bfd5200c PM |
244 | }; |
245 | }; |