[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / vf610-twr.dts

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "VF610 Tower Board";
	compatible = "fsl,vf610-twr", "fsl,vf610";

	chosen {
		bootargs = "console=ttyLP1,115200";
	};

	memory {
		reg = <0x80000000 0x8000000>;
	};

	clocks {
		audio_ext {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24576000>;
		};

		enet_ext {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3p3v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_vcc_3v3_mcu: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "vcc_3v3_mcu";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			master-clkdir-out;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
		};
	};
};

&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0_ad5>;
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&dspi0 {
	bus-num = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi0>;
	status = "okay";

	sflash: at26df081a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at26df081a";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
};

&fec0 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec0>;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	codec: sgtl5000@0a {
	       #sound-dai-cells = <0>;
	       compatible = "fsl,sgtl5000";
	       reg = <0x0a>;
	       VDDA-supply = <&reg_3p3v>;
	       VDDIO-supply = <&reg_3p3v>;
	       clocks = <&clks VF610_CLK_SAI2>;
       };
};

&iomuxc {
	vf610-twr {
		pinctrl_adc0_ad5: adc0ad5grp {
			fsl,pins = <
				VF610_PAD_PTC30__ADC0_SE5		0xa1
			>;
		};

		pinctrl_dspi0: dspi0grp {
			fsl,pins = <
				VF610_PAD_PTB19__DSPI0_CS0		0x1182
				VF610_PAD_PTB20__DSPI0_SIN		0x1181
				VF610_PAD_PTB21__DSPI0_SOUT		0x1182
				VF610_PAD_PTB22__DSPI0_SCK		0x1182
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,fsl,pins = <
				VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
				VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
				VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
				VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
				VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
				VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
				VF610_PAD_PTA7__GPIO_134	0x219d
			>;
		};

		pinctrl_fec0: fec0grp {
			fsl,pins = <
				VF610_PAD_PTA6__RMII_CLKIN		0x30d1
				VF610_PAD_PTC0__ENET_RMII0_MDC		0x30d3
				VF610_PAD_PTC1__ENET_RMII0_MDIO		0x30d1
				VF610_PAD_PTC2__ENET_RMII0_CRS		0x30d1
				VF610_PAD_PTC3__ENET_RMII0_RXD1		0x30d1
				VF610_PAD_PTC4__ENET_RMII0_RXD0		0x30d1
				VF610_PAD_PTC5__ENET_RMII0_RXER		0x30d1
				VF610_PAD_PTC6__ENET_RMII0_TXD1		0x30d2
				VF610_PAD_PTC7__ENET_RMII0_TXD0		0x30d2
				VF610_PAD_PTC8__ENET_RMII0_TXEN		0x30d2
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII_RXD1		0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				VF610_PAD_PTB14__I2C0_SCL		0x30d3
				VF610_PAD_PTB15__I2C0_SDA		0x30d3
			>;
		};

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				VF610_PAD_PTA16__SAI2_TX_BCLK		0x02ed
				VF610_PAD_PTA18__SAI2_TX_DATA		0x02ee
				VF610_PAD_PTA19__SAI2_TX_SYNC		0x02ed
				VF610_PAD_PTA21__SAI2_RX_BCLK		0x02ed
				VF610_PAD_PTA22__SAI2_RX_DATA		0x02ed
				VF610_PAD_PTA23__SAI2_RX_SYNC		0x02ed
				VF610_PAD_PTB18__EXT_AUDIO_MCLK		0x02ed
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};
	};
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};
Commit	Line	Data
e77b74ee JL	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	/dts-v1/;
	11	#include "vf610.dtsi"
	12
	13	/ {
	14	model = "VF610 Tower Board";
	15	compatible = "fsl,vf610-twr", "fsl,vf610";
	16
	17	chosen {
	18	bootargs = "console=ttyLP1,115200";
	19	};
	20
	21	memory {
	22	reg = <0x80000000 0x8000000>;
	23	};
	24
	25	clocks {
	26	audio_ext {
	27	compatible = "fixed-clock";
4b2b4043	28	#clock-cells = <0>;
e77b74ee JL	29	clock-frequency = <24576000>;
	30	};
	31
	32	enet_ext {
	33	compatible = "fixed-clock";
4b2b4043	34	#clock-cells = <0>;
e77b74ee JL	35	clock-frequency = <50000000>;
	36	};
	37	};
	38
c5d571e7 XL	39	regulators {
	40	compatible = "simple-bus";
	41	#address-cells = <1>;
	42	#size-cells = <0>;
	43
	44	reg_3p3v: regulator@0 {
	45	compatible = "regulator-fixed";
	46	reg = <0>;
	47	regulator-name = "3P3V";
	48	regulator-min-microvolt = <3300000>;
	49	regulator-max-microvolt = <3300000>;
	50	regulator-always-on;
	51	};
64436ff6 FD	52
	53	reg_vcc_3v3_mcu: regulator@1 {
	54	compatible = "regulator-fixed";
	55	reg = <1>;
	56	regulator-name = "vcc_3v3_mcu";
	57	regulator-min-microvolt = <3300000>;
	58	regulator-max-microvolt = <3300000>;
	59	};
c5d571e7	60	};
8128c4f3 XL	61
	62	sound {
	63	compatible = "simple-audio-card";
	64	simple-audio-card,format = "i2s";
	65	simple-audio-card,widgets =
	66	"Microphone", "Microphone Jack",
	67	"Headphone", "Headphone Jack",
	68	"Speaker", "Speaker Ext",
	69	"Line", "Line In Jack";
	70	simple-audio-card,routing =
	71	"MIC_IN", "Microphone Jack",
	72	"Microphone Jack", "Mic Bias",
	73	"LINE_IN", "Line In Jack",
	74	"Headphone Jack", "HP_OUT",
	75	"Speaker Ext", "LINE_OUT";
	76
	77	simple-audio-card,cpu {
	78	sound-dai = <&sai2>;
	79	master-clkdir-out;
	80	frame-master;
	81	bitclock-master;
	82	};
	83
	84	simple-audio-card,codec {
	85	sound-dai = <&codec>;
	86	frame-master;
	87	bitclock-master;
	88	};
	89	};
e77b74ee JL	90	};
e77b74ee JL	91
64436ff6 FD	92	&adc0 {
	93	pinctrl-names = "default";
	94	pinctrl-0 = <&pinctrl_adc0_ad5>;
	95	vref-supply = <&reg_vcc_3v3_mcu>;
	96	status = "okay";
	97	};
	98
dc03a50f CF	99	&dspi0 {
	100	bus-num = <0>;
	101	pinctrl-names = "default";
07ed1eed	102	pinctrl-0 = <&pinctrl_dspi0>;
dc03a50f CF	103	status = "okay";
	104
	105	sflash: at26df081a@0 {
	106	#address-cells = <1>;
	107	#size-cells = <1>;
	108	compatible = "atmel,at26df081a";
	109	spi-max-frequency = <16000000>;
	110	spi-cpol;
	111	spi-cpha;
	112	reg = <0>;
	113	};
	114	};
	115
0517fe6a CS	116	&esdhc1 {
	117	pinctrl-names = "default";
	118	pinctrl-0 = <&pinctrl_esdhc1>;
	119	bus-width = <4>;
	120	status = "okay";
	121	};
	122
e77b74ee JL	123	&fec0 {
	124	phy-mode = "rmii";
	125	pinctrl-names = "default";
07ed1eed	126	pinctrl-0 = <&pinctrl_fec0>;
e77b74ee JL	127	status = "okay";
	128	};
	129
	130	&fec1 {
	131	phy-mode = "rmii";
	132	pinctrl-names = "default";
07ed1eed	133	pinctrl-0 = <&pinctrl_fec1>;
e77b74ee JL	134	status = "okay";
	135	};
	136
d45393cd JL	137	&i2c0 {
	138	clock-frequency = <100000>;
	139	pinctrl-names = "default";
07ed1eed	140	pinctrl-0 = <&pinctrl_i2c0>;
d45393cd	141	status = "okay";
c5d571e7 XL	142
c5d571e7 XL	143	codec: sgtl5000@0a {
8128c4f3	144	#sound-dai-cells = <0>;
c5d571e7 XL	145	compatible = "fsl,sgtl5000";
	146	reg = <0x0a>;
	147	VDDA-supply = <&reg_3p3v>;
	148	VDDIO-supply = <&reg_3p3v>;
	149	clocks = <&clks VF610_CLK_SAI2>;
	150	};
d45393cd JL	151	};
d45393cd JL	152
07ed1eed SG	153	&iomuxc {
07ed1eed SG	154	vf610-twr {
64436ff6 FD	155	pinctrl_adc0_ad5: adc0ad5grp {
	156	fsl,pins = <
	157	VF610_PAD_PTC30__ADC0_SE5 0xa1
	158	>;
	159	};
	160
07ed1eed SG	161	pinctrl_dspi0: dspi0grp {
	162	fsl,pins = <
	163	VF610_PAD_PTB19__DSPI0_CS0 0x1182
	164	VF610_PAD_PTB20__DSPI0_SIN 0x1181
	165	VF610_PAD_PTB21__DSPI0_SOUT 0x1182
	166	VF610_PAD_PTB22__DSPI0_SCK 0x1182
	167	>;
	168	};
	169
0517fe6a CS	170	pinctrl_esdhc1: esdhc1grp {
	171	fsl,fsl,pins = <
	172	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	173	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	174	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	175	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	176	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	177	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	178	VF610_PAD_PTA7__GPIO_134 0x219d
	179	>;
	180	};
	181
07ed1eed SG	182	pinctrl_fec0: fec0grp {
	183	fsl,pins = <
	184	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	185	VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
	186	VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
	187	VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
	188	VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
	189	VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
	190	VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
	191	VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
	192	VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
	193	VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
	194	>;
	195	};
	196
	197	pinctrl_fec1: fec1grp {
	198	fsl,pins = <
	199	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	200	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	201	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	202	VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
	203	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	204	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	205	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	206	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	207	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	208	>;
	209	};
	210
	211	pinctrl_i2c0: i2c0grp {
	212	fsl,pins = <
	213	VF610_PAD_PTB14__I2C0_SCL 0x30d3
	214	VF610_PAD_PTB15__I2C0_SDA 0x30d3
	215	>;
	216	};
	217
95b13b66 XL	218	pinctrl_sai2: sai2grp {
	219	fsl,pins = <
	220	VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
	221	VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
	222	VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
	223	VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
	224	VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
	225	VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
	226	VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
	227	>;
	228	};
	229
07ed1eed SG	230	pinctrl_uart1: uart1grp {
	231	fsl,pins = <
	232	VF610_PAD_PTB4__UART1_TX 0x21a2
	233	VF610_PAD_PTB5__UART1_RX 0x21a1
	234	>;
	235	};
	236	};
	237	};
	238
95b13b66	239	&sai2 {
8128c4f3	240	#sound-dai-cells = <0>;
95b13b66 XL	241	pinctrl-names = "default";
	242	pinctrl-0 = <&pinctrl_sai2>;
	243	status = "okay";
	244	};
	245
e77b74ee JL	246	&uart1 {
e77b74ee JL	247	pinctrl-names = "default";
07ed1eed	248	pinctrl-0 = <&pinctrl_uart1>;
e77b74ee JL	249	status = "okay";
e77b74ee JL	250	};