[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / vf610-zii-dev-rev-b.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
 */

/dts-v1/;
#include "vf610-zii-dev.dtsi"

/ {
	model = "ZII VF610 Development Board, Rev B";
	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";

	mdio-mux {
		compatible = "mdio-mux-gpio";
		pinctrl-0 = <&pinctrl_mdio_mux>;
		pinctrl-names = "default";
		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
			 &gpio0 9  GPIO_ACTIVE_HIGH
			 &gpio0 24 GPIO_ACTIVE_HIGH
			 &gpio0 25 GPIO_ACTIVE_HIGH>;
		mdio-parent-bus = <&mdio1>;
		#address-cells = <1>;
		#size-cells = <0>;

		mdio_mux_1: mdio@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch0: switch@0 {
				compatible = "marvell,mv88e6085";
				pinctrl-0 = <&pinctrl_gpio_switch0>;
				pinctrl-names = "default";
				reg = <0>;
				dsa,member = <0 0>;
				interrupt-parent = <&gpio0>;
				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
				interrupt-controller;
				#interrupt-cells = <2>;
				eeprom-length = <512>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						label = "lan0";
						phy-handle = <&switch0phy0>;
					};

					port@1 {
						reg = <1>;
						label = "lan1";
						phy-handle = <&switch0phy1>;
					};

					port@2 {
						reg = <2>;
						label = "lan2";
						phy-handle = <&switch0phy2>;
					};

					switch0port5: port@5 {
						reg = <5>;
						label = "dsa";
						phy-mode = "rgmii-txid";
						link = <&switch1port6
							&switch2port9>;
						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};

					port@6 {
						reg = <6>;
						label = "cpu";
						ethernet = <&fec1>;

						fixed-link {
							speed = <100>;
							full-duplex;
						};
					};
				};
				mdio {
					#address-cells = <1>;
					#size-cells = <0>;
					switch0phy0: switch0phy0@0 {
						reg = <0>;
						interrupt-parent = <&switch0>;
						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
					};
					switch0phy1: switch1phy0@1 {
						reg = <1>;
						interrupt-parent = <&switch0>;
						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
					};
					switch0phy2: switch1phy0@2 {
						reg = <2>;
						interrupt-parent = <&switch0>;
						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
					};
				};
			};
		};

		mdio_mux_2: mdio@2 {
			reg = <2>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch1: switch@0 {
				compatible = "marvell,mv88e6085";
				pinctrl-0 = <&pinctrl_gpio_switch1>;
				pinctrl-names = "default";
				reg = <0>;
				dsa,member = <0 1>;
				interrupt-parent = <&gpio0>;
				interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
				interrupt-controller;
				#interrupt-cells = <2>;
				eeprom-length = <512>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						label = "lan3";
						phy-handle = <&switch1phy0>;
					};

					port@1 {
						reg = <1>;
						label = "lan4";
						phy-handle = <&switch1phy1>;
					};

					port@2 {
						reg = <2>;
						label = "lan5";
						phy-handle = <&switch1phy2>;
					};

					switch1port5: port@5 {
						reg = <5>;
						label = "dsa";
						link = <&switch2port9>;
						phy-mode = "rgmii-txid";

						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};

					switch1port6: port@6 {
						reg = <6>;
						label = "dsa";
						phy-mode = "rgmii-txid";
						link = <&switch0port5>;
						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};
				};
				mdio {
					#address-cells = <1>;
					#size-cells = <0>;

					switch1phy0: switch1phy0@0 {
						reg = <0>;
						interrupt-parent = <&switch1>;
						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
					};

					switch1phy1: switch1phy0@1 {
						reg = <1>;
						interrupt-parent = <&switch1>;
						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
					};

					switch1phy2: switch1phy0@2 {
						reg = <2>;
						interrupt-parent = <&switch1>;
						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
					};
				};
			};
		};

		mdio_mux_4: mdio@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			switch2: switch@0 {
				compatible = "marvell,mv88e6085";
				reg = <0>;
				dsa,member = <0 2>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						label = "lan6";
						phy-handle = <&switch2phy0>;
					};

					port@1 {
						reg = <1>;
						label = "lan7";
						phy-handle = <&switch2phy1>;
					};

					port@2 {
						reg = <2>;
						label = "lan8";
						phy-handle = <&switch2phy2>;
					};

					port@3 {
						reg = <3>;
						label = "optical3";

						fixed-link {
							speed = <1000>;
							full-duplex;
							link-gpios = <&gpio6 2
							      GPIO_ACTIVE_HIGH>;
						};
					};

					port@4 {
						reg = <4>;
						label = "optical4";

						fixed-link {
							speed = <1000>;
							full-duplex;
							link-gpios = <&gpio6 3
							      GPIO_ACTIVE_HIGH>;
						};
					};

					switch2port9: port@9 {
						reg = <9>;
						label = "dsa";
						phy-mode = "rgmii-txid";
						link = <&switch1port5
							&switch0port5>;

						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};
				};
				mdio {
					#address-cells = <1>;
					#size-cells = <0>;

					switch2phy0: phy@0 {
						reg = <0>;
					};
					switch2phy1: phy@1 {
						reg = <1>;
					};
					switch2phy2: phy@2 {
						reg = <2>;
					};
				};
			};
		};

		mdio_mux_8: mdio@8 {
			reg = <8>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	spi0 {
		compatible = "spi-gpio";
		pinctrl-0 = <&pinctrl_gpio_spi0>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_LOW
			     &gpio1  8 GPIO_ACTIVE_HIGH>;
		num-chipselects = <2>;

		flash@0 {
			compatible = "m25p128", "jedec,spi-nor";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0>;
			spi-max-frequency = <1000000>;
		};

		at93c46d@1 {
			compatible = "atmel,at93c46d";
			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
			pinctrl-names = "default";
			#address-cells = <0>;
			#size-cells = <0>;
			reg = <1>;
			spi-max-frequency = <500000>;
			spi-cs-high;
			data-size = <16>;
			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio5: io-expander@20 {
		compatible = "nxp,pca9554";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;

	};

	gpio6: io-expander@22 {
		compatible = "nxp,pca9554";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pca9554_22>;
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&gpio3>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	tca9548@70 {
		compatible = "nxp,pca9548";
		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			sfp1: eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			sfp2: eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			sfp3: eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			sfp4: eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};
	};
};


&iomuxc {
	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
		fsl,pins = <
			VF610_PAD_PTE27__GPIO_132	0x33e2
		>;
	};

	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
		fsl,pins = <
			VF610_PAD_PTB22__GPIO_44	0x33e2
			VF610_PAD_PTB21__GPIO_43	0x33e2
			VF610_PAD_PTB20__GPIO_42	0x33e1
			VF610_PAD_PTB19__GPIO_41	0x33e2
			VF610_PAD_PTB18__GPIO_40	0x33e2
		>;
	};

	pinctrl_mdio_mux: pinctrl-mdio-mux {
		fsl,pins = <
			VF610_PAD_PTA18__GPIO_8		0x31c2
			VF610_PAD_PTA19__GPIO_9		0x31c2
			VF610_PAD_PTB2__GPIO_24		0x31c2
			VF610_PAD_PTB3__GPIO_25		0x31c2
		>;
	};

	pinctrl_pca9554_22: pinctrl-pca95540-22 {
		fsl,pins = <
			VF610_PAD_PTB28__GPIO_98	0x219d
		>;
	};
};
Commit	Line	Data
7ee137a9	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
1556063f CT	2	/*
1556063f CT	3	* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
1556063f CT	4	*/
	5
	6	/dts-v1/;
d4cd1581	7	#include "vf610-zii-dev.dtsi"
1556063f CT	8
	9	/ {
	10	model = "ZII VF610 Development Board, Rev B";
	11	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
	12
1556063f CT	13	mdio-mux {
	14	compatible = "mdio-mux-gpio";
	15	pinctrl-0 = <&pinctrl_mdio_mux>;
	16	pinctrl-names = "default";
	17	gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
	18	&gpio0 9 GPIO_ACTIVE_HIGH
	19	&gpio0 24 GPIO_ACTIVE_HIGH
	20	&gpio0 25 GPIO_ACTIVE_HIGH>;
	21	mdio-parent-bus = <&mdio1>;
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	mdio_mux_1: mdio@1 {
	26	reg = <1>;
	27	#address-cells = <1>;
	28	#size-cells = <0>;
9dff6733	29
d4cd1581	30	switch0: switch@0 {
9dff6733	31	compatible = "marvell,mv88e6085";
f283745b AL	32	pinctrl-0 = <&pinctrl_gpio_switch0>;
f283745b AL	33	pinctrl-names = "default";
9dff6733 AL	34	reg = <0>;
9dff6733 AL	35	dsa,member = <0 0>;
f283745b AL	36	interrupt-parent = <&gpio0>;
	37	interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	38	interrupt-controller;
	39	#interrupt-cells = <2>;
925b865f	40	eeprom-length = <512>;
9dff6733 AL	41
	42	ports {
	43	#address-cells = <1>;
	44	#size-cells = <0>;
d4cd1581	45
9dff6733 AL	46	port@0 {
	47	reg = <0>;
	48	label = "lan0";
f283745b	49	phy-handle = <&switch0phy0>;
9dff6733 AL	50	};
	51
	52	port@1 {
	53	reg = <1>;
	54	label = "lan1";
f283745b	55	phy-handle = <&switch0phy1>;
9dff6733 AL	56	};
	57
	58	port@2 {
	59	reg = <2>;
	60	label = "lan2";
f283745b	61	phy-handle = <&switch0phy2>;
9dff6733 AL	62	};
	63
	64	switch0port5: port@5 {
	65	reg = <5>;
	66	label = "dsa";
	67	phy-mode = "rgmii-txid";
	68	link = <&switch1port6
	69	&switch2port9>;
	70	fixed-link {
	71	speed = <1000>;
	72	full-duplex;
	73	};
	74	};
	75
	76	port@6 {
	77	reg = <6>;
	78	label = "cpu";
	79	ethernet = <&fec1>;
d4cd1581	80
9dff6733 AL	81	fixed-link {
	82	speed = <100>;
	83	full-duplex;
	84	};
	85	};
	86	};
f283745b AL	87	mdio {
	88	#address-cells = <1>;
	89	#size-cells = <0>;
	90	switch0phy0: switch0phy0@0 {
	91	reg = <0>;
	92	interrupt-parent = <&switch0>;
	93	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
	94	};
	95	switch0phy1: switch1phy0@1 {
	96	reg = <1>;
	97	interrupt-parent = <&switch0>;
4c51de45 AF	98	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
4c51de45 AF	99	};
f283745b AL	100	switch0phy2: switch1phy0@2 {
	101	reg = <2>;
	102	interrupt-parent = <&switch0>;
	103	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
	104	};
	105	};
9dff6733	106	};
1556063f CT	107	};
	108
	109	mdio_mux_2: mdio@2 {
	110	reg = <2>;
	111	#address-cells = <1>;
	112	#size-cells = <0>;
1556063f	113
d4cd1581	114	switch1: switch@0 {
9dff6733	115	compatible = "marvell,mv88e6085";
f283745b AL	116	pinctrl-0 = <&pinctrl_gpio_switch1>;
f283745b AL	117	pinctrl-names = "default";
1556063f	118	reg = <0>;
9dff6733	119	dsa,member = <0 1>;
f283745b AL	120	interrupt-parent = <&gpio0>;
	121	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	122	interrupt-controller;
	123	#interrupt-cells = <2>;
925b865f	124	eeprom-length = <512>;
9dff6733 AL	125
	126	ports {
	127	#address-cells = <1>;
	128	#size-cells = <0>;
d4cd1581	129
9dff6733 AL	130	port@0 {
	131	reg = <0>;
	132	label = "lan3";
	133	phy-handle = <&switch1phy0>;
	134	};
	135
	136	port@1 {
	137	reg = <1>;
	138	label = "lan4";
	139	phy-handle = <&switch1phy1>;
	140	};
	141
	142	port@2 {
	143	reg = <2>;
	144	label = "lan5";
	145	phy-handle = <&switch1phy2>;
	146	};
	147
	148	switch1port5: port@5 {
	149	reg = <5>;
	150	label = "dsa";
	151	link = <&switch2port9>;
	152	phy-mode = "rgmii-txid";
d4cd1581	153
9dff6733 AL	154	fixed-link {
	155	speed = <1000>;
	156	full-duplex;
	157	};
	158	};
	159
	160	switch1port6: port@6 {
	161	reg = <6>;
	162	label = "dsa";
	163	phy-mode = "rgmii-txid";
	164	link = <&switch0port5>;
	165	fixed-link {
	166	speed = <1000>;
	167	full-duplex;
	168	};
	169	};
1556063f	170	};
9dff6733 AL	171	mdio {
	172	#address-cells = <1>;
	173	#size-cells = <0>;
d4cd1581	174
9dff6733 AL	175	switch1phy0: switch1phy0@0 {
9dff6733 AL	176	reg = <0>;
f283745b AL	177	interrupt-parent = <&switch1>;
f283745b AL	178	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
9dff6733	179	};
d4cd1581	180
9dff6733 AL	181	switch1phy1: switch1phy0@1 {
9dff6733 AL	182	reg = <1>;
f283745b AL	183	interrupt-parent = <&switch1>;
f283745b AL	184	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
9dff6733	185	};
d4cd1581	186
9dff6733 AL	187	switch1phy2: switch1phy0@2 {
9dff6733 AL	188	reg = <2>;
f283745b AL	189	interrupt-parent = <&switch1>;
f283745b AL	190	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
9dff6733	191	};
1556063f CT	192	};
1556063f CT	193	};
1556063f CT	194	};
1556063f CT	195
9dff6733	196	mdio_mux_4: mdio@4 {
1556063f CT	197	#address-cells = <1>;
1556063f CT	198	#size-cells = <0>;
9dff6733	199	reg = <4>;
1556063f	200
1cb1a68d	201	switch2: switch@0 {
9dff6733	202	compatible = "marvell,mv88e6085";
1556063f	203	reg = <0>;
9dff6733 AL	204	dsa,member = <0 2>;
	205
	206	ports {
	207	#address-cells = <1>;
	208	#size-cells = <0>;
d4cd1581	209
9dff6733 AL	210	port@0 {
	211	reg = <0>;
	212	label = "lan6";
7bb83f6d	213	phy-handle = <&switch2phy0>;
9dff6733 AL	214	};
	215
	216	port@1 {
	217	reg = <1>;
	218	label = "lan7";
7bb83f6d	219	phy-handle = <&switch2phy1>;
9dff6733 AL	220	};
	221
	222	port@2 {
	223	reg = <2>;
	224	label = "lan8";
7bb83f6d	225	phy-handle = <&switch2phy2>;
9dff6733 AL	226	};
	227
	228	port@3 {
	229	reg = <3>;
	230	label = "optical3";
d4cd1581	231
9dff6733 AL	232	fixed-link {
	233	speed = <1000>;
	234	full-duplex;
	235	link-gpios = <&gpio6 2
	236	GPIO_ACTIVE_HIGH>;
	237	};
	238	};
	239
	240	port@4 {
	241	reg = <4>;
	242	label = "optical4";
d4cd1581	243
9dff6733 AL	244	fixed-link {
	245	speed = <1000>;
	246	full-duplex;
	247	link-gpios = <&gpio6 3
	248	GPIO_ACTIVE_HIGH>;
	249	};
	250	};
	251
	252	switch2port9: port@9 {
	253	reg = <9>;
	254	label = "dsa";
	255	phy-mode = "rgmii-txid";
	256	link = <&switch1port5
	257	&switch0port5>;
d4cd1581	258
9dff6733 AL	259	fixed-link {
	260	speed = <1000>;
	261	full-duplex;
	262	};
	263	};
1556063f	264	};
7bb83f6d RK	265	mdio {
	266	#address-cells = <1>;
	267	#size-cells = <0>;
	268
	269	switch2phy0: phy@0 {
	270	reg = <0>;
	271	};
	272	switch2phy1: phy@1 {
	273	reg = <1>;
	274	};
	275	switch2phy2: phy@2 {
	276	reg = <2>;
	277	};
	278	};
1556063f CT	279	};
	280	};
	281
9dff6733 AL	282	mdio_mux_8: mdio@8 {
9dff6733 AL	283	reg = <8>;
1556063f CT	284	#address-cells = <1>;
1556063f CT	285	#size-cells = <0>;
1556063f CT	286	};
	287	};
	288
1556063f CT	289	spi0 {
	290	compatible = "spi-gpio";
	291	pinctrl-0 = <&pinctrl_gpio_spi0>;
	292	pinctrl-names = "default";
	293	#address-cells = <1>;
	294	#size-cells = <0>;
	295	gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	296	gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
	297	gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
2ea5c9b2	298	cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW
1556063f CT	299	&gpio1 8 GPIO_ACTIVE_HIGH>;
	300	num-chipselects = <2>;
	301
00e3ff8b	302	flash@0 {
1556063f CT	303	compatible = "m25p128", "jedec,spi-nor";
	304	#address-cells = <1>;
	305	#size-cells = <1>;
	306	reg = <0>;
	307	spi-max-frequency = <1000000>;
	308	};
	309
	310	at93c46d@1 {
	311	compatible = "atmel,at93c46d";
	312	pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
	313	pinctrl-names = "default";
	314	#address-cells = <0>;
	315	#size-cells = <0>;
	316	reg = <1>;
	317	spi-max-frequency = <500000>;
	318	spi-cs-high;
	319	data-size = <16>;
	320	select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
	321	};
	322	};
	323	};
	324
1556063f CT	325	&i2c0 {
	326	clock-frequency = <100000>;
	327	pinctrl-names = "default";
	328	pinctrl-0 = <&pinctrl_i2c0>;
	329	status = "okay";
	330
00e3ff8b	331	gpio5: io-expander@20 {
1556063f CT	332	compatible = "nxp,pca9554";
	333	reg = <0x20>;
	334	gpio-controller;
	335	#gpio-cells = <2>;
	336
	337	};
	338
00e3ff8b	339	gpio6: io-expander@22 {
1556063f CT	340	compatible = "nxp,pca9554";
	341	pinctrl-names = "default";
	342	pinctrl-0 = <&pinctrl_pca9554_22>;
	343	reg = <0x22>;
	344	gpio-controller;
	345	#gpio-cells = <2>;
c09d063b RK	346	interrupt-controller;
c09d063b RK	347	interrupt-parent = <&gpio3>;
1556063f CT	348	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
1556063f CT	349	};
1556063f CT	350	};
	351
	352	&i2c2 {
	353	clock-frequency = <100000>;
	354	pinctrl-names = "default";
	355	pinctrl-0 = <&pinctrl_i2c2>;
	356	status = "okay";
	357
	358	tca9548@70 {
	359	compatible = "nxp,pca9548";
	360	pinctrl-0 = <&pinctrl_i2c_mux_reset>;
	361	pinctrl-names = "default";
	362	#address-cells = <1>;
	363	#size-cells = <0>;
	364	reg = <0x70>;
	365	reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
	366
	367	i2c@0 {
	368	#address-cells = <1>;
	369	#size-cells = <0>;
	370	reg = <0>;
	371
00e3ff8b	372	sfp1: eeprom@50 {
1556063f CT	373	compatible = "atmel,24c02";
	374	reg = <0x50>;
	375	};
	376	};
	377
	378	i2c@1 {
	379	#address-cells = <1>;
	380	#size-cells = <0>;
	381	reg = <1>;
	382
00e3ff8b	383	sfp2: eeprom@50 {
1556063f CT	384	compatible = "atmel,24c02";
	385	reg = <0x50>;
	386	};
	387	};
	388
	389	i2c@2 {
	390	#address-cells = <1>;
	391	#size-cells = <0>;
	392	reg = <2>;
	393
00e3ff8b	394	sfp3: eeprom@50 {
1556063f CT	395	compatible = "atmel,24c02";
	396	reg = <0x50>;
	397	};
	398	};
	399
	400	i2c@3 {
	401	#address-cells = <1>;
	402	#size-cells = <0>;
	403	reg = <3>;
	404
00e3ff8b	405	sfp4: eeprom@50 {
1556063f CT	406	compatible = "atmel,24c02";
	407	reg = <0x50>;
	408	};
	409	};
	410
	411	i2c@4 {
	412	#address-cells = <1>;
	413	#size-cells = <0>;
	414	reg = <4>;
	415	};
	416	};
	417	};
	418
1556063f CT	419
1556063f CT	420	&iomuxc {
1556063f CT	421	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
	422	fsl,pins = <
	423	VF610_PAD_PTE27__GPIO_132 0x33e2
	424	>;
	425	};
	426
	427	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
	428	fsl,pins = <
	429	VF610_PAD_PTB22__GPIO_44 0x33e2
	430	VF610_PAD_PTB21__GPIO_43 0x33e2
	431	VF610_PAD_PTB20__GPIO_42 0x33e1
	432	VF610_PAD_PTB19__GPIO_41 0x33e2
	433	VF610_PAD_PTB18__GPIO_40 0x33e2
	434	>;
	435	};
	436
1556063f CT	437	pinctrl_mdio_mux: pinctrl-mdio-mux {
	438	fsl,pins = <
	439	VF610_PAD_PTA18__GPIO_8 0x31c2
	440	VF610_PAD_PTA19__GPIO_9 0x31c2
	441	VF610_PAD_PTB2__GPIO_24 0x31c2
	442	VF610_PAD_PTB3__GPIO_25 0x31c2
	443	>;
	444	};
	445
	446	pinctrl_pca9554_22: pinctrl-pca95540-22 {
	447	fsl,pins = <
	448	VF610_PAD_PTB28__GPIO_98 0x219d
	449	>;
	450	};
1556063f	451	};