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d02e1349 JL |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include "skeleton.dtsi" | |
11 | #include "vf610-pinfunc.h" | |
12 | #include <dt-bindings/clock/vf610-clock.h> | |
2bc88b1b | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
d02e1349 JL |
14 | |
15 | / { | |
16 | aliases { | |
17 | serial0 = &uart0; | |
18 | serial1 = &uart1; | |
19 | serial2 = &uart2; | |
20 | serial3 = &uart3; | |
21 | serial4 = &uart4; | |
22 | serial5 = &uart5; | |
23 | gpio0 = &gpio1; | |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | }; | |
29 | ||
30 | cpus { | |
31 | #address-cells = <1>; | |
32 | #size-cells = <0>; | |
33 | ||
34 | cpu@0 { | |
35 | compatible = "arm,cortex-a5"; | |
36 | device_type = "cpu"; | |
37 | reg = <0x0>; | |
38 | next-level-cache = <&L2>; | |
39 | }; | |
40 | }; | |
41 | ||
42 | clocks { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | sxosc { | |
47 | compatible = "fixed-clock"; | |
4b2b4043 | 48 | #clock-cells = <0>; |
d02e1349 JL |
49 | clock-frequency = <32768>; |
50 | }; | |
51 | ||
52 | fxosc { | |
53 | compatible = "fixed-clock"; | |
4b2b4043 | 54 | #clock-cells = <0>; |
d02e1349 JL |
55 | clock-frequency = <24000000>; |
56 | }; | |
57 | }; | |
58 | ||
59 | soc { | |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | compatible = "simple-bus"; | |
63 | interrupt-parent = <&intc>; | |
64 | ranges; | |
65 | ||
66 | aips0: aips-bus@40000000 { | |
67 | compatible = "fsl,aips-bus", "simple-bus"; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | interrupt-parent = <&intc>; | |
71 | reg = <0x40000000 0x70000>; | |
72 | ranges; | |
73 | ||
74 | intc: interrupt-controller@40002000 { | |
75 | compatible = "arm,cortex-a9-gic"; | |
76 | #interrupt-cells = <3>; | |
d02e1349 JL |
77 | interrupt-controller; |
78 | reg = <0x40003000 0x1000>, | |
79 | <0x40002100 0x100>; | |
80 | }; | |
81 | ||
82 | L2: l2-cache@40006000 { | |
83 | compatible = "arm,pl310-cache"; | |
84 | reg = <0x40006000 0x1000>; | |
85 | cache-unified; | |
86 | cache-level = <2>; | |
87 | arm,data-latency = <1 1 1>; | |
88 | arm,tag-latency = <2 2 2>; | |
89 | }; | |
90 | ||
b93293b9 JL |
91 | edma0: dma-controller@40018000 { |
92 | #dma-cells = <2>; | |
93 | compatible = "fsl,vf610-edma"; | |
94 | reg = <0x40018000 0x2000>, | |
95 | <0x40024000 0x1000>, | |
96 | <0x40025000 0x1000>; | |
97 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, | |
98 | <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
99 | interrupt-names = "edma-tx", "edma-err"; | |
100 | dma-channels = <32>; | |
101 | clock-names = "dmamux0", "dmamux1"; | |
102 | clocks = <&clks VF610_CLK_DMAMUX0>, | |
103 | <&clks VF610_CLK_DMAMUX1>; | |
104 | }; | |
105 | ||
d02e1349 JL |
106 | uart0: serial@40027000 { |
107 | compatible = "fsl,vf610-lpuart"; | |
108 | reg = <0x40027000 0x1000>; | |
2bc88b1b | 109 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
110 | clocks = <&clks VF610_CLK_UART0>; |
111 | clock-names = "ipg"; | |
8fbc8c07 YY |
112 | dmas = <&edma0 0 2>, |
113 | <&edma0 0 3>; | |
114 | dma-names = "rx","tx"; | |
d02e1349 JL |
115 | status = "disabled"; |
116 | }; | |
117 | ||
118 | uart1: serial@40028000 { | |
119 | compatible = "fsl,vf610-lpuart"; | |
120 | reg = <0x40028000 0x1000>; | |
2bc88b1b | 121 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
122 | clocks = <&clks VF610_CLK_UART1>; |
123 | clock-names = "ipg"; | |
8fbc8c07 YY |
124 | dmas = <&edma0 0 4>, |
125 | <&edma0 0 5>; | |
126 | dma-names = "rx","tx"; | |
d02e1349 JL |
127 | status = "disabled"; |
128 | }; | |
129 | ||
130 | uart2: serial@40029000 { | |
131 | compatible = "fsl,vf610-lpuart"; | |
132 | reg = <0x40029000 0x1000>; | |
2bc88b1b | 133 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
134 | clocks = <&clks VF610_CLK_UART2>; |
135 | clock-names = "ipg"; | |
8fbc8c07 YY |
136 | dmas = <&edma0 0 6>, |
137 | <&edma0 0 7>; | |
138 | dma-names = "rx","tx"; | |
d02e1349 JL |
139 | status = "disabled"; |
140 | }; | |
141 | ||
142 | uart3: serial@4002a000 { | |
143 | compatible = "fsl,vf610-lpuart"; | |
144 | reg = <0x4002a000 0x1000>; | |
2bc88b1b | 145 | interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
146 | clocks = <&clks VF610_CLK_UART3>; |
147 | clock-names = "ipg"; | |
8fbc8c07 YY |
148 | dmas = <&edma0 0 8>, |
149 | <&edma0 0 9>; | |
150 | dma-names = "rx","tx"; | |
d02e1349 JL |
151 | status = "disabled"; |
152 | }; | |
153 | ||
d7a9d8e2 CF |
154 | dspi0: dspi0@4002c000 { |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
157 | compatible = "fsl,vf610-dspi"; | |
158 | reg = <0x4002c000 0x1000>; | |
2bc88b1b | 159 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
d7a9d8e2 CF |
160 | clocks = <&clks VF610_CLK_DSPI0>; |
161 | clock-names = "dspi"; | |
162 | spi-num-chipselects = <5>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
d02e1349 JL |
166 | sai2: sai@40031000 { |
167 | compatible = "fsl,vf610-sai"; | |
168 | reg = <0x40031000 0x1000>; | |
2bc88b1b | 169 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
170 | clocks = <&clks VF610_CLK_SAI2>; |
171 | clock-names = "sai"; | |
1d412417 XL |
172 | dma-names = "tx", "rx"; |
173 | dmas = <&edma0 0 21>, | |
174 | <&edma0 0 20>; | |
d02e1349 JL |
175 | status = "disabled"; |
176 | }; | |
177 | ||
178 | pit: pit@40037000 { | |
179 | compatible = "fsl,vf610-pit"; | |
180 | reg = <0x40037000 0x1000>; | |
2bc88b1b | 181 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
182 | clocks = <&clks VF610_CLK_PIT>; |
183 | clock-names = "pit"; | |
184 | }; | |
185 | ||
7c978e0f XL |
186 | pwm0: pwm@40038000 { |
187 | compatible = "fsl,vf610-ftm-pwm"; | |
188 | #pwm-cells = <3>; | |
189 | reg = <0x40038000 0x1000>; | |
190 | clock-names = "ftm_sys", "ftm_ext", | |
191 | "ftm_fix", "ftm_cnt_clk_en"; | |
192 | clocks = <&clks VF610_CLK_FTM0>, | |
193 | <&clks VF610_CLK_FTM0_EXT_SEL>, | |
194 | <&clks VF610_CLK_FTM0_FIX_SEL>, | |
195 | <&clks VF610_CLK_FTM0_EXT_FIX_EN>; | |
196 | status = "disabled"; | |
197 | }; | |
198 | ||
64436ff6 FD |
199 | adc0: adc@4003b000 { |
200 | compatible = "fsl,vf610-adc"; | |
201 | reg = <0x4003b000 0x1000>; | |
202 | interrupts = <0 53 0x04>; | |
203 | clocks = <&clks VF610_CLK_ADC0>; | |
204 | clock-names = "adc"; | |
205 | status = "disabled"; | |
206 | }; | |
207 | ||
d02e1349 JL |
208 | wdog@4003e000 { |
209 | compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; | |
210 | reg = <0x4003e000 0x1000>; | |
211 | clocks = <&clks VF610_CLK_WDT>; | |
212 | clock-names = "wdog"; | |
213 | }; | |
214 | ||
215 | qspi0: quadspi@40044000 { | |
216 | #address-cells = <1>; | |
217 | #size-cells = <0>; | |
218 | compatible = "fsl,vf610-qspi"; | |
219 | reg = <0x40044000 0x1000>; | |
2bc88b1b | 220 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
221 | clocks = <&clks VF610_CLK_QSPI0_EN>, |
222 | <&clks VF610_CLK_QSPI0>; | |
223 | clock-names = "qspi_en", "qspi"; | |
224 | status = "disabled"; | |
225 | }; | |
226 | ||
227 | iomuxc: iomuxc@40048000 { | |
228 | compatible = "fsl,vf610-iomuxc"; | |
229 | reg = <0x40048000 0x1000>; | |
36af8f3e | 230 | #gpio-range-cells = <3>; |
d02e1349 JL |
231 | }; |
232 | ||
233 | gpio1: gpio@40049000 { | |
234 | compatible = "fsl,vf610-gpio"; | |
235 | reg = <0x40049000 0x1000 0x400ff000 0x40>; | |
2bc88b1b | 236 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
237 | gpio-controller; |
238 | #gpio-cells = <2>; | |
239 | interrupt-controller; | |
240 | #interrupt-cells = <2>; | |
36af8f3e | 241 | gpio-ranges = <&iomuxc 0 0 32>; |
d02e1349 JL |
242 | }; |
243 | ||
244 | gpio2: gpio@4004a000 { | |
245 | compatible = "fsl,vf610-gpio"; | |
246 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; | |
2bc88b1b | 247 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
248 | gpio-controller; |
249 | #gpio-cells = <2>; | |
250 | interrupt-controller; | |
251 | #interrupt-cells = <2>; | |
36af8f3e | 252 | gpio-ranges = <&iomuxc 0 32 32>; |
d02e1349 JL |
253 | }; |
254 | ||
255 | gpio3: gpio@4004b000 { | |
256 | compatible = "fsl,vf610-gpio"; | |
257 | reg = <0x4004b000 0x1000 0x400ff080 0x40>; | |
2bc88b1b | 258 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
259 | gpio-controller; |
260 | #gpio-cells = <2>; | |
261 | interrupt-controller; | |
262 | #interrupt-cells = <2>; | |
36af8f3e | 263 | gpio-ranges = <&iomuxc 0 64 32>; |
d02e1349 JL |
264 | }; |
265 | ||
266 | gpio4: gpio@4004c000 { | |
267 | compatible = "fsl,vf610-gpio"; | |
268 | reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; | |
2bc88b1b | 269 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
270 | gpio-controller; |
271 | #gpio-cells = <2>; | |
272 | interrupt-controller; | |
273 | #interrupt-cells = <2>; | |
36af8f3e | 274 | gpio-ranges = <&iomuxc 0 96 32>; |
d02e1349 JL |
275 | }; |
276 | ||
277 | gpio5: gpio@4004d000 { | |
278 | compatible = "fsl,vf610-gpio"; | |
279 | reg = <0x4004d000 0x1000 0x400ff100 0x40>; | |
2bc88b1b | 280 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
281 | gpio-controller; |
282 | #gpio-cells = <2>; | |
283 | interrupt-controller; | |
284 | #interrupt-cells = <2>; | |
36af8f3e | 285 | gpio-ranges = <&iomuxc 0 128 7>; |
d02e1349 JL |
286 | }; |
287 | ||
288 | anatop@40050000 { | |
289 | compatible = "fsl,vf610-anatop"; | |
290 | reg = <0x40050000 0x1000>; | |
291 | }; | |
292 | ||
293 | i2c0: i2c@40066000 { | |
294 | #address-cells = <1>; | |
295 | #size-cells = <0>; | |
296 | compatible = "fsl,vf610-i2c"; | |
297 | reg = <0x40066000 0x1000>; | |
2bc88b1b | 298 | interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
299 | clocks = <&clks VF610_CLK_I2C0>; |
300 | clock-names = "ipg"; | |
b4e5e84d YY |
301 | dmas = <&edma0 0 50>, |
302 | <&edma0 0 51>; | |
303 | dma-names = "rx","tx"; | |
d02e1349 JL |
304 | status = "disabled"; |
305 | }; | |
306 | ||
307 | clks: ccm@4006b000 { | |
308 | compatible = "fsl,vf610-ccm"; | |
309 | reg = <0x4006b000 0x1000>; | |
310 | #clock-cells = <1>; | |
311 | }; | |
312 | }; | |
313 | ||
314 | aips1: aips-bus@40080000 { | |
315 | compatible = "fsl,aips-bus", "simple-bus"; | |
316 | #address-cells = <1>; | |
317 | #size-cells = <1>; | |
318 | reg = <0x40080000 0x80000>; | |
319 | ranges; | |
320 | ||
b93293b9 JL |
321 | edma1: dma-controller@40098000 { |
322 | #dma-cells = <2>; | |
323 | compatible = "fsl,vf610-edma"; | |
324 | reg = <0x40098000 0x2000>, | |
325 | <0x400a1000 0x1000>, | |
326 | <0x400a2000 0x1000>; | |
327 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, | |
328 | <0 11 IRQ_TYPE_LEVEL_HIGH>; | |
329 | interrupt-names = "edma-tx", "edma-err"; | |
330 | dma-channels = <32>; | |
331 | clock-names = "dmamux0", "dmamux1"; | |
332 | clocks = <&clks VF610_CLK_DMAMUX2>, | |
333 | <&clks VF610_CLK_DMAMUX3>; | |
334 | }; | |
335 | ||
d02e1349 JL |
336 | uart4: serial@400a9000 { |
337 | compatible = "fsl,vf610-lpuart"; | |
338 | reg = <0x400a9000 0x1000>; | |
2bc88b1b | 339 | interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
340 | clocks = <&clks VF610_CLK_UART4>; |
341 | clock-names = "ipg"; | |
342 | status = "disabled"; | |
343 | }; | |
344 | ||
345 | uart5: serial@400aa000 { | |
346 | compatible = "fsl,vf610-lpuart"; | |
347 | reg = <0x400aa000 0x1000>; | |
2bc88b1b | 348 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; |
d02e1349 JL |
349 | clocks = <&clks VF610_CLK_UART5>; |
350 | clock-names = "ipg"; | |
351 | status = "disabled"; | |
352 | }; | |
353 | ||
64436ff6 FD |
354 | adc1: adc@400bb000 { |
355 | compatible = "fsl,vf610-adc"; | |
356 | reg = <0x400bb000 0x1000>; | |
357 | interrupts = <0 54 0x04>; | |
358 | clocks = <&clks VF610_CLK_ADC1>; | |
359 | clock-names = "adc"; | |
360 | status = "disabled"; | |
361 | }; | |
362 | ||
0517fe6a CS |
363 | esdhc1: esdhc@400b2000 { |
364 | compatible = "fsl,imx53-esdhc"; | |
365 | reg = <0x400b2000 0x4000>; | |
366 | interrupts = <0 28 0x04>; | |
367 | clocks = <&clks VF610_CLK_IPG_BUS>, | |
368 | <&clks VF610_CLK_PLATFORM_BUS>, | |
369 | <&clks VF610_CLK_ESDHC1>; | |
370 | clock-names = "ipg", "ahb", "per"; | |
371 | status = "disabled"; | |
372 | }; | |
373 | ||
07513e13 XL |
374 | ftm: ftm@400b8000 { |
375 | compatible = "fsl,ftm-timer"; | |
376 | reg = <0x400b8000 0x1000 0x400b9000 0x1000>; | |
377 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; | |
378 | clock-names = "ftm-evt", "ftm-src", | |
379 | "ftm-evt-counter-en", "ftm-src-counter-en"; | |
380 | clocks = <&clks VF610_CLK_FTM2>, | |
381 | <&clks VF610_CLK_FTM3>, | |
382 | <&clks VF610_CLK_FTM2_EXT_FIX_EN>, | |
383 | <&clks VF610_CLK_FTM3_EXT_FIX_EN>; | |
384 | status = "disabled"; | |
385 | }; | |
386 | ||
d02e1349 JL |
387 | fec0: ethernet@400d0000 { |
388 | compatible = "fsl,mvf600-fec"; | |
389 | reg = <0x400d0000 0x1000>; | |
2bc88b1b | 390 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
4f71612e SG |
391 | clocks = <&clks VF610_CLK_ENET0>, |
392 | <&clks VF610_CLK_ENET0>, | |
d02e1349 JL |
393 | <&clks VF610_CLK_ENET>; |
394 | clock-names = "ipg", "ahb", "ptp"; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
398 | fec1: ethernet@400d1000 { | |
399 | compatible = "fsl,mvf600-fec"; | |
400 | reg = <0x400d1000 0x1000>; | |
2bc88b1b | 401 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
4f71612e SG |
402 | clocks = <&clks VF610_CLK_ENET1>, |
403 | <&clks VF610_CLK_ENET1>, | |
d02e1349 JL |
404 | <&clks VF610_CLK_ENET>; |
405 | clock-names = "ipg", "ahb", "ptp"; | |
406 | status = "disabled"; | |
407 | }; | |
408 | }; | |
409 | }; | |
410 | }; |