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Commit | Line | Data |
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4606c480 TP |
1 | /* |
2 | * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "wm,wm8750"; | |
13 | ||
14 | cpus { | |
15 | #address-cells = <0>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu { | |
19 | device_type = "cpu"; | |
7007c60c | 20 | compatible = "arm,arm1176jzf"; |
4606c480 TP |
21 | }; |
22 | }; | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart0; | |
26 | serial1 = &uart1; | |
27 | serial2 = &uart2; | |
28 | serial3 = &uart3; | |
29 | serial4 = &uart4; | |
30 | serial5 = &uart5; | |
31 | i2c0 = &i2c_0; | |
32 | i2c1 = &i2c_1; | |
33 | }; | |
34 | ||
35 | soc { | |
36 | #address-cells = <1>; | |
37 | #size-cells = <1>; | |
38 | compatible = "simple-bus"; | |
39 | ranges; | |
40 | interrupt-parent = <&intc0>; | |
41 | ||
42 | intc0: interrupt-controller@d8140000 { | |
43 | compatible = "via,vt8500-intc"; | |
44 | interrupt-controller; | |
45 | reg = <0xd8140000 0x10000>; | |
46 | #interrupt-cells = <1>; | |
47 | }; | |
48 | ||
49 | /* Secondary IC cascaded to intc0 */ | |
50 | intc1: interrupt-controller@d8150000 { | |
51 | compatible = "via,vt8500-intc"; | |
52 | interrupt-controller; | |
53 | #interrupt-cells = <1>; | |
54 | reg = <0xD8150000 0x10000>; | |
55 | interrupts = <56 57 58 59 60 61 62 63>; | |
56 | }; | |
57 | ||
58 | pinctrl: pinctrl@d8110000 { | |
59 | compatible = "wm,wm8750-pinctrl"; | |
60 | reg = <0xd8110000 0x10000>; | |
61 | interrupt-controller; | |
62 | #interrupt-cells = <2>; | |
63 | gpio-controller; | |
64 | #gpio-cells = <2>; | |
65 | }; | |
66 | ||
67 | pmc@d8130000 { | |
68 | compatible = "via,vt8500-pmc"; | |
69 | reg = <0xd8130000 0x1000>; | |
70 | ||
71 | clocks { | |
72 | #address-cells = <1>; | |
73 | #size-cells = <0>; | |
74 | ||
75 | ref24: ref24M { | |
76 | #clock-cells = <0>; | |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <24000000>; | |
79 | }; | |
80 | ||
81 | ref25: ref25M { | |
82 | #clock-cells = <0>; | |
83 | compatible = "fixed-clock"; | |
84 | clock-frequency = <25000000>; | |
85 | }; | |
86 | ||
87 | plla: plla { | |
88 | #clock-cells = <0>; | |
89 | compatible = "wm,wm8750-pll-clock"; | |
90 | clocks = <&ref25>; | |
91 | reg = <0x200>; | |
92 | }; | |
93 | ||
94 | pllb: pllb { | |
95 | #clock-cells = <0>; | |
96 | compatible = "wm,wm8750-pll-clock"; | |
97 | clocks = <&ref25>; | |
98 | reg = <0x204>; | |
99 | }; | |
100 | ||
101 | pllc: pllc { | |
102 | #clock-cells = <0>; | |
103 | compatible = "wm,wm8750-pll-clock"; | |
104 | clocks = <&ref25>; | |
105 | reg = <0x208>; | |
106 | }; | |
107 | ||
108 | plld: plld { | |
109 | #clock-cells = <0>; | |
110 | compatible = "wm,wm8750-pll-clock"; | |
111 | clocks = <&ref25>; | |
112 | reg = <0x20C>; | |
113 | }; | |
114 | ||
115 | plle: plle { | |
116 | #clock-cells = <0>; | |
117 | compatible = "wm,wm8750-pll-clock"; | |
118 | clocks = <&ref25>; | |
119 | reg = <0x210>; | |
120 | }; | |
121 | ||
122 | clkarm: arm { | |
123 | #clock-cells = <0>; | |
124 | compatible = "via,vt8500-device-clock"; | |
125 | clocks = <&plla>; | |
126 | divisor-reg = <0x300>; | |
127 | }; | |
128 | ||
129 | clkahb: ahb { | |
130 | #clock-cells = <0>; | |
131 | compatible = "via,vt8500-device-clock"; | |
132 | clocks = <&pllb>; | |
133 | divisor-reg = <0x304>; | |
134 | }; | |
135 | ||
9e7b6d3e TP |
136 | clkapb: apb { |
137 | #clock-cells = <0>; | |
138 | compatible = "via,vt8500-device-clock"; | |
139 | clocks = <&pllb>; | |
140 | divisor-reg = <0x320>; | |
141 | }; | |
142 | ||
4606c480 TP |
143 | clkddr: ddr { |
144 | #clock-cells = <0>; | |
145 | compatible = "via,vt8500-device-clock"; | |
146 | clocks = <&plld>; | |
147 | divisor-reg = <0x310>; | |
148 | }; | |
149 | ||
150 | clkuart0: uart0 { | |
151 | #clock-cells = <0>; | |
152 | compatible = "via,vt8500-device-clock"; | |
153 | clocks = <&ref24>; | |
154 | enable-reg = <0x254>; | |
155 | enable-bit = <24>; | |
156 | }; | |
157 | ||
158 | clkuart1: uart1 { | |
159 | #clock-cells = <0>; | |
160 | compatible = "via,vt8500-device-clock"; | |
161 | clocks = <&ref24>; | |
162 | enable-reg = <0x254>; | |
163 | enable-bit = <25>; | |
164 | }; | |
165 | ||
166 | clkuart2: uart2 { | |
167 | #clock-cells = <0>; | |
168 | compatible = "via,vt8500-device-clock"; | |
169 | clocks = <&ref24>; | |
170 | enable-reg = <0x254>; | |
171 | enable-bit = <26>; | |
172 | }; | |
173 | ||
174 | clkuart3: uart3 { | |
175 | #clock-cells = <0>; | |
176 | compatible = "via,vt8500-device-clock"; | |
177 | clocks = <&ref24>; | |
178 | enable-reg = <0x254>; | |
179 | enable-bit = <27>; | |
180 | }; | |
181 | ||
182 | clkuart4: uart4 { | |
183 | #clock-cells = <0>; | |
184 | compatible = "via,vt8500-device-clock"; | |
185 | clocks = <&ref24>; | |
186 | enable-reg = <0x254>; | |
187 | enable-bit = <28>; | |
188 | }; | |
189 | ||
190 | clkuart5: uart5 { | |
191 | #clock-cells = <0>; | |
192 | compatible = "via,vt8500-device-clock"; | |
193 | clocks = <&ref24>; | |
194 | enable-reg = <0x254>; | |
195 | enable-bit = <29>; | |
196 | }; | |
197 | ||
198 | clkpwm: pwm { | |
199 | #clock-cells = <0>; | |
200 | compatible = "via,vt8500-device-clock"; | |
201 | clocks = <&pllb>; | |
202 | divisor-reg = <0x350>; | |
203 | enable-reg = <0x250>; | |
204 | enable-bit = <17>; | |
205 | }; | |
206 | ||
207 | clksdhc: sdhc { | |
208 | #clock-cells = <0>; | |
209 | compatible = "via,vt8500-device-clock"; | |
210 | clocks = <&pllb>; | |
211 | divisor-reg = <0x330>; | |
212 | divisor-mask = <0x3f>; | |
213 | enable-reg = <0x250>; | |
214 | enable-bit = <0>; | |
215 | }; | |
216 | ||
217 | clki2c0: i2c0clk { | |
218 | #clock-cells = <0>; | |
219 | compatible = "via,vt8500-device-clock"; | |
220 | clocks = <&pllb>; | |
221 | divisor-reg = <0x3A0>; | |
222 | enable-reg = <0x250>; | |
223 | enable-bit = <8>; | |
224 | }; | |
225 | ||
226 | clki2c1: i2c1clk { | |
227 | #clock-cells = <0>; | |
228 | compatible = "via,vt8500-device-clock"; | |
229 | clocks = <&pllb>; | |
230 | divisor-reg = <0x3A4>; | |
231 | enable-reg = <0x250>; | |
232 | enable-bit = <9>; | |
233 | }; | |
234 | }; | |
235 | }; | |
236 | ||
237 | pwm: pwm@d8220000 { | |
238 | #pwm-cells = <3>; | |
239 | compatible = "via,vt8500-pwm"; | |
240 | reg = <0xd8220000 0x100>; | |
241 | clocks = <&clkpwm>; | |
242 | }; | |
243 | ||
244 | timer@d8130100 { | |
245 | compatible = "via,vt8500-timer"; | |
246 | reg = <0xd8130100 0x28>; | |
247 | interrupts = <36>; | |
248 | }; | |
249 | ||
250 | ehci@d8007900 { | |
251 | compatible = "via,vt8500-ehci"; | |
252 | reg = <0xd8007900 0x200>; | |
253 | interrupts = <26>; | |
254 | }; | |
255 | ||
256 | uhci@d8007b00 { | |
257 | compatible = "platform-uhci"; | |
258 | reg = <0xd8007b00 0x200>; | |
259 | interrupts = <26>; | |
260 | }; | |
261 | ||
262 | uhci@d8008d00 { | |
263 | compatible = "platform-uhci"; | |
264 | reg = <0xd8008d00 0x200>; | |
265 | interrupts = <26>; | |
266 | }; | |
267 | ||
55954f85 | 268 | uart0: serial@d8200000 { |
4606c480 TP |
269 | compatible = "via,vt8500-uart"; |
270 | reg = <0xd8200000 0x1040>; | |
271 | interrupts = <32>; | |
272 | clocks = <&clkuart0>; | |
55954f85 | 273 | status = "disabled"; |
4606c480 TP |
274 | }; |
275 | ||
55954f85 | 276 | uart1: serial@d82b0000 { |
4606c480 TP |
277 | compatible = "via,vt8500-uart"; |
278 | reg = <0xd82b0000 0x1040>; | |
279 | interrupts = <33>; | |
280 | clocks = <&clkuart1>; | |
55954f85 | 281 | status = "disabled"; |
4606c480 TP |
282 | }; |
283 | ||
55954f85 | 284 | uart2: serial@d8210000 { |
4606c480 TP |
285 | compatible = "via,vt8500-uart"; |
286 | reg = <0xd8210000 0x1040>; | |
287 | interrupts = <47>; | |
288 | clocks = <&clkuart2>; | |
55954f85 | 289 | status = "disabled"; |
4606c480 TP |
290 | }; |
291 | ||
55954f85 | 292 | uart3: serial@d82c0000 { |
4606c480 TP |
293 | compatible = "via,vt8500-uart"; |
294 | reg = <0xd82c0000 0x1040>; | |
295 | interrupts = <50>; | |
296 | clocks = <&clkuart3>; | |
55954f85 | 297 | status = "disabled"; |
4606c480 TP |
298 | }; |
299 | ||
55954f85 | 300 | uart4: serial@d8370000 { |
4606c480 TP |
301 | compatible = "via,vt8500-uart"; |
302 | reg = <0xd8370000 0x1040>; | |
303 | interrupts = <30>; | |
304 | clocks = <&clkuart4>; | |
55954f85 | 305 | status = "disabled"; |
4606c480 TP |
306 | }; |
307 | ||
55954f85 | 308 | uart5: serial@d8380000 { |
4606c480 TP |
309 | compatible = "via,vt8500-uart"; |
310 | reg = <0xd8380000 0x1040>; | |
311 | interrupts = <43>; | |
312 | clocks = <&clkuart5>; | |
55954f85 | 313 | status = "disabled"; |
4606c480 TP |
314 | }; |
315 | ||
316 | rtc@d8100000 { | |
317 | compatible = "via,vt8500-rtc"; | |
318 | reg = <0xd8100000 0x10000>; | |
319 | interrupts = <48>; | |
320 | }; | |
321 | ||
322 | sdhc@d800a000 { | |
323 | compatible = "wm,wm8505-sdhc"; | |
324 | reg = <0xd800a000 0x1000>; | |
325 | interrupts = <20 21>; | |
326 | clocks = <&clksdhc>; | |
327 | bus-width = <4>; | |
328 | sdon-inverted; | |
329 | }; | |
330 | ||
331 | i2c_0: i2c@d8280000 { | |
332 | compatible = "wm,wm8505-i2c"; | |
333 | reg = <0xd8280000 0x1000>; | |
334 | interrupts = <19>; | |
335 | clocks = <&clki2c0>; | |
336 | clock-frequency = <400000>; | |
337 | }; | |
338 | ||
339 | i2c_1: i2c@d8320000 { | |
340 | compatible = "wm,wm8505-i2c"; | |
341 | reg = <0xd8320000 0x1000>; | |
342 | interrupts = <18>; | |
343 | clocks = <&clki2c1>; | |
344 | clock-frequency = <400000>; | |
345 | }; | |
346 | }; | |
347 | }; |