projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| def4d6c0 TP |
1 | /* |
| 2 | * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later | |
| 7 | */ | |
| 8 | ||
| def4d6c0 | 9 | / { |
| abe60a3a RH |
10 | #address-cells = <1>; |
| 11 | #size-cells = <1>; | |
| def4d6c0 TP |
12 | compatible = "wm,wm8850"; |
| 13 | ||
| 7ec13d42 TP |
14 | cpus { |
| 15 | #address-cells = <1>; | |
| 16 | #size-cells = <0>; | |
| 17 | ||
| 18 | cpu@0 { | |
| 19 | device_type = "cpu"; | |
| 20 | compatible = "arm,cortex-a9"; | |
| 21 | reg = <0x0>; | |
| 22 | }; | |
| 23 | }; | |
| 24 | ||
| abe60a3a RH |
25 | memory { |
| 26 | device_type = "memory"; | |
| 27 | reg = <0x0 0x0>; | |
| 28 | }; | |
| 29 | ||
| def4d6c0 TP |
30 | aliases { |
| 31 | serial0 = &uart0; | |
| 32 | serial1 = &uart1; | |
| 33 | serial2 = &uart2; | |
| 34 | serial3 = &uart3; | |
| 35 | }; | |
| 36 | ||
| 37 | soc { | |
| 38 | #address-cells = <1>; | |
| 39 | #size-cells = <1>; | |
| 40 | compatible = "simple-bus"; | |
| 41 | ranges; | |
| 42 | interrupt-parent = <&intc0>; | |
| 43 | ||
| 44 | intc0: interrupt-controller@d8140000 { | |
| 45 | compatible = "via,vt8500-intc"; | |
| 46 | interrupt-controller; | |
| 47 | reg = <0xd8140000 0x10000>; | |
| 48 | #interrupt-cells = <1>; | |
| 49 | }; | |
| 50 | ||
| 51 | /* Secondary IC cascaded to intc0 */ | |
| 52 | intc1: interrupt-controller@d8150000 { | |
| 53 | compatible = "via,vt8500-intc"; | |
| 54 | interrupt-controller; | |
| 55 | #interrupt-cells = <1>; | |
| 56 | reg = <0xD8150000 0x10000>; | |
| 57 | interrupts = <56 57 58 59 60 61 62 63>; | |
| 58 | }; | |
| 59 | ||
| 649a59cf TP |
60 | pinctrl: pinctrl@d8110000 { |
| 61 | compatible = "wm,wm8850-pinctrl"; | |
| def4d6c0 | 62 | reg = <0xd8110000 0x10000>; |
| 649a59cf TP |
63 | interrupt-controller; |
| 64 | #interrupt-cells = <2>; | |
| 65 | gpio-controller; | |
| 66 | #gpio-cells = <2>; | |
| def4d6c0 TP |
67 | }; |
| 68 | ||
| 69 | pmc@d8130000 { | |
| 70 | compatible = "via,vt8500-pmc"; | |
| 71 | reg = <0xd8130000 0x1000>; | |
| 72 | ||
| 73 | clocks { | |
| 74 | #address-cells = <1>; | |
| 75 | #size-cells = <0>; | |
| 76 | ||
| 77 | ref25: ref25M { | |
| 78 | #clock-cells = <0>; | |
| 79 | compatible = "fixed-clock"; | |
| 80 | clock-frequency = <25000000>; | |
| 81 | }; | |
| 82 | ||
| 83 | ref24: ref24M { | |
| 84 | #clock-cells = <0>; | |
| 85 | compatible = "fixed-clock"; | |
| 86 | clock-frequency = <24000000>; | |
| 87 | }; | |
| 88 | ||
| 89 | plla: plla { | |
| 90 | #clock-cells = <0>; | |
| 7d4c6f3c | 91 | compatible = "wm,wm8850-pll-clock"; |
| e36572b6 | 92 | clocks = <&ref24>; |
| def4d6c0 TP |
93 | reg = <0x200>; |
| 94 | }; | |
| 95 | ||
| 96 | pllb: pllb { | |
| 97 | #clock-cells = <0>; | |
| 7d4c6f3c | 98 | compatible = "wm,wm8850-pll-clock"; |
| e36572b6 | 99 | clocks = <&ref24>; |
| def4d6c0 TP |
100 | reg = <0x204>; |
| 101 | }; | |
| 102 | ||
| 5c2b0a85 TP |
103 | pllc: pllc { |
| 104 | #clock-cells = <0>; | |
| 105 | compatible = "wm,wm8850-pll-clock"; | |
| e36572b6 | 106 | clocks = <&ref24>; |
| 5c2b0a85 TP |
107 | reg = <0x208>; |
| 108 | }; | |
| 109 | ||
| 110 | plld: plld { | |
| 111 | #clock-cells = <0>; | |
| 112 | compatible = "wm,wm8850-pll-clock"; | |
| e36572b6 | 113 | clocks = <&ref24>; |
| 5c2b0a85 TP |
114 | reg = <0x20c>; |
| 115 | }; | |
| 116 | ||
| 117 | plle: plle { | |
| 118 | #clock-cells = <0>; | |
| 119 | compatible = "wm,wm8850-pll-clock"; | |
| e36572b6 | 120 | clocks = <&ref24>; |
| 5c2b0a85 TP |
121 | reg = <0x210>; |
| 122 | }; | |
| 123 | ||
| 124 | pllf: pllf { | |
| 125 | #clock-cells = <0>; | |
| 126 | compatible = "wm,wm8850-pll-clock"; | |
| e36572b6 | 127 | clocks = <&ref24>; |
| 5c2b0a85 TP |
128 | reg = <0x214>; |
| 129 | }; | |
| 130 | ||
| 131 | pllg: pllg { | |
| 132 | #clock-cells = <0>; | |
| 133 | compatible = "wm,wm8850-pll-clock"; | |
| e36572b6 | 134 | clocks = <&ref24>; |
| 5c2b0a85 TP |
135 | reg = <0x218>; |
| 136 | }; | |
| 137 | ||
| 9e7b6d3e TP |
138 | clkarm: arm { |
| 139 | #clock-cells = <0>; | |
| 140 | compatible = "via,vt8500-device-clock"; | |
| 141 | clocks = <&plla>; | |
| 142 | divisor-reg = <0x300>; | |
| 143 | }; | |
| 144 | ||
| 145 | clkahb: ahb { | |
| 146 | #clock-cells = <0>; | |
| 147 | compatible = "via,vt8500-device-clock"; | |
| 148 | clocks = <&pllb>; | |
| 149 | divisor-reg = <0x304>; | |
| 150 | }; | |
| 151 | ||
| 152 | clkapb: apb { | |
| 153 | #clock-cells = <0>; | |
| 154 | compatible = "via,vt8500-device-clock"; | |
| 155 | clocks = <&pllb>; | |
| 156 | divisor-reg = <0x320>; | |
| 157 | }; | |
| 158 | ||
| 159 | clkddr: ddr { | |
| 160 | #clock-cells = <0>; | |
| 161 | compatible = "via,vt8500-device-clock"; | |
| 162 | clocks = <&plld>; | |
| 163 | divisor-reg = <0x310>; | |
| 164 | }; | |
| 165 | ||
| def4d6c0 TP |
166 | clkuart0: uart0 { |
| 167 | #clock-cells = <0>; | |
| 168 | compatible = "via,vt8500-device-clock"; | |
| 169 | clocks = <&ref24>; | |
| 170 | enable-reg = <0x254>; | |
| 171 | enable-bit = <24>; | |
| 172 | }; | |
| 173 | ||
| 174 | clkuart1: uart1 { | |
| 175 | #clock-cells = <0>; | |
| 176 | compatible = "via,vt8500-device-clock"; | |
| 177 | clocks = <&ref24>; | |
| 178 | enable-reg = <0x254>; | |
| 179 | enable-bit = <25>; | |
| 180 | }; | |
| 181 | ||
| 182 | clkuart2: uart2 { | |
| 183 | #clock-cells = <0>; | |
| 184 | compatible = "via,vt8500-device-clock"; | |
| 185 | clocks = <&ref24>; | |
| 186 | enable-reg = <0x254>; | |
| 187 | enable-bit = <26>; | |
| 188 | }; | |
| 189 | ||
| 190 | clkuart3: uart3 { | |
| 191 | #clock-cells = <0>; | |
| 192 | compatible = "via,vt8500-device-clock"; | |
| 193 | clocks = <&ref24>; | |
| 194 | enable-reg = <0x254>; | |
| 195 | enable-bit = <27>; | |
| 196 | }; | |
| 197 | ||
| 198 | clkpwm: pwm { | |
| 199 | #clock-cells = <0>; | |
| 200 | compatible = "via,vt8500-device-clock"; | |
| 201 | clocks = <&pllb>; | |
| 202 | divisor-reg = <0x350>; | |
| 203 | enable-reg = <0x250>; | |
| 204 | enable-bit = <17>; | |
| 205 | }; | |
| 206 | ||
| 207 | clksdhc: sdhc { | |
| 208 | #clock-cells = <0>; | |
| 209 | compatible = "via,vt8500-device-clock"; | |
| 210 | clocks = <&pllb>; | |
| 211 | divisor-reg = <0x330>; | |
| 212 | divisor-mask = <0x3f>; | |
| 213 | enable-reg = <0x250>; | |
| 214 | enable-bit = <0>; | |
| 215 | }; | |
| 216 | }; | |
| 217 | }; | |
| 218 | ||
| 7ab0a484 | 219 | fb: fb@d8051700 { |
| def4d6c0 TP |
220 | compatible = "wm,wm8505-fb"; |
| 221 | reg = <0xd8051700 0x200>; | |
| def4d6c0 TP |
222 | }; |
| 223 | ||
| 224 | ge_rops@d8050400 { | |
| 225 | compatible = "wm,prizm-ge-rops"; | |
| 226 | reg = <0xd8050400 0x100>; | |
| 227 | }; | |
| 228 | ||
| 229 | pwm: pwm@d8220000 { | |
| 230 | #pwm-cells = <3>; | |
| 231 | compatible = "via,vt8500-pwm"; | |
| 232 | reg = <0xd8220000 0x100>; | |
| 233 | clocks = <&clkpwm>; | |
| 234 | }; | |
| 235 | ||
| 236 | timer@d8130100 { | |
| 237 | compatible = "via,vt8500-timer"; | |
| 238 | reg = <0xd8130100 0x28>; | |
| 239 | interrupts = <36>; | |
| 240 | }; | |
| 241 | ||
| 242 | ehci@d8007900 { | |
| 243 | compatible = "via,vt8500-ehci"; | |
| 244 | reg = <0xd8007900 0x200>; | |
| 245 | interrupts = <26>; | |
| 246 | }; | |
| 247 | ||
| 248 | uhci@d8007b00 { | |
| 249 | compatible = "platform-uhci"; | |
| 250 | reg = <0xd8007b00 0x200>; | |
| 251 | interrupts = <26>; | |
| 252 | }; | |
| 253 | ||
| 254 | uhci@d8008d00 { | |
| 255 | compatible = "platform-uhci"; | |
| 256 | reg = <0xd8008d00 0x200>; | |
| 257 | interrupts = <26>; | |
| 258 | }; | |
| 259 | ||
| 55954f85 | 260 | uart0: serial@d8200000 { |
| def4d6c0 TP |
261 | compatible = "via,vt8500-uart"; |
| 262 | reg = <0xd8200000 0x1040>; | |
| 263 | interrupts = <32>; | |
| 264 | clocks = <&clkuart0>; | |
| 55954f85 | 265 | status = "disabled"; |
| def4d6c0 TP |
266 | }; |
| 267 | ||
| 55954f85 | 268 | uart1: serial@d82b0000 { |
| def4d6c0 TP |
269 | compatible = "via,vt8500-uart"; |
| 270 | reg = <0xd82b0000 0x1040>; | |
| 271 | interrupts = <33>; | |
| 272 | clocks = <&clkuart1>; | |
| 55954f85 | 273 | status = "disabled"; |
| def4d6c0 TP |
274 | }; |
| 275 | ||
| 55954f85 | 276 | uart2: serial@d8210000 { |
| def4d6c0 TP |
277 | compatible = "via,vt8500-uart"; |
| 278 | reg = <0xd8210000 0x1040>; | |
| 279 | interrupts = <47>; | |
| 280 | clocks = <&clkuart2>; | |
| 55954f85 | 281 | status = "disabled"; |
| def4d6c0 TP |
282 | }; |
| 283 | ||
| 55954f85 | 284 | uart3: serial@d82c0000 { |
| def4d6c0 TP |
285 | compatible = "via,vt8500-uart"; |
| 286 | reg = <0xd82c0000 0x1040>; | |
| 287 | interrupts = <50>; | |
| 288 | clocks = <&clkuart3>; | |
| 55954f85 | 289 | status = "disabled"; |
| def4d6c0 TP |
290 | }; |
| 291 | ||
| 292 | rtc@d8100000 { | |
| 293 | compatible = "via,vt8500-rtc"; | |
| 294 | reg = <0xd8100000 0x10000>; | |
| 295 | interrupts = <48>; | |
| 296 | }; | |
| 297 | ||
| 298 | sdhc@d800a000 { | |
| 299 | compatible = "wm,wm8505-sdhc"; | |
| 300 | reg = <0xd800a000 0x1000>; | |
| 301 | interrupts = <20 21>; | |
| 302 | clocks = <&clksdhc>; | |
| 303 | bus-width = <4>; | |
| 304 | sdon-inverted; | |
| 305 | }; | |
| 2d283862 AC |
306 | |
| 307 | ethernet@d8004000 { | |
| 308 | compatible = "via,vt8500-rhine"; | |
| 309 | reg = <0xd8004000 0x100>; | |
| 310 | interrupts = <10>; | |
| 311 | }; | |
| def4d6c0 TP |
312 | }; |
| 313 | }; |