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def4d6c0 TP |
1 | /* |
2 | * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "wm,wm8850"; | |
13 | ||
14 | aliases { | |
15 | serial0 = &uart0; | |
16 | serial1 = &uart1; | |
17 | serial2 = &uart2; | |
18 | serial3 = &uart3; | |
19 | }; | |
20 | ||
21 | soc { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | compatible = "simple-bus"; | |
25 | ranges; | |
26 | interrupt-parent = <&intc0>; | |
27 | ||
28 | intc0: interrupt-controller@d8140000 { | |
29 | compatible = "via,vt8500-intc"; | |
30 | interrupt-controller; | |
31 | reg = <0xd8140000 0x10000>; | |
32 | #interrupt-cells = <1>; | |
33 | }; | |
34 | ||
35 | /* Secondary IC cascaded to intc0 */ | |
36 | intc1: interrupt-controller@d8150000 { | |
37 | compatible = "via,vt8500-intc"; | |
38 | interrupt-controller; | |
39 | #interrupt-cells = <1>; | |
40 | reg = <0xD8150000 0x10000>; | |
41 | interrupts = <56 57 58 59 60 61 62 63>; | |
42 | }; | |
43 | ||
44 | gpio: gpio-controller@d8110000 { | |
45 | compatible = "wm,wm8650-gpio"; | |
46 | gpio-controller; | |
47 | reg = <0xd8110000 0x10000>; | |
48 | #gpio-cells = <3>; | |
49 | }; | |
50 | ||
51 | pmc@d8130000 { | |
52 | compatible = "via,vt8500-pmc"; | |
53 | reg = <0xd8130000 0x1000>; | |
54 | ||
55 | clocks { | |
56 | #address-cells = <1>; | |
57 | #size-cells = <0>; | |
58 | ||
59 | ref25: ref25M { | |
60 | #clock-cells = <0>; | |
61 | compatible = "fixed-clock"; | |
62 | clock-frequency = <25000000>; | |
63 | }; | |
64 | ||
65 | ref24: ref24M { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-clock"; | |
68 | clock-frequency = <24000000>; | |
69 | }; | |
70 | ||
71 | plla: plla { | |
72 | #clock-cells = <0>; | |
73 | compatible = "wm,wm8750-pll-clock"; | |
74 | clocks = <&ref25>; | |
75 | reg = <0x200>; | |
76 | }; | |
77 | ||
78 | pllb: pllb { | |
79 | #clock-cells = <0>; | |
80 | compatible = "wm,wm8750-pll-clock"; | |
81 | clocks = <&ref25>; | |
82 | reg = <0x204>; | |
83 | }; | |
84 | ||
85 | clkuart0: uart0 { | |
86 | #clock-cells = <0>; | |
87 | compatible = "via,vt8500-device-clock"; | |
88 | clocks = <&ref24>; | |
89 | enable-reg = <0x254>; | |
90 | enable-bit = <24>; | |
91 | }; | |
92 | ||
93 | clkuart1: uart1 { | |
94 | #clock-cells = <0>; | |
95 | compatible = "via,vt8500-device-clock"; | |
96 | clocks = <&ref24>; | |
97 | enable-reg = <0x254>; | |
98 | enable-bit = <25>; | |
99 | }; | |
100 | ||
101 | clkuart2: uart2 { | |
102 | #clock-cells = <0>; | |
103 | compatible = "via,vt8500-device-clock"; | |
104 | clocks = <&ref24>; | |
105 | enable-reg = <0x254>; | |
106 | enable-bit = <26>; | |
107 | }; | |
108 | ||
109 | clkuart3: uart3 { | |
110 | #clock-cells = <0>; | |
111 | compatible = "via,vt8500-device-clock"; | |
112 | clocks = <&ref24>; | |
113 | enable-reg = <0x254>; | |
114 | enable-bit = <27>; | |
115 | }; | |
116 | ||
117 | clkpwm: pwm { | |
118 | #clock-cells = <0>; | |
119 | compatible = "via,vt8500-device-clock"; | |
120 | clocks = <&pllb>; | |
121 | divisor-reg = <0x350>; | |
122 | enable-reg = <0x250>; | |
123 | enable-bit = <17>; | |
124 | }; | |
125 | ||
126 | clksdhc: sdhc { | |
127 | #clock-cells = <0>; | |
128 | compatible = "via,vt8500-device-clock"; | |
129 | clocks = <&pllb>; | |
130 | divisor-reg = <0x330>; | |
131 | divisor-mask = <0x3f>; | |
132 | enable-reg = <0x250>; | |
133 | enable-bit = <0>; | |
134 | }; | |
135 | }; | |
136 | }; | |
137 | ||
138 | fb@d8051700 { | |
139 | compatible = "wm,wm8505-fb"; | |
140 | reg = <0xd8051700 0x200>; | |
141 | display = <&display>; | |
142 | default-mode = <&mode0>; | |
143 | }; | |
144 | ||
145 | ge_rops@d8050400 { | |
146 | compatible = "wm,prizm-ge-rops"; | |
147 | reg = <0xd8050400 0x100>; | |
148 | }; | |
149 | ||
150 | pwm: pwm@d8220000 { | |
151 | #pwm-cells = <3>; | |
152 | compatible = "via,vt8500-pwm"; | |
153 | reg = <0xd8220000 0x100>; | |
154 | clocks = <&clkpwm>; | |
155 | }; | |
156 | ||
157 | timer@d8130100 { | |
158 | compatible = "via,vt8500-timer"; | |
159 | reg = <0xd8130100 0x28>; | |
160 | interrupts = <36>; | |
161 | }; | |
162 | ||
163 | ehci@d8007900 { | |
164 | compatible = "via,vt8500-ehci"; | |
165 | reg = <0xd8007900 0x200>; | |
166 | interrupts = <26>; | |
167 | }; | |
168 | ||
169 | uhci@d8007b00 { | |
170 | compatible = "platform-uhci"; | |
171 | reg = <0xd8007b00 0x200>; | |
172 | interrupts = <26>; | |
173 | }; | |
174 | ||
175 | uhci@d8008d00 { | |
176 | compatible = "platform-uhci"; | |
177 | reg = <0xd8008d00 0x200>; | |
178 | interrupts = <26>; | |
179 | }; | |
180 | ||
181 | uart0: uart@d8200000 { | |
182 | compatible = "via,vt8500-uart"; | |
183 | reg = <0xd8200000 0x1040>; | |
184 | interrupts = <32>; | |
185 | clocks = <&clkuart0>; | |
186 | }; | |
187 | ||
188 | uart1: uart@d82b0000 { | |
189 | compatible = "via,vt8500-uart"; | |
190 | reg = <0xd82b0000 0x1040>; | |
191 | interrupts = <33>; | |
192 | clocks = <&clkuart1>; | |
193 | }; | |
194 | ||
195 | uart2: uart@d8210000 { | |
196 | compatible = "via,vt8500-uart"; | |
197 | reg = <0xd8210000 0x1040>; | |
198 | interrupts = <47>; | |
199 | clocks = <&clkuart2>; | |
200 | }; | |
201 | ||
202 | uart3: uart@d82c0000 { | |
203 | compatible = "via,vt8500-uart"; | |
204 | reg = <0xd82c0000 0x1040>; | |
205 | interrupts = <50>; | |
206 | clocks = <&clkuart3>; | |
207 | }; | |
208 | ||
209 | rtc@d8100000 { | |
210 | compatible = "via,vt8500-rtc"; | |
211 | reg = <0xd8100000 0x10000>; | |
212 | interrupts = <48>; | |
213 | }; | |
214 | ||
215 | sdhc@d800a000 { | |
216 | compatible = "wm,wm8505-sdhc"; | |
217 | reg = <0xd800a000 0x1000>; | |
218 | interrupts = <20 21>; | |
219 | clocks = <&clksdhc>; | |
220 | bus-width = <4>; | |
221 | sdon-inverted; | |
222 | }; | |
223 | }; | |
224 | }; |