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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 | 17 | |
41e4cdb9 SB |
18 | cpus { |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
21 | ||
22 | cpu@0 { | |
23 | compatible = "arm,cortex-a9"; | |
24 | device_type = "cpu"; | |
25 | reg = <0>; | |
26 | clocks = <&clkc 3>; | |
27 | }; | |
28 | ||
29 | cpu@1 { | |
30 | compatible = "arm,cortex-a9"; | |
31 | device_type = "cpu"; | |
32 | reg = <1>; | |
33 | clocks = <&clkc 3>; | |
34 | }; | |
35 | }; | |
36 | ||
268a8200 MS |
37 | pmu { |
38 | compatible = "arm,cortex-a9-pmu"; | |
39 | interrupts = <0 5 4>, <0 6 4>; | |
40 | interrupt-parent = <&intc>; | |
41 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | |
42 | }; | |
43 | ||
b85a3ef4 JL |
44 | amba { |
45 | compatible = "simple-bus"; | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
e06f1a9e | 48 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
49 | ranges; |
50 | ||
51 | intc: interrupt-controller@f8f01000 { | |
f447ed2d JC |
52 | compatible = "arm,cortex-a9-gic"; |
53 | #interrupt-cells = <3>; | |
54 | #address-cells = <1>; | |
b85a3ef4 | 55 | interrupt-controller; |
f447ed2d JC |
56 | reg = <0xF8F01000 0x1000>, |
57 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
58 | }; |
59 | ||
0fcfdbca JC |
60 | L2: cache-controller { |
61 | compatible = "arm,pl310-cache"; | |
62 | reg = <0xF8F02000 0x1000>; | |
39c41df9 SB |
63 | arm,data-latency = <3 2 2>; |
64 | arm,tag-latency = <2 2 2>; | |
0fcfdbca JC |
65 | cache-unified; |
66 | cache-level = <2>; | |
67 | }; | |
68 | ||
b85a3ef4 JL |
69 | uart0: uart@e0000000 { |
70 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 71 | status = "disabled"; |
30e1e285 SB |
72 | clocks = <&clkc 23>, <&clkc 40>; |
73 | clock-names = "ref_clk", "aper_clk"; | |
b85a3ef4 | 74 | reg = <0xE0000000 0x1000>; |
f447ed2d | 75 | interrupts = <0 27 4>; |
b85a3ef4 | 76 | }; |
78d6785d JC |
77 | |
78 | uart1: uart@e0001000 { | |
79 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 80 | status = "disabled"; |
30e1e285 SB |
81 | clocks = <&clkc 24>, <&clkc 41>; |
82 | clock-names = "ref_clk", "aper_clk"; | |
78d6785d JC |
83 | reg = <0xE0001000 0x1000>; |
84 | interrupts = <0 50 4>; | |
78d6785d | 85 | }; |
0f586fbf | 86 | |
982264c3 ST |
87 | gem0: ethernet@e000b000 { |
88 | compatible = "cdns,gem"; | |
89 | reg = <0xe000b000 0x4000>; | |
90 | status = "disabled"; | |
91 | interrupts = <0 22 4>; | |
92 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; | |
93 | clock-names = "pclk", "hclk", "tx_clk"; | |
94 | }; | |
95 | ||
96 | gem1: ethernet@e000c000 { | |
97 | compatible = "cdns,gem"; | |
98 | reg = <0xe000c000 0x4000>; | |
99 | status = "disabled"; | |
100 | interrupts = <0 45 4>; | |
101 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; | |
102 | clock-names = "pclk", "hclk", "tx_clk"; | |
103 | }; | |
104 | ||
3f7c7302 SB |
105 | sdhci0: ps7-sdhci@e0100000 { |
106 | compatible = "arasan,sdhci-8.9a"; | |
107 | status = "disabled"; | |
108 | clock-names = "clk_xin", "clk_ahb"; | |
109 | clocks = <&clkc 21>, <&clkc 32>; | |
110 | interrupt-parent = <&intc>; | |
111 | interrupts = <0 24 4>; | |
112 | reg = <0xe0100000 0x1000>; | |
113 | } ; | |
114 | ||
115 | sdhci1: ps7-sdhci@e0101000 { | |
116 | compatible = "arasan,sdhci-8.9a"; | |
117 | status = "disabled"; | |
118 | clock-names = "clk_xin", "clk_ahb"; | |
119 | clocks = <&clkc 22>, <&clkc 33>; | |
120 | interrupt-parent = <&intc>; | |
121 | interrupts = <0 47 4>; | |
122 | reg = <0xe0101000 0x1000>; | |
123 | } ; | |
124 | ||
0f586fbf JC |
125 | slcr: slcr@f8000000 { |
126 | compatible = "xlnx,zynq-slcr"; | |
127 | reg = <0xF8000000 0x1000>; | |
128 | ||
129 | clocks { | |
130 | #address-cells = <1>; | |
131 | #size-cells = <0>; | |
132 | ||
30e1e285 | 133 | clkc: clkc { |
0f586fbf | 134 | #clock-cells = <1>; |
30e1e285 SB |
135 | compatible = "xlnx,ps7-clkc"; |
136 | ps-clk-frequency = <33333333>; | |
137 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | |
138 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | |
139 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | |
140 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
141 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | |
142 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | |
143 | "gem1_aper", "sdio0_aper", "sdio1_aper", | |
144 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | |
145 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | |
146 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | |
147 | "dbg_trc", "dbg_apb"; | |
0f586fbf JC |
148 | }; |
149 | }; | |
150 | }; | |
91dc985c | 151 | |
fa94bd57 SB |
152 | global_timer: timer@f8f00200 { |
153 | compatible = "arm,cortex-a9-global-timer"; | |
154 | reg = <0xf8f00200 0x20>; | |
155 | interrupts = <1 11 0x301>; | |
156 | interrupt-parent = <&intc>; | |
157 | clocks = <&clkc 4>; | |
158 | }; | |
159 | ||
91dc985c | 160 | ttc0: ttc0@f8001000 { |
e932900a MS |
161 | interrupt-parent = <&intc>; |
162 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | |
163 | compatible = "cdns,ttc"; | |
30e1e285 | 164 | clocks = <&clkc 6>; |
91dc985c | 165 | reg = <0xF8001000 0x1000>; |
91dc985c JC |
166 | }; |
167 | ||
168 | ttc1: ttc1@f8002000 { | |
e932900a MS |
169 | interrupt-parent = <&intc>; |
170 | interrupts = < 0 37 4 0 38 4 0 39 4 >; | |
171 | compatible = "cdns,ttc"; | |
30e1e285 | 172 | clocks = <&clkc 6>; |
91dc985c | 173 | reg = <0xF8002000 0x1000>; |
91dc985c | 174 | }; |
2f34e0a5 MS |
175 | scutimer: scutimer@f8f00600 { |
176 | interrupt-parent = <&intc>; | |
177 | interrupts = < 1 13 0x301 >; | |
178 | compatible = "arm,cortex-a9-twd-timer"; | |
179 | reg = < 0xf8f00600 0x20 >; | |
30e1e285 | 180 | clocks = <&clkc 4>; |
2f34e0a5 | 181 | } ; |
b85a3ef4 JL |
182 | }; |
183 | }; |