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f27ecacc RK |
1 | /* |
2 | * linux/arch/arm/common/gic.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Interrupt architecture for the GIC: | |
11 | * | |
12 | * o There is one Interrupt Distributor, which receives interrupts | |
13 | * from system devices and sends them to the Interrupt Controllers. | |
14 | * | |
15 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
16 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
17 | * associated CPU. The base address of the CPU interface is usually |
18 | * aliased so that the same address points to different chips depending | |
19 | * on the CPU it is accessed from. | |
f27ecacc RK |
20 | * |
21 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
22 | * As such, the enable set/clear, pending set/clear and active bit | |
23 | * registers are banked per-cpu for these sources. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/smp.h> | |
dcb86e8c | 29 | #include <linux/cpumask.h> |
fced80c7 | 30 | #include <linux/io.h> |
f27ecacc RK |
31 | |
32 | #include <asm/irq.h> | |
f27ecacc RK |
33 | #include <asm/mach/irq.h> |
34 | #include <asm/hardware/gic.h> | |
35 | ||
c4bfa28a | 36 | static DEFINE_SPINLOCK(irq_controller_lock); |
f27ecacc | 37 | |
b3a1bde4 CM |
38 | struct gic_chip_data { |
39 | unsigned int irq_offset; | |
40 | void __iomem *dist_base; | |
41 | void __iomem *cpu_base; | |
42 | }; | |
43 | ||
44 | #ifndef MAX_GIC_NR | |
45 | #define MAX_GIC_NR 1 | |
46 | #endif | |
47 | ||
48 | static struct gic_chip_data gic_data[MAX_GIC_NR]; | |
49 | ||
50 | static inline void __iomem *gic_dist_base(unsigned int irq) | |
51 | { | |
52 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); | |
53 | return gic_data->dist_base; | |
54 | } | |
55 | ||
56 | static inline void __iomem *gic_cpu_base(unsigned int irq) | |
57 | { | |
58 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); | |
59 | return gic_data->cpu_base; | |
60 | } | |
61 | ||
62 | static inline unsigned int gic_irq(unsigned int irq) | |
63 | { | |
64 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); | |
65 | return irq - gic_data->irq_offset; | |
66 | } | |
67 | ||
f27ecacc RK |
68 | /* |
69 | * Routines to acknowledge, disable and enable interrupts | |
70 | * | |
71 | * Linux assumes that when we're done with an interrupt we need to | |
72 | * unmask it, in the same way we need to unmask an interrupt when | |
73 | * we first enable it. | |
74 | * | |
6cbdc8c5 | 75 | * The GIC has a separate notion of "end of interrupt" to re-enable |
f27ecacc RK |
76 | * an interrupt after handling, in order to support hardware |
77 | * prioritisation. | |
78 | * | |
79 | * We can make the GIC behave in the way that Linux expects by making | |
80 | * our "acknowledge" routine disable the interrupt, then mark it as | |
81 | * complete. | |
82 | */ | |
83 | static void gic_ack_irq(unsigned int irq) | |
84 | { | |
85 | u32 mask = 1 << (irq % 32); | |
c4bfa28a TG |
86 | |
87 | spin_lock(&irq_controller_lock); | |
b3a1bde4 CM |
88 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); |
89 | writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); | |
c4bfa28a | 90 | spin_unlock(&irq_controller_lock); |
f27ecacc RK |
91 | } |
92 | ||
93 | static void gic_mask_irq(unsigned int irq) | |
94 | { | |
95 | u32 mask = 1 << (irq % 32); | |
c4bfa28a TG |
96 | |
97 | spin_lock(&irq_controller_lock); | |
b3a1bde4 | 98 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); |
c4bfa28a | 99 | spin_unlock(&irq_controller_lock); |
f27ecacc RK |
100 | } |
101 | ||
102 | static void gic_unmask_irq(unsigned int irq) | |
103 | { | |
104 | u32 mask = 1 << (irq % 32); | |
c4bfa28a TG |
105 | |
106 | spin_lock(&irq_controller_lock); | |
b3a1bde4 | 107 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4); |
c4bfa28a | 108 | spin_unlock(&irq_controller_lock); |
f27ecacc RK |
109 | } |
110 | ||
a06f5466 | 111 | #ifdef CONFIG_SMP |
0de26520 | 112 | static void gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) |
f27ecacc | 113 | { |
b3a1bde4 | 114 | void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); |
f27ecacc | 115 | unsigned int shift = (irq % 4) * 8; |
0de26520 | 116 | unsigned int cpu = cpumask_first(mask_val); |
f27ecacc RK |
117 | u32 val; |
118 | ||
c4bfa28a TG |
119 | spin_lock(&irq_controller_lock); |
120 | irq_desc[irq].cpu = cpu; | |
f27ecacc RK |
121 | val = readl(reg) & ~(0xff << shift); |
122 | val |= 1 << (cpu + shift); | |
123 | writel(val, reg); | |
c4bfa28a | 124 | spin_unlock(&irq_controller_lock); |
f27ecacc | 125 | } |
a06f5466 | 126 | #endif |
f27ecacc | 127 | |
0f347bb9 | 128 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 CM |
129 | { |
130 | struct gic_chip_data *chip_data = get_irq_data(irq); | |
131 | struct irq_chip *chip = get_irq_chip(irq); | |
0f347bb9 | 132 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
133 | unsigned long status; |
134 | ||
135 | /* primary controller ack'ing */ | |
136 | chip->ack(irq); | |
137 | ||
138 | spin_lock(&irq_controller_lock); | |
139 | status = readl(chip_data->cpu_base + GIC_CPU_INTACK); | |
140 | spin_unlock(&irq_controller_lock); | |
141 | ||
0f347bb9 RK |
142 | gic_irq = (status & 0x3ff); |
143 | if (gic_irq == 1023) | |
b3a1bde4 | 144 | goto out; |
b3a1bde4 | 145 | |
0f347bb9 RK |
146 | cascade_irq = gic_irq + chip_data->irq_offset; |
147 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) | |
148 | do_bad_IRQ(cascade_irq, desc); | |
149 | else | |
150 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
151 | |
152 | out: | |
153 | /* primary controller unmasking */ | |
154 | chip->unmask(irq); | |
155 | } | |
156 | ||
38c677cb DB |
157 | static struct irq_chip gic_chip = { |
158 | .name = "GIC", | |
f27ecacc RK |
159 | .ack = gic_ack_irq, |
160 | .mask = gic_mask_irq, | |
161 | .unmask = gic_unmask_irq, | |
162 | #ifdef CONFIG_SMP | |
c4bfa28a | 163 | .set_affinity = gic_set_cpu, |
f27ecacc RK |
164 | #endif |
165 | }; | |
166 | ||
b3a1bde4 CM |
167 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
168 | { | |
169 | if (gic_nr >= MAX_GIC_NR) | |
170 | BUG(); | |
171 | if (set_irq_data(irq, &gic_data[gic_nr]) != 0) | |
172 | BUG(); | |
173 | set_irq_chained_handler(irq, gic_handle_cascade_irq); | |
174 | } | |
175 | ||
176 | void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, | |
177 | unsigned int irq_start) | |
f27ecacc RK |
178 | { |
179 | unsigned int max_irq, i; | |
180 | u32 cpumask = 1 << smp_processor_id(); | |
181 | ||
b3a1bde4 CM |
182 | if (gic_nr >= MAX_GIC_NR) |
183 | BUG(); | |
184 | ||
f27ecacc RK |
185 | cpumask |= cpumask << 8; |
186 | cpumask |= cpumask << 16; | |
187 | ||
b3a1bde4 CM |
188 | gic_data[gic_nr].dist_base = base; |
189 | gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31; | |
f27ecacc RK |
190 | |
191 | writel(0, base + GIC_DIST_CTRL); | |
192 | ||
193 | /* | |
194 | * Find out how many interrupts are supported. | |
195 | */ | |
196 | max_irq = readl(base + GIC_DIST_CTR) & 0x1f; | |
197 | max_irq = (max_irq + 1) * 32; | |
198 | ||
199 | /* | |
200 | * The GIC only supports up to 1020 interrupt sources. | |
201 | * Limit this to either the architected maximum, or the | |
202 | * platform maximum. | |
203 | */ | |
204 | if (max_irq > max(1020, NR_IRQS)) | |
205 | max_irq = max(1020, NR_IRQS); | |
206 | ||
207 | /* | |
208 | * Set all global interrupts to be level triggered, active low. | |
209 | */ | |
210 | for (i = 32; i < max_irq; i += 16) | |
211 | writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); | |
212 | ||
213 | /* | |
214 | * Set all global interrupts to this CPU only. | |
215 | */ | |
216 | for (i = 32; i < max_irq; i += 4) | |
217 | writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); | |
218 | ||
219 | /* | |
220 | * Set priority on all interrupts. | |
221 | */ | |
222 | for (i = 0; i < max_irq; i += 4) | |
223 | writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); | |
224 | ||
225 | /* | |
226 | * Disable all interrupts. | |
227 | */ | |
228 | for (i = 0; i < max_irq; i += 32) | |
229 | writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); | |
230 | ||
231 | /* | |
232 | * Setup the Linux IRQ subsystem. | |
233 | */ | |
b3a1bde4 | 234 | for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) { |
f27ecacc | 235 | set_irq_chip(i, &gic_chip); |
b3a1bde4 | 236 | set_irq_chip_data(i, &gic_data[gic_nr]); |
10dd5ce2 | 237 | set_irq_handler(i, handle_level_irq); |
f27ecacc RK |
238 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
239 | } | |
240 | ||
241 | writel(1, base + GIC_DIST_CTRL); | |
242 | } | |
243 | ||
b3a1bde4 | 244 | void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) |
f27ecacc | 245 | { |
b3a1bde4 CM |
246 | if (gic_nr >= MAX_GIC_NR) |
247 | BUG(); | |
248 | ||
249 | gic_data[gic_nr].cpu_base = base; | |
250 | ||
f27ecacc RK |
251 | writel(0xf0, base + GIC_CPU_PRIMASK); |
252 | writel(1, base + GIC_CPU_CTRL); | |
253 | } | |
254 | ||
255 | #ifdef CONFIG_SMP | |
82668104 | 256 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
f27ecacc | 257 | { |
82668104 | 258 | unsigned long map = *cpus_addr(*mask); |
f27ecacc | 259 | |
b3a1bde4 CM |
260 | /* this always happens on GIC0 */ |
261 | writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); | |
f27ecacc RK |
262 | } |
263 | #endif |