[mirror_ubuntu-artful-kernel.git] / arch / arm / common / gic.c

/*
 *  linux/arch/arm/common/gic.c
 *
 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Interrupt architecture for the GIC:
 *
 * o There is one Interrupt Distributor, which receives interrupts
 *   from system devices and sends them to the Interrupt Controllers.
 *
 * o There is one CPU Interface per CPU, which sends interrupts sent
 *   by the Distributor, and interrupts generated locally, to the
 *   associated CPU. The base address of the CPU interface is usually
 *   aliased so that the same address points to different chips depending
 *   on the CPU it is accessed from.
 *
 * Note that IRQs 0-31 are special - they are local to each CPU.
 * As such, the enable set/clear, pending set/clear and active bit
 * registers are banked per-cpu for these sources.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/io.h>

#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>

static DEFINE_SPINLOCK(irq_controller_lock);

/* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly;

struct gic_chip_data {
	unsigned int irq_offset;
	void __iomem *dist_base;
	void __iomem *cpu_base;
};

/*
 * Supported arch specific GIC irq extension.
 * Default make them NULL.
 */
struct irq_chip gic_arch_extn = {
	.irq_ack	= NULL,
	.irq_mask	= NULL,
	.irq_unmask	= NULL,
	.irq_retrigger	= NULL,
	.irq_set_type	= NULL,
	.irq_set_wake	= NULL,
};

#ifndef MAX_GIC_NR
#define MAX_GIC_NR	1
#endif

static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;

static inline void __iomem *gic_dist_base(struct irq_data *d)
{
	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
	return gic_data->dist_base;
}

static inline void __iomem *gic_cpu_base(struct irq_data *d)
{
	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
	return gic_data->cpu_base;
}

static inline unsigned int gic_irq(struct irq_data *d)
{
	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
	return d->irq - gic_data->irq_offset;
}

/*
 * Routines to acknowledge, disable and enable interrupts
 */
static void gic_ack_irq(struct irq_data *d)
{
	spin_lock(&irq_controller_lock);
	if (gic_arch_extn.irq_ack)
		gic_arch_extn.irq_ack(d);
	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
	spin_unlock(&irq_controller_lock);
}

static void gic_mask_irq(struct irq_data *d)
{
	u32 mask = 1 << (d->irq % 32);

	spin_lock(&irq_controller_lock);
	writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
	if (gic_arch_extn.irq_mask)
		gic_arch_extn.irq_mask(d);
	spin_unlock(&irq_controller_lock);
}

static void gic_unmask_irq(struct irq_data *d)
{
	u32 mask = 1 << (d->irq % 32);

	spin_lock(&irq_controller_lock);
	if (gic_arch_extn.irq_unmask)
		gic_arch_extn.irq_unmask(d);
	writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
	spin_unlock(&irq_controller_lock);
}

static int gic_set_type(struct irq_data *d, unsigned int type)
{
	void __iomem *base = gic_dist_base(d);
	unsigned int gicirq = gic_irq(d);
	u32 enablemask = 1 << (gicirq % 32);
	u32 enableoff = (gicirq / 32) * 4;
	u32 confmask = 0x2 << ((gicirq % 16) * 2);
	u32 confoff = (gicirq / 16) * 4;
	bool enabled = false;
	u32 val;

	/* Interrupt configuration for SGIs can't be changed */
	if (gicirq < 16)
		return -EINVAL;

	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
		return -EINVAL;

	spin_lock(&irq_controller_lock);

	if (gic_arch_extn.irq_set_type)
		gic_arch_extn.irq_set_type(d, type);

	val = readl(base + GIC_DIST_CONFIG + confoff);
	if (type == IRQ_TYPE_LEVEL_HIGH)
		val &= ~confmask;
	else if (type == IRQ_TYPE_EDGE_RISING)
		val |= confmask;

	/*
	 * As recommended by the spec, disable the interrupt before changing
	 * the configuration
	 */
	if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
		writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
		enabled = true;
	}

	writel(val, base + GIC_DIST_CONFIG + confoff);

	if (enabled)
		writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);

	spin_unlock(&irq_controller_lock);

	return 0;
}

static int gic_retrigger(struct irq_data *d)
{
	if (gic_arch_extn.irq_retrigger)
		return gic_arch_extn.irq_retrigger(d);

	return -ENXIO;
}

#ifdef CONFIG_SMP
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
			    bool force)
{
	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
	unsigned int shift = (d->irq % 4) * 8;
	unsigned int cpu = cpumask_first(mask_val);
	u32 val, mask, bit;

	if (cpu >= 8)
		return -EINVAL;

	mask = 0xff << shift;
	bit = 1 << (cpu + shift);

	spin_lock(&irq_controller_lock);
	d->node = cpu;
	val = readl(reg) & ~mask;
	writel(val | bit, reg);
	spin_unlock(&irq_controller_lock);

	return 0;
}
#endif

#ifdef CONFIG_PM
static int gic_set_wake(struct irq_data *d, unsigned int on)
{
	int ret = -ENXIO;

	if (gic_arch_extn.irq_set_wake)
		ret = gic_arch_extn.irq_set_wake(d, on);

	return ret;
}

#else
#define gic_set_wake	NULL
#endif

static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned int cascade_irq, gic_irq;
	unsigned long status;

	/* primary controller ack'ing */
	chip->irq_ack(&desc->irq_data);

	spin_lock(&irq_controller_lock);
	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
	spin_unlock(&irq_controller_lock);

	gic_irq = (status & 0x3ff);
	if (gic_irq == 1023)
		goto out;

	cascade_irq = gic_irq + chip_data->irq_offset;
	if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
		do_bad_IRQ(cascade_irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	/* primary controller unmasking */
	chip->irq_unmask(&desc->irq_data);
}

static struct irq_chip gic_chip = {
	.name			= "GIC",
	.irq_ack		= gic_ack_irq,
	.irq_mask		= gic_mask_irq,
	.irq_unmask		= gic_unmask_irq,
	.irq_set_type		= gic_set_type,
	.irq_retrigger		= gic_retrigger,
#ifdef CONFIG_SMP
	.irq_set_affinity	= gic_set_affinity,
#endif
	.irq_set_wake		= gic_set_wake,
};

void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{
	if (gic_nr >= MAX_GIC_NR)
		BUG();
	if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
		BUG();
	irq_set_chained_handler(irq, gic_handle_cascade_irq);
}

static void __init gic_dist_init(struct gic_chip_data *gic,
	unsigned int irq_start)
{
	unsigned int gic_irqs, irq_limit, i;
	void __iomem *base = gic->dist_base;
	u32 cpumask = 1 << smp_processor_id();

	cpumask |= cpumask << 8;
	cpumask |= cpumask << 16;

	writel(0, base + GIC_DIST_CTRL);

	/*
	 * Find out how many interrupts are supported.
	 * The GIC only supports up to 1020 interrupt sources.
	 */
	gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
	gic_irqs = (gic_irqs + 1) * 32;
	if (gic_irqs > 1020)
		gic_irqs = 1020;

	/*
	 * Set all global interrupts to be level triggered, active low.
	 */
	for (i = 32; i < gic_irqs; i += 16)
		writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);

	/*
	 * Set all global interrupts to this CPU only.
	 */
	for (i = 32; i < gic_irqs; i += 4)
		writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);

	/*
	 * Set priority on all global interrupts.
	 */
	for (i = 32; i < gic_irqs; i += 4)
		writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);

	/*
	 * Disable all interrupts.  Leave the PPI and SGIs alone
	 * as these enables are banked registers.
	 */
	for (i = 32; i < gic_irqs; i += 32)
		writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);

	/*
	 * Limit number of interrupts registered to the platform maximum
	 */
	irq_limit = gic->irq_offset + gic_irqs;
	if (WARN_ON(irq_limit > NR_IRQS))
		irq_limit = NR_IRQS;

	/*
	 * Setup the Linux IRQ subsystem.
	 */
	for (i = irq_start; i < irq_limit; i++) {
		irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
		irq_set_chip_data(i, gic);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	writel(1, base + GIC_DIST_CTRL);
}

static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
{
	void __iomem *dist_base = gic->dist_base;
	void __iomem *base = gic->cpu_base;
	int i;

	/*
	 * Deal with the banked PPI and SGI interrupts - disable all
	 * PPI interrupts, ensure all SGI interrupts are enabled.
	 */
	writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
	writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);

	/*
	 * Set priority on PPI and SGI interrupts
	 */
	for (i = 0; i < 32; i += 4)
		writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);

	writel(0xf0, base + GIC_CPU_PRIMASK);
	writel(1, base + GIC_CPU_CTRL);
}

void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
	void __iomem *dist_base, void __iomem *cpu_base)
{
	struct gic_chip_data *gic;

	BUG_ON(gic_nr >= MAX_GIC_NR);

	gic = &gic_data[gic_nr];
	gic->dist_base = dist_base;
	gic->cpu_base = cpu_base;
	gic->irq_offset = (irq_start - 1) & ~31;

	if (gic_nr == 0)
		gic_cpu_base_addr = cpu_base;

	gic_dist_init(gic, irq_start);
	gic_cpu_init(gic);
}

void __cpuinit gic_secondary_init(unsigned int gic_nr)
{
	BUG_ON(gic_nr >= MAX_GIC_NR);

	gic_cpu_init(&gic_data[gic_nr]);
}

void __cpuinit gic_enable_ppi(unsigned int irq)
{
	unsigned long flags;

	local_irq_save(flags);
	irq_set_status_flags(irq, IRQ_NOPROBE);
	gic_unmask_irq(irq_get_irq_data(irq));
	local_irq_restore(flags);
}

#ifdef CONFIG_SMP
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
	unsigned long map = *cpus_addr(*mask);

	/* this always happens on GIC0 */
	writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
Commit	Line	Data
f27ecacc RK	1	/*
	2	* linux/arch/arm/common/gic.c
	3	*
	4	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Interrupt architecture for the GIC:
	11	*
	12	* o There is one Interrupt Distributor, which receives interrupts
	13	* from system devices and sends them to the Interrupt Controllers.
	14	*
	15	* o There is one CPU Interface per CPU, which sends interrupts sent
	16	* by the Distributor, and interrupts generated locally, to the
b3a1bde4 CM	17	* associated CPU. The base address of the CPU interface is usually
	18	* aliased so that the same address points to different chips depending
	19	* on the CPU it is accessed from.
f27ecacc RK	20	*
	21	* Note that IRQs 0-31 are special - they are local to each CPU.
	22	* As such, the enable set/clear, pending set/clear and active bit
	23	* registers are banked per-cpu for these sources.
	24	*/
	25	#include <linux/init.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/smp.h>
dcb86e8c	29	#include <linux/cpumask.h>
fced80c7	30	#include <linux/io.h>
f27ecacc RK	31
f27ecacc RK	32	#include <asm/irq.h>
f27ecacc RK	33	#include <asm/mach/irq.h>
	34	#include <asm/hardware/gic.h>
	35
c4bfa28a	36	static DEFINE_SPINLOCK(irq_controller_lock);
f27ecacc	37
ff2e27ae	38	/* Address of GIC 0 CPU interface */
bef8f9ee	39	void __iomem *gic_cpu_base_addr __read_mostly;
ff2e27ae	40
b3a1bde4 CM	41	struct gic_chip_data {
	42	unsigned int irq_offset;
	43	void __iomem *dist_base;
	44	void __iomem *cpu_base;
	45	};
	46
d7ed36a4 SS	47	/*
	48	* Supported arch specific GIC irq extension.
	49	* Default make them NULL.
	50	*/
	51	struct irq_chip gic_arch_extn = {
	52	.irq_ack = NULL,
	53	.irq_mask = NULL,
	54	.irq_unmask = NULL,
	55	.irq_retrigger = NULL,
	56	.irq_set_type = NULL,
	57	.irq_set_wake = NULL,
	58	};
	59
b3a1bde4 CM	60	#ifndef MAX_GIC_NR
	61	#define MAX_GIC_NR 1
	62	#endif
	63
bef8f9ee	64	static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
b3a1bde4	65
7d1f4288	66	static inline void __iomem gic_dist_base(struct irq_data d)
b3a1bde4	67	{
7d1f4288	68	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
b3a1bde4 CM	69	return gic_data->dist_base;
	70	}
	71
7d1f4288	72	static inline void __iomem gic_cpu_base(struct irq_data d)
b3a1bde4	73	{
7d1f4288	74	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
b3a1bde4 CM	75	return gic_data->cpu_base;
	76	}
	77
7d1f4288	78	static inline unsigned int gic_irq(struct irq_data *d)
b3a1bde4	79	{
7d1f4288 LB	80	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
7d1f4288 LB	81	return d->irq - gic_data->irq_offset;
b3a1bde4 CM	82	}
b3a1bde4 CM	83
f27ecacc RK	84	/*
f27ecacc RK	85	* Routines to acknowledge, disable and enable interrupts
f27ecacc	86	*/
7d1f4288	87	static void gic_ack_irq(struct irq_data *d)
f27ecacc	88	{
c4bfa28a	89	spin_lock(&irq_controller_lock);
d7ed36a4 SS	90	if (gic_arch_extn.irq_ack)
d7ed36a4 SS	91	gic_arch_extn.irq_ack(d);
7d1f4288	92	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
c4bfa28a	93	spin_unlock(&irq_controller_lock);
f27ecacc RK	94	}
f27ecacc RK	95
7d1f4288	96	static void gic_mask_irq(struct irq_data *d)
f27ecacc	97	{
7d1f4288	98	u32 mask = 1 << (d->irq % 32);
c4bfa28a TG	99
c4bfa28a TG	100	spin_lock(&irq_controller_lock);
7d1f4288	101	writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
d7ed36a4 SS	102	if (gic_arch_extn.irq_mask)
d7ed36a4 SS	103	gic_arch_extn.irq_mask(d);
c4bfa28a	104	spin_unlock(&irq_controller_lock);
f27ecacc RK	105	}
f27ecacc RK	106
7d1f4288	107	static void gic_unmask_irq(struct irq_data *d)
f27ecacc	108	{
7d1f4288	109	u32 mask = 1 << (d->irq % 32);
c4bfa28a TG	110
c4bfa28a TG	111	spin_lock(&irq_controller_lock);
d7ed36a4 SS	112	if (gic_arch_extn.irq_unmask)
d7ed36a4 SS	113	gic_arch_extn.irq_unmask(d);
7d1f4288	114	writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
c4bfa28a	115	spin_unlock(&irq_controller_lock);
f27ecacc RK	116	}
f27ecacc RK	117
7d1f4288	118	static int gic_set_type(struct irq_data *d, unsigned int type)
5c0c1f08	119	{
7d1f4288 LB	120	void __iomem *base = gic_dist_base(d);
7d1f4288 LB	121	unsigned int gicirq = gic_irq(d);
5c0c1f08 RV	122	u32 enablemask = 1 << (gicirq % 32);
	123	u32 enableoff = (gicirq / 32) * 4;
	124	u32 confmask = 0x2 << ((gicirq % 16) * 2);
	125	u32 confoff = (gicirq / 16) * 4;
	126	bool enabled = false;
	127	u32 val;
	128
	129	/* Interrupt configuration for SGIs can't be changed */
	130	if (gicirq < 16)
	131	return -EINVAL;
	132
	133	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
	134	return -EINVAL;
	135
	136	spin_lock(&irq_controller_lock);
	137
d7ed36a4 SS	138	if (gic_arch_extn.irq_set_type)
	139	gic_arch_extn.irq_set_type(d, type);
	140
5c0c1f08 RV	141	val = readl(base + GIC_DIST_CONFIG + confoff);
	142	if (type == IRQ_TYPE_LEVEL_HIGH)
	143	val &= ~confmask;
	144	else if (type == IRQ_TYPE_EDGE_RISING)
	145	val \|= confmask;
	146
	147	/*
	148	* As recommended by the spec, disable the interrupt before changing
	149	* the configuration
	150	*/
	151	if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
	152	writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
	153	enabled = true;
	154	}
	155
	156	writel(val, base + GIC_DIST_CONFIG + confoff);
	157
	158	if (enabled)
	159	writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
	160
	161	spin_unlock(&irq_controller_lock);
	162
	163	return 0;
	164	}
	165
d7ed36a4 SS	166	static int gic_retrigger(struct irq_data *d)
	167	{
	168	if (gic_arch_extn.irq_retrigger)
	169	return gic_arch_extn.irq_retrigger(d);
	170
	171	return -ENXIO;
	172	}
	173
a06f5466	174	#ifdef CONFIG_SMP
c191789c RK	175	static int gic_set_affinity(struct irq_data d, const struct cpumask mask_val,
c191789c RK	176	bool force)
f27ecacc	177	{
7d1f4288 LB	178	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
7d1f4288 LB	179	unsigned int shift = (d->irq % 4) * 8;
0de26520	180	unsigned int cpu = cpumask_first(mask_val);
c191789c	181	u32 val, mask, bit;
f27ecacc	182
c191789c	183	if (cpu >= 8)
87507500	184	return -EINVAL;
c191789c RK	185
	186	mask = 0xff << shift;
	187	bit = 1 << (cpu + shift);
	188
	189	spin_lock(&irq_controller_lock);
7d1f4288	190	d->node = cpu;
c191789c RK	191	val = readl(reg) & ~mask;
c191789c RK	192	writel(val \| bit, reg);
c4bfa28a	193	spin_unlock(&irq_controller_lock);
d5dedd45 YL	194
d5dedd45 YL	195	return 0;
f27ecacc	196	}
a06f5466	197	#endif
f27ecacc	198
d7ed36a4 SS	199	#ifdef CONFIG_PM
	200	static int gic_set_wake(struct irq_data *d, unsigned int on)
	201	{
	202	int ret = -ENXIO;
	203
	204	if (gic_arch_extn.irq_set_wake)
	205	ret = gic_arch_extn.irq_set_wake(d, on);
	206
	207	return ret;
	208	}
	209
	210	#else
	211	#define gic_set_wake NULL
	212	#endif
	213
0f347bb9	214	static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
b3a1bde4	215	{
6845664a TG	216	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
6845664a TG	217	struct irq_chip *chip = irq_get_chip(irq);
0f347bb9	218	unsigned int cascade_irq, gic_irq;
b3a1bde4 CM	219	unsigned long status;
	220
	221	/* primary controller ack'ing */
7d1f4288	222	chip->irq_ack(&desc->irq_data);
b3a1bde4 CM	223
	224	spin_lock(&irq_controller_lock);
	225	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
	226	spin_unlock(&irq_controller_lock);
	227
0f347bb9 RK	228	gic_irq = (status & 0x3ff);
0f347bb9 RK	229	if (gic_irq == 1023)
b3a1bde4	230	goto out;
b3a1bde4	231
0f347bb9 RK	232	cascade_irq = gic_irq + chip_data->irq_offset;
	233	if (unlikely(gic_irq < 32 \|\| gic_irq > 1020 \|\| cascade_irq >= NR_IRQS))
	234	do_bad_IRQ(cascade_irq, desc);
	235	else
	236	generic_handle_irq(cascade_irq);
b3a1bde4 CM	237
	238	out:
	239	/* primary controller unmasking */
7d1f4288	240	chip->irq_unmask(&desc->irq_data);
b3a1bde4 CM	241	}
b3a1bde4 CM	242
38c677cb	243	static struct irq_chip gic_chip = {
7d1f4288 LB	244	.name = "GIC",
	245	.irq_ack = gic_ack_irq,
	246	.irq_mask = gic_mask_irq,
	247	.irq_unmask = gic_unmask_irq,
	248	.irq_set_type = gic_set_type,
d7ed36a4	249	.irq_retrigger = gic_retrigger,
f27ecacc	250	#ifdef CONFIG_SMP
c191789c	251	.irq_set_affinity = gic_set_affinity,
f27ecacc	252	#endif
d7ed36a4	253	.irq_set_wake = gic_set_wake,
f27ecacc RK	254	};
f27ecacc RK	255
b3a1bde4 CM	256	void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
	257	{
	258	if (gic_nr >= MAX_GIC_NR)
	259	BUG();
6845664a	260	if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
b3a1bde4	261	BUG();
6845664a	262	irq_set_chained_handler(irq, gic_handle_cascade_irq);
b3a1bde4 CM	263	}
b3a1bde4 CM	264
bef8f9ee	265	static void __init gic_dist_init(struct gic_chip_data *gic,
b580b899	266	unsigned int irq_start)
f27ecacc	267	{
e6afec9b	268	unsigned int gic_irqs, irq_limit, i;
bef8f9ee	269	void __iomem *base = gic->dist_base;
f27ecacc RK	270	u32 cpumask = 1 << smp_processor_id();
	271
	272	cpumask \|= cpumask << 8;
	273	cpumask \|= cpumask << 16;
	274
f27ecacc RK	275	writel(0, base + GIC_DIST_CTRL);
	276
	277	/*
	278	* Find out how many interrupts are supported.
f27ecacc	279	* The GIC only supports up to 1020 interrupt sources.
f27ecacc	280	*/
e6afec9b PM	281	gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
	282	gic_irqs = (gic_irqs + 1) * 32;
	283	if (gic_irqs > 1020)
	284	gic_irqs = 1020;
f27ecacc RK	285
	286	/*
	287	* Set all global interrupts to be level triggered, active low.
	288	*/
e6afec9b	289	for (i = 32; i < gic_irqs; i += 16)
f27ecacc RK	290	writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
	291
	292	/*
	293	* Set all global interrupts to this CPU only.
	294	*/
e6afec9b	295	for (i = 32; i < gic_irqs; i += 4)
f27ecacc RK	296	writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
	297
	298	/*
9395f6ea	299	* Set priority on all global interrupts.
f27ecacc	300	*/
e6afec9b	301	for (i = 32; i < gic_irqs; i += 4)
f27ecacc RK	302	writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
	303
	304	/*
9395f6ea RK	305	* Disable all interrupts. Leave the PPI and SGIs alone
9395f6ea RK	306	* as these enables are banked registers.
f27ecacc	307	*/
e6afec9b	308	for (i = 32; i < gic_irqs; i += 32)
f27ecacc RK	309	writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
f27ecacc RK	310
e6afec9b PM	311	/*
	312	* Limit number of interrupts registered to the platform maximum
	313	*/
bef8f9ee	314	irq_limit = gic->irq_offset + gic_irqs;
e6afec9b PM	315	if (WARN_ON(irq_limit > NR_IRQS))
	316	irq_limit = NR_IRQS;
	317
f27ecacc RK	318	/*
	319	* Setup the Linux IRQ subsystem.
	320	*/
e6afec9b	321	for (i = irq_start; i < irq_limit; i++) {
f38c02f3	322	irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
9323f261	323	irq_set_chip_data(i, gic);
f27ecacc RK	324	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	325	}
	326
	327	writel(1, base + GIC_DIST_CTRL);
	328	}
	329
bef8f9ee	330	static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
f27ecacc	331	{
bef8f9ee RK	332	void __iomem *dist_base = gic->dist_base;
bef8f9ee RK	333	void __iomem *base = gic->cpu_base;
9395f6ea RK	334	int i;
9395f6ea RK	335
9395f6ea RK	336	/*
	337	* Deal with the banked PPI and SGI interrupts - disable all
	338	* PPI interrupts, ensure all SGI interrupts are enabled.
	339	*/
	340	writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
	341	writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
	342
	343	/*
	344	* Set priority on PPI and SGI interrupts
	345	*/
	346	for (i = 0; i < 32; i += 4)
	347	writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
	348
f27ecacc RK	349	writel(0xf0, base + GIC_CPU_PRIMASK);
	350	writel(1, base + GIC_CPU_CTRL);
	351	}
	352
b580b899 RK	353	void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
	354	void __iomem dist_base, void __iomem cpu_base)
	355	{
bef8f9ee RK	356	struct gic_chip_data *gic;
	357
	358	BUG_ON(gic_nr >= MAX_GIC_NR);
	359
	360	gic = &gic_data[gic_nr];
	361	gic->dist_base = dist_base;
	362	gic->cpu_base = cpu_base;
	363	gic->irq_offset = (irq_start - 1) & ~31;
	364
ff2e27ae RK	365	if (gic_nr == 0)
ff2e27ae RK	366	gic_cpu_base_addr = cpu_base;
bef8f9ee RK	367
	368	gic_dist_init(gic, irq_start);
	369	gic_cpu_init(gic);
b580b899 RK	370	}
b580b899 RK	371
38489533 RK	372	void __cpuinit gic_secondary_init(unsigned int gic_nr)
38489533 RK	373	{
bef8f9ee RK	374	BUG_ON(gic_nr >= MAX_GIC_NR);
	375
	376	gic_cpu_init(&gic_data[gic_nr]);
38489533 RK	377	}
38489533 RK	378
ac61d143 RK	379	void __cpuinit gic_enable_ppi(unsigned int irq)
	380	{
	381	unsigned long flags;
	382
	383	local_irq_save(flags);
fdea77b8	384	irq_set_status_flags(irq, IRQ_NOPROBE);
7d1f4288	385	gic_unmask_irq(irq_get_irq_data(irq));
ac61d143 RK	386	local_irq_restore(flags);
	387	}
	388
f27ecacc	389	#ifdef CONFIG_SMP
82668104	390	void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
f27ecacc	391	{
82668104	392	unsigned long map = cpus_addr(mask);
f27ecacc	393
b3a1bde4 CM	394	/* this always happens on GIC0 */
b3a1bde4 CM	395	writel(map << 16 \| irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
f27ecacc RK	396	}
f27ecacc RK	397	#endif