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a8fc0789 MR |
1 | /* |
2 | * linux/arch/arm/common/it8152.c | |
3 | * | |
4 | * Copyright Compulab Ltd, 2002-2007 | |
5 | * Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c | |
8 | * (see this file for respective copyrights) | |
9 | * | |
10 | * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation | |
11 | * and demux code. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/ptrace.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/mm.h> | |
a8fc0789 MR |
24 | #include <linux/init.h> |
25 | #include <linux/ioport.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/io.h> | |
28 | ||
29 | #include <asm/mach/pci.h> | |
30 | #include <asm/hardware/it8152.h> | |
31 | ||
32 | #define MAX_SLOTS 21 | |
33 | ||
8cdd4572 | 34 | static void it8152_mask_irq(struct irq_data *d) |
a8fc0789 | 35 | { |
8cdd4572 LB |
36 | unsigned int irq = d->irq; |
37 | ||
a8fc0789 MR |
38 | if (irq >= IT8152_LD_IRQ(0)) { |
39 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | | |
40 | (1 << (irq - IT8152_LD_IRQ(0)))), | |
41 | IT8152_INTC_LDCNIMR); | |
42 | } else if (irq >= IT8152_LP_IRQ(0)) { | |
43 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | | |
44 | (1 << (irq - IT8152_LP_IRQ(0)))), | |
45 | IT8152_INTC_LPCNIMR); | |
46 | } else if (irq >= IT8152_PD_IRQ(0)) { | |
47 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | | |
48 | (1 << (irq - IT8152_PD_IRQ(0)))), | |
49 | IT8152_INTC_PDCNIMR); | |
50 | } | |
51 | } | |
52 | ||
8cdd4572 | 53 | static void it8152_unmask_irq(struct irq_data *d) |
a8fc0789 | 54 | { |
8cdd4572 LB |
55 | unsigned int irq = d->irq; |
56 | ||
a8fc0789 MR |
57 | if (irq >= IT8152_LD_IRQ(0)) { |
58 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & | |
59 | ~(1 << (irq - IT8152_LD_IRQ(0)))), | |
60 | IT8152_INTC_LDCNIMR); | |
61 | } else if (irq >= IT8152_LP_IRQ(0)) { | |
62 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & | |
63 | ~(1 << (irq - IT8152_LP_IRQ(0)))), | |
64 | IT8152_INTC_LPCNIMR); | |
65 | } else if (irq >= IT8152_PD_IRQ(0)) { | |
66 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & | |
67 | ~(1 << (irq - IT8152_PD_IRQ(0)))), | |
68 | IT8152_INTC_PDCNIMR); | |
69 | } | |
70 | } | |
71 | ||
a8fc0789 MR |
72 | static struct irq_chip it8152_irq_chip = { |
73 | .name = "it8152", | |
8cdd4572 LB |
74 | .irq_ack = it8152_mask_irq, |
75 | .irq_mask = it8152_mask_irq, | |
76 | .irq_unmask = it8152_unmask_irq, | |
a8fc0789 MR |
77 | }; |
78 | ||
79 | void it8152_init_irq(void) | |
80 | { | |
81 | int irq; | |
82 | ||
83 | __raw_writel((0xffff), IT8152_INTC_PDCNIMR); | |
84 | __raw_writel((0), IT8152_INTC_PDCNIRR); | |
85 | __raw_writel((0xffff), IT8152_INTC_LPCNIMR); | |
86 | __raw_writel((0), IT8152_INTC_LPCNIRR); | |
87 | __raw_writel((0xffff), IT8152_INTC_LDCNIMR); | |
88 | __raw_writel((0), IT8152_INTC_LDCNIRR); | |
89 | ||
90 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { | |
f38c02f3 TG |
91 | irq_set_chip_and_handler(irq, &it8152_irq_chip, |
92 | handle_level_irq); | |
a8fc0789 MR |
93 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
94 | } | |
95 | } | |
96 | ||
97 | void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | |
98 | { | |
99 | int bits_pd, bits_lp, bits_ld; | |
100 | int i; | |
101 | ||
a8fc0789 MR |
102 | while (1) { |
103 | /* Read all */ | |
104 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | |
105 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | |
106 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); | |
107 | ||
108 | /* Ack */ | |
109 | __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR); | |
110 | __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR); | |
111 | __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR); | |
112 | ||
113 | if (!(bits_ld | bits_lp | bits_pd)) { | |
114 | /* Re-read to guarantee, that there was a moment of | |
115 | time, when they all three were 0. */ | |
116 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | |
117 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | |
b6265177 | 118 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); |
a8fc0789 MR |
119 | if (!(bits_ld | bits_lp | bits_pd)) |
120 | return; | |
121 | } | |
122 | ||
123 | bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1); | |
124 | while (bits_pd) { | |
125 | i = __ffs(bits_pd); | |
d8aa0251 | 126 | generic_handle_irq(IT8152_PD_IRQ(i)); |
a8fc0789 MR |
127 | bits_pd &= ~(1 << i); |
128 | } | |
129 | ||
130 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); | |
131 | while (bits_lp) { | |
b6265177 | 132 | i = __ffs(bits_lp); |
d8aa0251 | 133 | generic_handle_irq(IT8152_LP_IRQ(i)); |
a8fc0789 MR |
134 | bits_lp &= ~(1 << i); |
135 | } | |
136 | ||
137 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); | |
138 | while (bits_ld) { | |
b6265177 | 139 | i = __ffs(bits_ld); |
d8aa0251 | 140 | generic_handle_irq(IT8152_LD_IRQ(i)); |
a8fc0789 MR |
141 | bits_ld &= ~(1 << i); |
142 | } | |
143 | } | |
144 | } | |
145 | ||
146 | /* mapping for on-chip devices */ | |
147 | int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
148 | { | |
149 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | |
150 | (dev->device == PCI_DEVICE_ID_ITE_8152)) { | |
151 | if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO) | |
152 | return IT8152_AUDIO_INT; | |
153 | if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB) | |
154 | return IT8152_USB_INT; | |
155 | if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA) | |
156 | return IT8152_CDMA_INT; | |
157 | } | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus, | |
163 | unsigned int devfn) | |
164 | { | |
165 | unsigned long addr = 0; | |
166 | ||
167 | if (bus->number == 0) { | |
168 | if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) | |
169 | addr = (devfn << 8); | |
170 | } else | |
171 | addr = (bus->number << 16) | (devfn << 8); | |
172 | ||
173 | return addr; | |
174 | } | |
175 | ||
176 | static int it8152_pci_read_config(struct pci_bus *bus, | |
177 | unsigned int devfn, int where, | |
178 | int size, u32 *value) | |
179 | { | |
180 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | |
181 | u32 v; | |
182 | int shift; | |
183 | ||
184 | shift = (where & 3); | |
185 | ||
186 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
187 | v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); | |
188 | ||
189 | *value = v; | |
190 | ||
191 | return PCIBIOS_SUCCESSFUL; | |
192 | } | |
193 | ||
194 | static int it8152_pci_write_config(struct pci_bus *bus, | |
195 | unsigned int devfn, int where, | |
196 | int size, u32 value) | |
197 | { | |
198 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | |
199 | u32 v, vtemp, mask = 0; | |
200 | int shift; | |
201 | ||
202 | if (size == 1) | |
203 | mask = 0xff; | |
204 | if (size == 2) | |
205 | mask = 0xffff; | |
206 | ||
207 | shift = (where & 3); | |
208 | ||
209 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
210 | vtemp = __raw_readl(IT8152_PCI_CFG_DATA); | |
211 | ||
212 | if (mask) | |
213 | vtemp &= ~(mask << (8 * shift)); | |
214 | else | |
215 | vtemp = 0; | |
216 | ||
217 | v = (value << (8 * shift)); | |
218 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
219 | __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA); | |
220 | ||
221 | return PCIBIOS_SUCCESSFUL; | |
222 | } | |
223 | ||
224 | static struct pci_ops it8152_ops = { | |
225 | .read = it8152_pci_read_config, | |
226 | .write = it8152_pci_write_config, | |
227 | }; | |
228 | ||
229 | static struct resource it8152_io = { | |
230 | .name = "IT8152 PCI I/O region", | |
231 | .flags = IORESOURCE_IO, | |
232 | }; | |
233 | ||
234 | static struct resource it8152_mem = { | |
235 | .name = "IT8152 PCI memory region", | |
236 | .start = 0x10000000, | |
237 | .end = 0x13e00000, | |
238 | .flags = IORESOURCE_MEM, | |
239 | }; | |
240 | ||
241 | /* | |
242 | * The following functions are needed for DMA bouncing. | |
b595076a | 243 | * ITE8152 chip can address up to 64MByte, so all the devices |
a8fc0789 MR |
244 | * connected to ITE8152 (PCI and USB) should have limited DMA window |
245 | */ | |
0703ed2a RK |
246 | static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) |
247 | { | |
248 | dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", | |
249 | __func__, dma_addr, size); | |
250 | return dev->bus == &pci_bus_type && | |
251 | (dma_addr + size - PHYS_OFFSET) >= SZ_64M; | |
252 | } | |
a8fc0789 MR |
253 | |
254 | /* | |
255 | * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all | |
256 | * other devices. | |
257 | */ | |
258 | static int it8152_pci_platform_notify(struct device *dev) | |
259 | { | |
260 | if (dev->bus == &pci_bus_type) { | |
261 | if (dev->dma_mask) | |
262 | *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | |
263 | dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | |
0703ed2a | 264 | dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce); |
a8fc0789 MR |
265 | } |
266 | return 0; | |
267 | } | |
268 | ||
269 | static int it8152_pci_platform_notify_remove(struct device *dev) | |
270 | { | |
271 | if (dev->bus == &pci_bus_type) | |
272 | dmabounce_unregister_dev(dev); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
710224fa FT |
277 | int dma_set_coherent_mask(struct device *dev, u64 mask) |
278 | { | |
279 | if (mask >= PHYS_OFFSET + SZ_64M - 1) | |
280 | return 0; | |
281 | ||
282 | return -EIO; | |
283 | } | |
284 | ||
a8fc0789 MR |
285 | int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) |
286 | { | |
287 | it8152_io.start = IT8152_IO_BASE + 0x12000; | |
288 | it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; | |
289 | ||
290 | sys->mem_offset = 0x10000000; | |
291 | sys->io_offset = IT8152_IO_BASE; | |
292 | ||
293 | if (request_resource(&ioport_resource, &it8152_io)) { | |
294 | printk(KERN_ERR "PCI: unable to allocate IO region\n"); | |
295 | goto err0; | |
296 | } | |
297 | if (request_resource(&iomem_resource, &it8152_mem)) { | |
298 | printk(KERN_ERR "PCI: unable to allocate memory region\n"); | |
299 | goto err1; | |
300 | } | |
301 | ||
302 | sys->resource[0] = &it8152_io; | |
303 | sys->resource[1] = &it8152_mem; | |
304 | ||
305 | if (platform_notify || platform_notify_remove) { | |
306 | printk(KERN_ERR "PCI: Can't use platform_notify\n"); | |
307 | goto err2; | |
308 | } | |
309 | ||
310 | platform_notify = it8152_pci_platform_notify; | |
311 | platform_notify_remove = it8152_pci_platform_notify_remove; | |
312 | ||
313 | return 1; | |
314 | ||
315 | err2: | |
316 | release_resource(&it8152_io); | |
317 | err1: | |
318 | release_resource(&it8152_mem); | |
319 | err0: | |
320 | return -EBUSY; | |
321 | } | |
322 | ||
323 | /* | |
324 | * If we set up a device for bus mastering, we need to check the latency | |
325 | * timer as we don't have even crappy BIOSes to set it properly. | |
326 | * The implementation is from arch/i386/pci/i386.c | |
327 | */ | |
328 | unsigned int pcibios_max_latency = 255; | |
329 | ||
330 | void pcibios_set_master(struct pci_dev *dev) | |
331 | { | |
332 | u8 lat; | |
333 | ||
334 | /* no need to update on-chip OHCI controller */ | |
335 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | |
336 | (dev->device == PCI_DEVICE_ID_ITE_8152) && | |
337 | ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)) | |
338 | return; | |
339 | ||
340 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
341 | if (lat < 16) | |
342 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
343 | else if (lat > pcibios_max_latency) | |
344 | lat = pcibios_max_latency; | |
345 | else | |
346 | return; | |
347 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", | |
348 | pci_name(dev), lat); | |
349 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
350 | } | |
351 | ||
352 | ||
353 | struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) | |
354 | { | |
355 | return pci_scan_bus(nr, &it8152_ops, sys); | |
356 | } | |
357 | ||
88a58101 | 358 | EXPORT_SYMBOL(dma_set_coherent_mask); |