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a8fc0789 MR |
1 | /* |
2 | * linux/arch/arm/common/it8152.c | |
3 | * | |
4 | * Copyright Compulab Ltd, 2002-2007 | |
5 | * Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c | |
8 | * (see this file for respective copyrights) | |
9 | * | |
10 | * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation | |
11 | * and demux code. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/ptrace.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/mm.h> | |
a8fc0789 MR |
24 | #include <linux/init.h> |
25 | #include <linux/ioport.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/io.h> | |
28 | ||
29 | #include <asm/mach/pci.h> | |
30 | #include <asm/hardware/it8152.h> | |
31 | ||
32 | #define MAX_SLOTS 21 | |
33 | ||
34 | static void it8152_mask_irq(unsigned int irq) | |
35 | { | |
36 | if (irq >= IT8152_LD_IRQ(0)) { | |
37 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | | |
38 | (1 << (irq - IT8152_LD_IRQ(0)))), | |
39 | IT8152_INTC_LDCNIMR); | |
40 | } else if (irq >= IT8152_LP_IRQ(0)) { | |
41 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | | |
42 | (1 << (irq - IT8152_LP_IRQ(0)))), | |
43 | IT8152_INTC_LPCNIMR); | |
44 | } else if (irq >= IT8152_PD_IRQ(0)) { | |
45 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | | |
46 | (1 << (irq - IT8152_PD_IRQ(0)))), | |
47 | IT8152_INTC_PDCNIMR); | |
48 | } | |
49 | } | |
50 | ||
51 | static void it8152_unmask_irq(unsigned int irq) | |
52 | { | |
53 | if (irq >= IT8152_LD_IRQ(0)) { | |
54 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & | |
55 | ~(1 << (irq - IT8152_LD_IRQ(0)))), | |
56 | IT8152_INTC_LDCNIMR); | |
57 | } else if (irq >= IT8152_LP_IRQ(0)) { | |
58 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & | |
59 | ~(1 << (irq - IT8152_LP_IRQ(0)))), | |
60 | IT8152_INTC_LPCNIMR); | |
61 | } else if (irq >= IT8152_PD_IRQ(0)) { | |
62 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & | |
63 | ~(1 << (irq - IT8152_PD_IRQ(0)))), | |
64 | IT8152_INTC_PDCNIMR); | |
65 | } | |
66 | } | |
67 | ||
a8fc0789 MR |
68 | static struct irq_chip it8152_irq_chip = { |
69 | .name = "it8152", | |
70 | .ack = it8152_mask_irq, | |
71 | .mask = it8152_mask_irq, | |
72 | .unmask = it8152_unmask_irq, | |
73 | }; | |
74 | ||
75 | void it8152_init_irq(void) | |
76 | { | |
77 | int irq; | |
78 | ||
79 | __raw_writel((0xffff), IT8152_INTC_PDCNIMR); | |
80 | __raw_writel((0), IT8152_INTC_PDCNIRR); | |
81 | __raw_writel((0xffff), IT8152_INTC_LPCNIMR); | |
82 | __raw_writel((0), IT8152_INTC_LPCNIRR); | |
83 | __raw_writel((0xffff), IT8152_INTC_LDCNIMR); | |
84 | __raw_writel((0), IT8152_INTC_LDCNIRR); | |
85 | ||
86 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { | |
87 | set_irq_chip(irq, &it8152_irq_chip); | |
88 | set_irq_handler(irq, handle_level_irq); | |
89 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
90 | } | |
91 | } | |
92 | ||
93 | void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | |
94 | { | |
95 | int bits_pd, bits_lp, bits_ld; | |
96 | int i; | |
97 | ||
a8fc0789 MR |
98 | while (1) { |
99 | /* Read all */ | |
100 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | |
101 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | |
102 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); | |
103 | ||
104 | /* Ack */ | |
105 | __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR); | |
106 | __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR); | |
107 | __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR); | |
108 | ||
109 | if (!(bits_ld | bits_lp | bits_pd)) { | |
110 | /* Re-read to guarantee, that there was a moment of | |
111 | time, when they all three were 0. */ | |
112 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | |
113 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | |
b6265177 | 114 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); |
a8fc0789 MR |
115 | if (!(bits_ld | bits_lp | bits_pd)) |
116 | return; | |
117 | } | |
118 | ||
119 | bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1); | |
120 | while (bits_pd) { | |
121 | i = __ffs(bits_pd); | |
d8aa0251 | 122 | generic_handle_irq(IT8152_PD_IRQ(i)); |
a8fc0789 MR |
123 | bits_pd &= ~(1 << i); |
124 | } | |
125 | ||
126 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); | |
127 | while (bits_lp) { | |
b6265177 | 128 | i = __ffs(bits_lp); |
d8aa0251 | 129 | generic_handle_irq(IT8152_LP_IRQ(i)); |
a8fc0789 MR |
130 | bits_lp &= ~(1 << i); |
131 | } | |
132 | ||
133 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); | |
134 | while (bits_ld) { | |
b6265177 | 135 | i = __ffs(bits_ld); |
d8aa0251 | 136 | generic_handle_irq(IT8152_LD_IRQ(i)); |
a8fc0789 MR |
137 | bits_ld &= ~(1 << i); |
138 | } | |
139 | } | |
140 | } | |
141 | ||
142 | /* mapping for on-chip devices */ | |
143 | int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
144 | { | |
145 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | |
146 | (dev->device == PCI_DEVICE_ID_ITE_8152)) { | |
147 | if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO) | |
148 | return IT8152_AUDIO_INT; | |
149 | if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB) | |
150 | return IT8152_USB_INT; | |
151 | if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA) | |
152 | return IT8152_CDMA_INT; | |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus, | |
159 | unsigned int devfn) | |
160 | { | |
161 | unsigned long addr = 0; | |
162 | ||
163 | if (bus->number == 0) { | |
164 | if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) | |
165 | addr = (devfn << 8); | |
166 | } else | |
167 | addr = (bus->number << 16) | (devfn << 8); | |
168 | ||
169 | return addr; | |
170 | } | |
171 | ||
172 | static int it8152_pci_read_config(struct pci_bus *bus, | |
173 | unsigned int devfn, int where, | |
174 | int size, u32 *value) | |
175 | { | |
176 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | |
177 | u32 v; | |
178 | int shift; | |
179 | ||
180 | shift = (where & 3); | |
181 | ||
182 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
183 | v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); | |
184 | ||
185 | *value = v; | |
186 | ||
187 | return PCIBIOS_SUCCESSFUL; | |
188 | } | |
189 | ||
190 | static int it8152_pci_write_config(struct pci_bus *bus, | |
191 | unsigned int devfn, int where, | |
192 | int size, u32 value) | |
193 | { | |
194 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | |
195 | u32 v, vtemp, mask = 0; | |
196 | int shift; | |
197 | ||
198 | if (size == 1) | |
199 | mask = 0xff; | |
200 | if (size == 2) | |
201 | mask = 0xffff; | |
202 | ||
203 | shift = (where & 3); | |
204 | ||
205 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
206 | vtemp = __raw_readl(IT8152_PCI_CFG_DATA); | |
207 | ||
208 | if (mask) | |
209 | vtemp &= ~(mask << (8 * shift)); | |
210 | else | |
211 | vtemp = 0; | |
212 | ||
213 | v = (value << (8 * shift)); | |
214 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | |
215 | __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA); | |
216 | ||
217 | return PCIBIOS_SUCCESSFUL; | |
218 | } | |
219 | ||
220 | static struct pci_ops it8152_ops = { | |
221 | .read = it8152_pci_read_config, | |
222 | .write = it8152_pci_write_config, | |
223 | }; | |
224 | ||
225 | static struct resource it8152_io = { | |
226 | .name = "IT8152 PCI I/O region", | |
227 | .flags = IORESOURCE_IO, | |
228 | }; | |
229 | ||
230 | static struct resource it8152_mem = { | |
231 | .name = "IT8152 PCI memory region", | |
232 | .start = 0x10000000, | |
233 | .end = 0x13e00000, | |
234 | .flags = IORESOURCE_MEM, | |
235 | }; | |
236 | ||
237 | /* | |
238 | * The following functions are needed for DMA bouncing. | |
b595076a | 239 | * ITE8152 chip can address up to 64MByte, so all the devices |
a8fc0789 MR |
240 | * connected to ITE8152 (PCI and USB) should have limited DMA window |
241 | */ | |
242 | ||
243 | /* | |
244 | * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all | |
245 | * other devices. | |
246 | */ | |
247 | static int it8152_pci_platform_notify(struct device *dev) | |
248 | { | |
249 | if (dev->bus == &pci_bus_type) { | |
250 | if (dev->dma_mask) | |
251 | *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | |
252 | dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | |
253 | dmabounce_register_dev(dev, 2048, 4096); | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static int it8152_pci_platform_notify_remove(struct device *dev) | |
259 | { | |
260 | if (dev->bus == &pci_bus_type) | |
261 | dmabounce_unregister_dev(dev); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
0485e18b RK |
266 | int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) |
267 | { | |
268 | dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", | |
269 | __func__, dma_addr, size); | |
270 | return (dev->bus == &pci_bus_type) && | |
271 | ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); | |
272 | } | |
273 | ||
710224fa FT |
274 | int dma_set_coherent_mask(struct device *dev, u64 mask) |
275 | { | |
276 | if (mask >= PHYS_OFFSET + SZ_64M - 1) | |
277 | return 0; | |
278 | ||
279 | return -EIO; | |
280 | } | |
281 | ||
a8fc0789 MR |
282 | int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) |
283 | { | |
284 | it8152_io.start = IT8152_IO_BASE + 0x12000; | |
285 | it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; | |
286 | ||
287 | sys->mem_offset = 0x10000000; | |
288 | sys->io_offset = IT8152_IO_BASE; | |
289 | ||
290 | if (request_resource(&ioport_resource, &it8152_io)) { | |
291 | printk(KERN_ERR "PCI: unable to allocate IO region\n"); | |
292 | goto err0; | |
293 | } | |
294 | if (request_resource(&iomem_resource, &it8152_mem)) { | |
295 | printk(KERN_ERR "PCI: unable to allocate memory region\n"); | |
296 | goto err1; | |
297 | } | |
298 | ||
299 | sys->resource[0] = &it8152_io; | |
300 | sys->resource[1] = &it8152_mem; | |
301 | ||
302 | if (platform_notify || platform_notify_remove) { | |
303 | printk(KERN_ERR "PCI: Can't use platform_notify\n"); | |
304 | goto err2; | |
305 | } | |
306 | ||
307 | platform_notify = it8152_pci_platform_notify; | |
308 | platform_notify_remove = it8152_pci_platform_notify_remove; | |
309 | ||
310 | return 1; | |
311 | ||
312 | err2: | |
313 | release_resource(&it8152_io); | |
314 | err1: | |
315 | release_resource(&it8152_mem); | |
316 | err0: | |
317 | return -EBUSY; | |
318 | } | |
319 | ||
320 | /* | |
321 | * If we set up a device for bus mastering, we need to check the latency | |
322 | * timer as we don't have even crappy BIOSes to set it properly. | |
323 | * The implementation is from arch/i386/pci/i386.c | |
324 | */ | |
325 | unsigned int pcibios_max_latency = 255; | |
326 | ||
327 | void pcibios_set_master(struct pci_dev *dev) | |
328 | { | |
329 | u8 lat; | |
330 | ||
331 | /* no need to update on-chip OHCI controller */ | |
332 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | |
333 | (dev->device == PCI_DEVICE_ID_ITE_8152) && | |
334 | ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)) | |
335 | return; | |
336 | ||
337 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
338 | if (lat < 16) | |
339 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
340 | else if (lat > pcibios_max_latency) | |
341 | lat = pcibios_max_latency; | |
342 | else | |
343 | return; | |
344 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", | |
345 | pci_name(dev), lat); | |
346 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
347 | } | |
348 | ||
349 | ||
350 | struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) | |
351 | { | |
352 | return pci_scan_bus(nr, &it8152_ops, sys); | |
353 | } | |
354 |