]>
Commit | Line | Data |
---|---|---|
e3887714 | 1 | /* |
8a9618f5 | 2 | * linux/arch/arm/common/timer-sp.c |
e3887714 RK |
3 | * |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
7ff550de | 21 | #include <linux/clk.h> |
e3887714 RK |
22 | #include <linux/clocksource.h> |
23 | #include <linux/clockchips.h> | |
7ff550de | 24 | #include <linux/err.h> |
e3887714 RK |
25 | #include <linux/interrupt.h> |
26 | #include <linux/irq.h> | |
27 | #include <linux/io.h> | |
28 | ||
29 | #include <asm/hardware/arm_timer.h> | |
30 | ||
e3887714 | 31 | /* |
4ce17552 | 32 | * These timers are currently always setup to be clocked at 1MHz. |
e3887714 | 33 | */ |
4ce17552 RK |
34 | #define TIMER_FREQ_KHZ (1000) |
35 | #define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) | |
e3887714 | 36 | |
7ff550de RK |
37 | static long __init sp804_get_clock_rate(const char *name) |
38 | { | |
39 | struct clk *clk; | |
40 | long rate; | |
41 | int err; | |
42 | ||
43 | clk = clk_get_sys("sp804", name); | |
44 | if (IS_ERR(clk)) { | |
45 | pr_err("sp804: %s clock not found: %d\n", name, | |
46 | (int)PTR_ERR(clk)); | |
47 | return PTR_ERR(clk); | |
48 | } | |
49 | ||
50 | err = clk_enable(clk); | |
51 | if (err) { | |
52 | pr_err("sp804: %s clock failed to enable: %d\n", name, err); | |
53 | clk_put(clk); | |
54 | return err; | |
55 | } | |
56 | ||
57 | rate = clk_get_rate(clk); | |
58 | if (rate < 0) { | |
59 | pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); | |
60 | clk_disable(clk); | |
61 | clk_put(clk); | |
62 | } | |
63 | ||
64 | return rate; | |
65 | } | |
66 | ||
fb593cf3 | 67 | void __init sp804_clocksource_init(void __iomem *base, const char *name) |
e3887714 | 68 | { |
7ff550de RK |
69 | long rate = sp804_get_clock_rate(name); |
70 | ||
71 | if (rate < 0) | |
72 | return; | |
73 | ||
e3887714 | 74 | /* setup timer 0 as free-running clocksource */ |
bfe45e0b RK |
75 | writel(0, base + TIMER_CTRL); |
76 | writel(0xffffffff, base + TIMER_LOAD); | |
77 | writel(0xffffffff, base + TIMER_VALUE); | |
e3887714 | 78 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
bfe45e0b | 79 | base + TIMER_CTRL); |
e3887714 | 80 | |
fb593cf3 | 81 | clocksource_mmio_init(base + TIMER_VALUE, name, |
7ff550de | 82 | rate, 200, 32, clocksource_mmio_readl_down); |
e3887714 RK |
83 | } |
84 | ||
85 | ||
86 | static void __iomem *clkevt_base; | |
87 | ||
88 | /* | |
89 | * IRQ handler for the timer | |
90 | */ | |
91 | static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) | |
92 | { | |
93 | struct clock_event_device *evt = dev_id; | |
94 | ||
95 | /* clear the interrupt */ | |
96 | writel(1, clkevt_base + TIMER_INTCLR); | |
97 | ||
98 | evt->event_handler(evt); | |
99 | ||
100 | return IRQ_HANDLED; | |
101 | } | |
102 | ||
103 | static void sp804_set_mode(enum clock_event_mode mode, | |
104 | struct clock_event_device *evt) | |
105 | { | |
106 | unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE; | |
107 | ||
108 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
109 | ||
110 | switch (mode) { | |
111 | case CLOCK_EVT_MODE_PERIODIC: | |
112 | writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); | |
113 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | |
114 | break; | |
115 | ||
116 | case CLOCK_EVT_MODE_ONESHOT: | |
117 | /* period set, and timer enabled in 'next_event' hook */ | |
118 | ctrl |= TIMER_CTRL_ONESHOT; | |
119 | break; | |
120 | ||
121 | case CLOCK_EVT_MODE_UNUSED: | |
122 | case CLOCK_EVT_MODE_SHUTDOWN: | |
123 | default: | |
124 | break; | |
125 | } | |
126 | ||
127 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
128 | } | |
129 | ||
130 | static int sp804_set_next_event(unsigned long next, | |
131 | struct clock_event_device *evt) | |
132 | { | |
133 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | |
134 | ||
135 | writel(next, clkevt_base + TIMER_LOAD); | |
136 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static struct clock_event_device sp804_clockevent = { | |
142 | .name = "timer0", | |
143 | .shift = 32, | |
144 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
145 | .set_mode = sp804_set_mode, | |
146 | .set_next_event = sp804_set_next_event, | |
147 | .rating = 300, | |
148 | .cpumask = cpu_all_mask, | |
149 | }; | |
150 | ||
151 | static struct irqaction sp804_timer_irq = { | |
152 | .name = "timer", | |
153 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
154 | .handler = sp804_timer_interrupt, | |
155 | .dev_id = &sp804_clockevent, | |
156 | }; | |
157 | ||
158 | void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) | |
159 | { | |
160 | struct clock_event_device *evt = &sp804_clockevent; | |
161 | ||
162 | clkevt_base = base; | |
163 | ||
164 | evt->irq = timer_irq; | |
4ce17552 | 165 | evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); |
e3887714 RK |
166 | evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); |
167 | evt->min_delta_ns = clockevent_delta2ns(0xf, evt); | |
168 | ||
169 | setup_irq(timer_irq, &sp804_timer_irq); | |
170 | clockevents_register_device(evt); | |
171 | } |