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e3887714 | 1 | /* |
8a9618f5 | 2 | * linux/arch/arm/common/timer-sp.c |
e3887714 RK |
3 | * |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
7ff550de | 21 | #include <linux/clk.h> |
e3887714 RK |
22 | #include <linux/clocksource.h> |
23 | #include <linux/clockchips.h> | |
7ff550de | 24 | #include <linux/err.h> |
e3887714 RK |
25 | #include <linux/interrupt.h> |
26 | #include <linux/irq.h> | |
27 | #include <linux/io.h> | |
7a0eca71 RH |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
e3887714 | 31 | |
a7bf6162 | 32 | #include <asm/sched_clock.h> |
e3887714 | 33 | #include <asm/hardware/arm_timer.h> |
870e2928 | 34 | #include <asm/hardware/timer-sp.h> |
e3887714 | 35 | |
7a0eca71 | 36 | static long __init sp804_get_clock_rate(struct clk *clk) |
7ff550de | 37 | { |
7ff550de RK |
38 | long rate; |
39 | int err; | |
40 | ||
6f5ad963 RK |
41 | err = clk_prepare(clk); |
42 | if (err) { | |
7a0eca71 | 43 | pr_err("sp804: clock failed to prepare: %d\n", err); |
6f5ad963 RK |
44 | clk_put(clk); |
45 | return err; | |
46 | } | |
47 | ||
7ff550de RK |
48 | err = clk_enable(clk); |
49 | if (err) { | |
7a0eca71 | 50 | pr_err("sp804: clock failed to enable: %d\n", err); |
6f5ad963 | 51 | clk_unprepare(clk); |
7ff550de RK |
52 | clk_put(clk); |
53 | return err; | |
54 | } | |
55 | ||
56 | rate = clk_get_rate(clk); | |
57 | if (rate < 0) { | |
7a0eca71 | 58 | pr_err("sp804: clock failed to get rate: %ld\n", rate); |
7ff550de | 59 | clk_disable(clk); |
6f5ad963 | 60 | clk_unprepare(clk); |
7ff550de RK |
61 | clk_put(clk); |
62 | } | |
63 | ||
64 | return rate; | |
65 | } | |
66 | ||
a7bf6162 RH |
67 | static void __iomem *sched_clock_base; |
68 | ||
69 | static u32 sp804_read(void) | |
70 | { | |
71 | return ~readl_relaxed(sched_clock_base + TIMER_VALUE); | |
72 | } | |
73 | ||
74 | void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, | |
75 | const char *name, | |
7a0eca71 | 76 | struct clk *clk, |
a7bf6162 | 77 | int use_sched_clock) |
e3887714 | 78 | { |
7a0eca71 RH |
79 | long rate; |
80 | ||
81 | if (!clk) { | |
82 | clk = clk_get_sys("sp804", name); | |
83 | if (IS_ERR(clk)) { | |
84 | pr_err("sp804: clock not found: %d\n", | |
85 | (int)PTR_ERR(clk)); | |
86 | return; | |
87 | } | |
88 | } | |
89 | ||
90 | rate = sp804_get_clock_rate(clk); | |
7ff550de RK |
91 | |
92 | if (rate < 0) | |
93 | return; | |
94 | ||
e3887714 | 95 | /* setup timer 0 as free-running clocksource */ |
bfe45e0b RK |
96 | writel(0, base + TIMER_CTRL); |
97 | writel(0xffffffff, base + TIMER_LOAD); | |
98 | writel(0xffffffff, base + TIMER_VALUE); | |
e3887714 | 99 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
bfe45e0b | 100 | base + TIMER_CTRL); |
e3887714 | 101 | |
fb593cf3 | 102 | clocksource_mmio_init(base + TIMER_VALUE, name, |
7ff550de | 103 | rate, 200, 32, clocksource_mmio_readl_down); |
a7bf6162 RH |
104 | |
105 | if (use_sched_clock) { | |
106 | sched_clock_base = base; | |
107 | setup_sched_clock(sp804_read, 32, rate); | |
108 | } | |
e3887714 RK |
109 | } |
110 | ||
111 | ||
112 | static void __iomem *clkevt_base; | |
23828a7a | 113 | static unsigned long clkevt_reload; |
e3887714 RK |
114 | |
115 | /* | |
116 | * IRQ handler for the timer | |
117 | */ | |
118 | static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) | |
119 | { | |
120 | struct clock_event_device *evt = dev_id; | |
121 | ||
122 | /* clear the interrupt */ | |
123 | writel(1, clkevt_base + TIMER_INTCLR); | |
124 | ||
125 | evt->event_handler(evt); | |
126 | ||
127 | return IRQ_HANDLED; | |
128 | } | |
129 | ||
130 | static void sp804_set_mode(enum clock_event_mode mode, | |
131 | struct clock_event_device *evt) | |
132 | { | |
133 | unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE; | |
134 | ||
135 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
136 | ||
137 | switch (mode) { | |
138 | case CLOCK_EVT_MODE_PERIODIC: | |
23828a7a | 139 | writel(clkevt_reload, clkevt_base + TIMER_LOAD); |
e3887714 RK |
140 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; |
141 | break; | |
142 | ||
143 | case CLOCK_EVT_MODE_ONESHOT: | |
144 | /* period set, and timer enabled in 'next_event' hook */ | |
145 | ctrl |= TIMER_CTRL_ONESHOT; | |
146 | break; | |
147 | ||
148 | case CLOCK_EVT_MODE_UNUSED: | |
149 | case CLOCK_EVT_MODE_SHUTDOWN: | |
150 | default: | |
151 | break; | |
152 | } | |
153 | ||
154 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
155 | } | |
156 | ||
157 | static int sp804_set_next_event(unsigned long next, | |
158 | struct clock_event_device *evt) | |
159 | { | |
160 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | |
161 | ||
162 | writel(next, clkevt_base + TIMER_LOAD); | |
163 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static struct clock_event_device sp804_clockevent = { | |
e3887714 RK |
169 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
170 | .set_mode = sp804_set_mode, | |
171 | .set_next_event = sp804_set_next_event, | |
172 | .rating = 300, | |
e3887714 RK |
173 | }; |
174 | ||
175 | static struct irqaction sp804_timer_irq = { | |
176 | .name = "timer", | |
177 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
178 | .handler = sp804_timer_interrupt, | |
179 | .dev_id = &sp804_clockevent, | |
180 | }; | |
181 | ||
7a0eca71 | 182 | void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) |
e3887714 RK |
183 | { |
184 | struct clock_event_device *evt = &sp804_clockevent; | |
7a0eca71 RH |
185 | long rate; |
186 | ||
187 | if (!clk) | |
188 | clk = clk_get_sys("sp804", name); | |
189 | if (IS_ERR(clk)) { | |
190 | pr_err("sp804: %s clock not found: %d\n", name, | |
191 | (int)PTR_ERR(clk)); | |
192 | return; | |
193 | } | |
23828a7a | 194 | |
7a0eca71 | 195 | rate = sp804_get_clock_rate(clk); |
23828a7a RK |
196 | if (rate < 0) |
197 | return; | |
e3887714 RK |
198 | |
199 | clkevt_base = base; | |
23828a7a | 200 | clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); |
57cc4f7d RK |
201 | evt->name = name; |
202 | evt->irq = irq; | |
ea3aacf5 | 203 | evt->cpumask = cpu_possible_mask; |
e3887714 | 204 | |
7a0eca71 RH |
205 | writel(0, base + TIMER_CTRL); |
206 | ||
57cc4f7d | 207 | setup_irq(irq, &sp804_timer_irq); |
7c324d83 | 208 | clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); |
e3887714 | 209 | } |
7a0eca71 RH |
210 | |
211 | static void __init sp804_of_init(struct device_node *np) | |
212 | { | |
213 | static bool initialized = false; | |
214 | void __iomem *base; | |
215 | int irq; | |
216 | u32 irq_num = 0; | |
217 | struct clk *clk1, *clk2; | |
218 | const char *name = of_get_property(np, "compatible", NULL); | |
219 | ||
220 | base = of_iomap(np, 0); | |
221 | if (WARN_ON(!base)) | |
222 | return; | |
223 | ||
224 | /* Ensure timers are disabled */ | |
225 | writel(0, base + TIMER_CTRL); | |
226 | writel(0, base + TIMER_2_BASE + TIMER_CTRL); | |
227 | ||
228 | if (initialized || !of_device_is_available(np)) | |
229 | goto err; | |
230 | ||
231 | clk1 = of_clk_get(np, 0); | |
232 | if (IS_ERR(clk1)) | |
233 | clk1 = NULL; | |
234 | ||
235 | /* Get the 2nd clock if the timer has 2 timer clocks */ | |
236 | if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) { | |
237 | clk2 = of_clk_get(np, 1); | |
238 | if (IS_ERR(clk2)) { | |
239 | pr_err("sp804: %s clock not found: %d\n", np->name, | |
240 | (int)PTR_ERR(clk2)); | |
241 | goto err; | |
242 | } | |
243 | } else | |
244 | clk2 = clk1; | |
245 | ||
246 | irq = irq_of_parse_and_map(np, 0); | |
247 | if (irq <= 0) | |
248 | goto err; | |
249 | ||
250 | of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); | |
251 | if (irq_num == 2) { | |
252 | __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); | |
253 | __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); | |
254 | } else { | |
255 | __sp804_clockevents_init(base, irq, clk1 , name); | |
256 | __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, | |
257 | name, clk2, 1); | |
258 | } | |
259 | initialized = true; | |
260 | ||
261 | return; | |
262 | err: | |
263 | iounmap(base); | |
264 | } | |
265 | CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); | |
870e2928 RH |
266 | |
267 | static void __init integrator_cp_of_init(struct device_node *np) | |
268 | { | |
269 | static int init_count = 0; | |
270 | void __iomem *base; | |
271 | int irq; | |
272 | const char *name = of_get_property(np, "compatible", NULL); | |
273 | ||
274 | base = of_iomap(np, 0); | |
275 | if (WARN_ON(!base)) | |
276 | return; | |
277 | ||
278 | /* Ensure timer is disabled */ | |
279 | writel(0, base + TIMER_CTRL); | |
280 | ||
281 | if (init_count == 2 || !of_device_is_available(np)) | |
282 | goto err; | |
283 | ||
284 | if (!init_count) | |
285 | sp804_clocksource_init(base, name); | |
286 | else { | |
287 | irq = irq_of_parse_and_map(np, 0); | |
288 | if (irq <= 0) | |
289 | goto err; | |
290 | ||
291 | sp804_clockevents_init(base, irq, name); | |
292 | } | |
293 | ||
294 | init_count++; | |
295 | return; | |
296 | err: | |
297 | iounmap(base); | |
298 | } | |
299 | CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); |