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Commit | Line | Data |
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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/assembler.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This file contains arm architecture specific defines | |
11 | * for the different processors. | |
12 | * | |
13 | * Do not include any C declarations in this file - it is included by | |
14 | * assembler source. | |
15 | */ | |
2bc58a6f MD |
16 | #ifndef __ASM_ASSEMBLER_H__ |
17 | #define __ASM_ASSEMBLER_H__ | |
18 | ||
1da177e4 LT |
19 | #ifndef __ASSEMBLY__ |
20 | #error "Only include this from assembly code" | |
21 | #endif | |
22 | ||
23 | #include <asm/ptrace.h> | |
247055aa | 24 | #include <asm/domain.h> |
80c59daf | 25 | #include <asm/opcodes-virt.h> |
0b1f68e8 | 26 | #include <asm/asm-offsets.h> |
9a2b51b6 AR |
27 | #include <asm/page.h> |
28 | #include <asm/thread_info.h> | |
1da177e4 | 29 | |
6f6f6a70 RH |
30 | #define IOMEM(x) (x) |
31 | ||
1da177e4 LT |
32 | /* |
33 | * Endian independent macros for shifting bytes within registers. | |
34 | */ | |
35 | #ifndef __ARMEB__ | |
d98b90ea VK |
36 | #define lspull lsr |
37 | #define lspush lsl | |
1da177e4 LT |
38 | #define get_byte_0 lsl #0 |
39 | #define get_byte_1 lsr #8 | |
40 | #define get_byte_2 lsr #16 | |
41 | #define get_byte_3 lsr #24 | |
42 | #define put_byte_0 lsl #0 | |
43 | #define put_byte_1 lsl #8 | |
44 | #define put_byte_2 lsl #16 | |
45 | #define put_byte_3 lsl #24 | |
46 | #else | |
d98b90ea VK |
47 | #define lspull lsl |
48 | #define lspush lsr | |
1da177e4 LT |
49 | #define get_byte_0 lsr #24 |
50 | #define get_byte_1 lsr #16 | |
51 | #define get_byte_2 lsr #8 | |
52 | #define get_byte_3 lsl #0 | |
53 | #define put_byte_0 lsl #24 | |
54 | #define put_byte_1 lsl #16 | |
55 | #define put_byte_2 lsl #8 | |
56 | #define put_byte_3 lsl #0 | |
57 | #endif | |
58 | ||
457c2403 BD |
59 | /* Select code for any configuration running in BE8 mode */ |
60 | #ifdef CONFIG_CPU_ENDIAN_BE8 | |
61 | #define ARM_BE8(code...) code | |
62 | #else | |
63 | #define ARM_BE8(code...) | |
64 | #endif | |
65 | ||
1da177e4 LT |
66 | /* |
67 | * Data preload for architectures that support it | |
68 | */ | |
69 | #if __LINUX_ARM_ARCH__ >= 5 | |
70 | #define PLD(code...) code | |
71 | #else | |
72 | #define PLD(code...) | |
73 | #endif | |
74 | ||
2239aff6 NP |
75 | /* |
76 | * This can be used to enable code to cacheline align the destination | |
77 | * pointer when bulk writing to memory. Experiments on StrongARM and | |
78 | * XScale didn't show this a worthwhile thing to do when the cache is not | |
79 | * set to write-allocate (this would need further testing on XScale when WA | |
80 | * is used). | |
81 | * | |
82 | * On Feroceon there is much to gain however, regardless of cache mode. | |
83 | */ | |
84 | #ifdef CONFIG_CPU_FEROCEON | |
85 | #define CALGN(code...) code | |
86 | #else | |
87 | #define CALGN(code...) | |
88 | #endif | |
89 | ||
ffa47aa6 AB |
90 | #define IMM12_MASK 0xfff |
91 | ||
1da177e4 | 92 | /* |
9c42954d | 93 | * Enable and disable interrupts |
1da177e4 | 94 | */ |
59d1ff3b | 95 | #if __LINUX_ARM_ARCH__ >= 6 |
0d928b0b | 96 | .macro disable_irq_notrace |
59d1ff3b | 97 | cpsid i |
9c42954d RK |
98 | .endm |
99 | ||
0d928b0b | 100 | .macro enable_irq_notrace |
9c42954d RK |
101 | cpsie i |
102 | .endm | |
59d1ff3b | 103 | #else |
0d928b0b | 104 | .macro disable_irq_notrace |
9c42954d RK |
105 | msr cpsr_c, #PSR_I_BIT | SVC_MODE |
106 | .endm | |
107 | ||
0d928b0b | 108 | .macro enable_irq_notrace |
9c42954d RK |
109 | msr cpsr_c, #SVC_MODE |
110 | .endm | |
59d1ff3b | 111 | #endif |
9c42954d | 112 | |
3302cadd | 113 | .macro asm_trace_hardirqs_off, save=1 |
0d928b0b | 114 | #if defined(CONFIG_TRACE_IRQFLAGS) |
3302cadd | 115 | .if \save |
0d928b0b | 116 | stmdb sp!, {r0-r3, ip, lr} |
3302cadd | 117 | .endif |
0d928b0b | 118 | bl trace_hardirqs_off |
3302cadd | 119 | .if \save |
0d928b0b | 120 | ldmia sp!, {r0-r3, ip, lr} |
3302cadd | 121 | .endif |
0d928b0b UKK |
122 | #endif |
123 | .endm | |
124 | ||
3302cadd | 125 | .macro asm_trace_hardirqs_on, cond=al, save=1 |
0d928b0b UKK |
126 | #if defined(CONFIG_TRACE_IRQFLAGS) |
127 | /* | |
128 | * actually the registers should be pushed and pop'd conditionally, but | |
129 | * after bl the flags are certainly clobbered | |
130 | */ | |
3302cadd | 131 | .if \save |
0d928b0b | 132 | stmdb sp!, {r0-r3, ip, lr} |
3302cadd | 133 | .endif |
0d928b0b | 134 | bl\cond trace_hardirqs_on |
3302cadd | 135 | .if \save |
0d928b0b | 136 | ldmia sp!, {r0-r3, ip, lr} |
3302cadd | 137 | .endif |
0d928b0b UKK |
138 | #endif |
139 | .endm | |
140 | ||
3302cadd | 141 | .macro disable_irq, save=1 |
0d928b0b | 142 | disable_irq_notrace |
3302cadd | 143 | asm_trace_hardirqs_off \save |
0d928b0b UKK |
144 | .endm |
145 | ||
146 | .macro enable_irq | |
147 | asm_trace_hardirqs_on | |
148 | enable_irq_notrace | |
149 | .endm | |
9c42954d RK |
150 | /* |
151 | * Save the current IRQ state and disable IRQs. Note that this macro | |
152 | * assumes FIQs are enabled, and that the processor is in SVC mode. | |
153 | */ | |
154 | .macro save_and_disable_irqs, oldcpsr | |
55bdd694 CM |
155 | #ifdef CONFIG_CPU_V7M |
156 | mrs \oldcpsr, primask | |
157 | #else | |
9c42954d | 158 | mrs \oldcpsr, cpsr |
55bdd694 | 159 | #endif |
9c42954d | 160 | disable_irq |
1da177e4 LT |
161 | .endm |
162 | ||
8e43a905 | 163 | .macro save_and_disable_irqs_notrace, oldcpsr |
b2bf482a VM |
164 | #ifdef CONFIG_CPU_V7M |
165 | mrs \oldcpsr, primask | |
166 | #else | |
8e43a905 | 167 | mrs \oldcpsr, cpsr |
b2bf482a | 168 | #endif |
8e43a905 RV |
169 | disable_irq_notrace |
170 | .endm | |
171 | ||
1da177e4 LT |
172 | /* |
173 | * Restore interrupt state previously stored in a register. We don't | |
174 | * guarantee that this will preserve the flags. | |
175 | */ | |
0d928b0b | 176 | .macro restore_irqs_notrace, oldcpsr |
55bdd694 CM |
177 | #ifdef CONFIG_CPU_V7M |
178 | msr primask, \oldcpsr | |
179 | #else | |
1da177e4 | 180 | msr cpsr_c, \oldcpsr |
55bdd694 | 181 | #endif |
1da177e4 LT |
182 | .endm |
183 | ||
0d928b0b UKK |
184 | .macro restore_irqs, oldcpsr |
185 | tst \oldcpsr, #PSR_I_BIT | |
01e09a28 | 186 | asm_trace_hardirqs_on cond=eq |
0d928b0b UKK |
187 | restore_irqs_notrace \oldcpsr |
188 | .endm | |
189 | ||
14327c66 RK |
190 | /* |
191 | * Assembly version of "adr rd, BSYM(sym)". This should only be used to | |
192 | * reference local symbols in the same assembly file which are to be | |
193 | * resolved by the assembler. Other usage is undefined. | |
194 | */ | |
195 | .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo | |
196 | .macro badr\c, rd, sym | |
197 | #ifdef CONFIG_THUMB2_KERNEL | |
198 | adr\c \rd, \sym + 1 | |
199 | #else | |
200 | adr\c \rd, \sym | |
201 | #endif | |
202 | .endm | |
203 | .endr | |
204 | ||
39ad04cc CM |
205 | /* |
206 | * Get current thread_info. | |
207 | */ | |
208 | .macro get_thread_info, rd | |
9a2b51b6 | 209 | ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) |
39ad04cc | 210 | THUMB( mov \rd, sp ) |
9a2b51b6 AR |
211 | THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) |
212 | mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT | |
39ad04cc CM |
213 | .endm |
214 | ||
0b1f68e8 CM |
215 | /* |
216 | * Increment/decrement the preempt count. | |
217 | */ | |
218 | #ifdef CONFIG_PREEMPT_COUNT | |
219 | .macro inc_preempt_count, ti, tmp | |
220 | ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count | |
221 | add \tmp, \tmp, #1 @ increment it | |
222 | str \tmp, [\ti, #TI_PREEMPT] | |
223 | .endm | |
224 | ||
225 | .macro dec_preempt_count, ti, tmp | |
226 | ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count | |
227 | sub \tmp, \tmp, #1 @ decrement it | |
228 | str \tmp, [\ti, #TI_PREEMPT] | |
229 | .endm | |
230 | ||
231 | .macro dec_preempt_count_ti, ti, tmp | |
232 | get_thread_info \ti | |
233 | dec_preempt_count \ti, \tmp | |
234 | .endm | |
235 | #else | |
236 | .macro inc_preempt_count, ti, tmp | |
237 | .endm | |
238 | ||
239 | .macro dec_preempt_count, ti, tmp | |
240 | .endm | |
241 | ||
242 | .macro dec_preempt_count_ti, ti, tmp | |
243 | .endm | |
244 | #endif | |
245 | ||
1da177e4 LT |
246 | #define USER(x...) \ |
247 | 9999: x; \ | |
4260415f | 248 | .pushsection __ex_table,"a"; \ |
1da177e4 LT |
249 | .align 3; \ |
250 | .long 9999b,9001f; \ | |
4260415f | 251 | .popsection |
bac4e960 | 252 | |
f00ec48f RK |
253 | #ifdef CONFIG_SMP |
254 | #define ALT_SMP(instr...) \ | |
255 | 9998: instr | |
ed3768a8 DM |
256 | /* |
257 | * Note: if you get assembler errors from ALT_UP() when building with | |
258 | * CONFIG_THUMB2_KERNEL, you almost certainly need to use | |
259 | * ALT_SMP( W(instr) ... ) | |
260 | */ | |
f00ec48f RK |
261 | #define ALT_UP(instr...) \ |
262 | .pushsection ".alt.smp.init", "a" ;\ | |
263 | .long 9998b ;\ | |
ed3768a8 | 264 | 9997: instr ;\ |
89c6bc58 RK |
265 | .if . - 9997b == 2 ;\ |
266 | nop ;\ | |
267 | .endif ;\ | |
ed3768a8 DM |
268 | .if . - 9997b != 4 ;\ |
269 | .error "ALT_UP() content must assemble to exactly 4 bytes";\ | |
270 | .endif ;\ | |
f00ec48f RK |
271 | .popsection |
272 | #define ALT_UP_B(label) \ | |
273 | .equ up_b_offset, label - 9998b ;\ | |
274 | .pushsection ".alt.smp.init", "a" ;\ | |
275 | .long 9998b ;\ | |
ed3768a8 | 276 | W(b) . + up_b_offset ;\ |
f00ec48f RK |
277 | .popsection |
278 | #else | |
279 | #define ALT_SMP(instr...) | |
280 | #define ALT_UP(instr...) instr | |
281 | #define ALT_UP_B(label) b label | |
282 | #endif | |
283 | ||
d675d0bc WD |
284 | /* |
285 | * Instruction barrier | |
286 | */ | |
287 | .macro instr_sync | |
288 | #if __LINUX_ARM_ARCH__ >= 7 | |
289 | isb | |
290 | #elif __LINUX_ARM_ARCH__ == 6 | |
291 | mcr p15, 0, r0, c7, c5, 4 | |
292 | #endif | |
293 | .endm | |
294 | ||
bac4e960 RK |
295 | /* |
296 | * SMP data memory barrier | |
297 | */ | |
ed3768a8 | 298 | .macro smp_dmb mode |
bac4e960 RK |
299 | #ifdef CONFIG_SMP |
300 | #if __LINUX_ARM_ARCH__ >= 7 | |
ed3768a8 | 301 | .ifeqs "\mode","arm" |
3ea12806 | 302 | ALT_SMP(dmb ish) |
ed3768a8 | 303 | .else |
3ea12806 | 304 | ALT_SMP(W(dmb) ish) |
ed3768a8 | 305 | .endif |
bac4e960 | 306 | #elif __LINUX_ARM_ARCH__ == 6 |
f00ec48f RK |
307 | ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb |
308 | #else | |
309 | #error Incompatible SMP platform | |
bac4e960 | 310 | #endif |
ed3768a8 | 311 | .ifeqs "\mode","arm" |
f00ec48f | 312 | ALT_UP(nop) |
ed3768a8 DM |
313 | .else |
314 | ALT_UP(W(nop)) | |
315 | .endif | |
bac4e960 RK |
316 | #endif |
317 | .endm | |
b86040a5 | 318 | |
55bdd694 CM |
319 | #if defined(CONFIG_CPU_V7M) |
320 | /* | |
321 | * setmode is used to assert to be in svc mode during boot. For v7-M | |
322 | * this is done in __v7m_setup, so setmode can be empty here. | |
323 | */ | |
324 | .macro setmode, mode, reg | |
325 | .endm | |
326 | #elif defined(CONFIG_THUMB2_KERNEL) | |
b86040a5 CM |
327 | .macro setmode, mode, reg |
328 | mov \reg, #\mode | |
329 | msr cpsr_c, \reg | |
330 | .endm | |
331 | #else | |
332 | .macro setmode, mode, reg | |
333 | msr cpsr_c, #\mode | |
334 | .endm | |
335 | #endif | |
8b592783 | 336 | |
80c59daf DM |
337 | /* |
338 | * Helper macro to enter SVC mode cleanly and mask interrupts. reg is | |
339 | * a scratch register for the macro to overwrite. | |
340 | * | |
341 | * This macro is intended for forcing the CPU into SVC mode at boot time. | |
342 | * you cannot return to the original mode. | |
80c59daf DM |
343 | */ |
344 | .macro safe_svcmode_maskall reg:req | |
0e0779da | 345 | #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) |
80c59daf | 346 | mrs \reg , cpsr |
8e9c24a2 RK |
347 | eor \reg, \reg, #HYP_MODE |
348 | tst \reg, #MODE_MASK | |
80c59daf | 349 | bic \reg , \reg , #MODE_MASK |
8e9c24a2 | 350 | orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
80c59daf | 351 | THUMB( orr \reg , \reg , #PSR_T_BIT ) |
80c59daf | 352 | bne 1f |
2a552d5e | 353 | orr \reg, \reg, #PSR_A_BIT |
14327c66 | 354 | badr lr, 2f |
2a552d5e | 355 | msr spsr_cxsf, \reg |
80c59daf DM |
356 | __MSR_ELR_HYP(14) |
357 | __ERET | |
2a552d5e | 358 | 1: msr cpsr_c, \reg |
80c59daf | 359 | 2: |
1ecec696 DM |
360 | #else |
361 | /* | |
362 | * workaround for possibly broken pre-v6 hardware | |
363 | * (akita, Sharp Zaurus C-1000, PXA270-based) | |
364 | */ | |
365 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg | |
366 | #endif | |
80c59daf DM |
367 | .endm |
368 | ||
8b592783 CM |
369 | /* |
370 | * STRT/LDRT access macros with ARM and Thumb-2 variants | |
371 | */ | |
372 | #ifdef CONFIG_THUMB2_KERNEL | |
373 | ||
4e7682d0 | 374 | .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() |
8b592783 CM |
375 | 9999: |
376 | .if \inc == 1 | |
247055aa | 377 | \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] |
8b592783 | 378 | .elseif \inc == 4 |
247055aa | 379 | \instr\cond\()\t\().w \reg, [\ptr, #\off] |
8b592783 CM |
380 | .else |
381 | .error "Unsupported inc macro argument" | |
382 | .endif | |
383 | ||
4260415f | 384 | .pushsection __ex_table,"a" |
8b592783 CM |
385 | .align 3 |
386 | .long 9999b, \abort | |
4260415f | 387 | .popsection |
8b592783 CM |
388 | .endm |
389 | ||
390 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort | |
391 | @ explicit IT instruction needed because of the label | |
392 | @ introduced by the USER macro | |
393 | .ifnc \cond,al | |
394 | .if \rept == 1 | |
395 | itt \cond | |
396 | .elseif \rept == 2 | |
397 | ittt \cond | |
398 | .else | |
399 | .error "Unsupported rept macro argument" | |
400 | .endif | |
401 | .endif | |
402 | ||
403 | @ Slightly optimised to avoid incrementing the pointer twice | |
404 | usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort | |
405 | .if \rept == 2 | |
1142b71d | 406 | usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort |
8b592783 CM |
407 | .endif |
408 | ||
409 | add\cond \ptr, #\rept * \inc | |
410 | .endm | |
411 | ||
412 | #else /* !CONFIG_THUMB2_KERNEL */ | |
413 | ||
4e7682d0 | 414 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() |
8b592783 CM |
415 | .rept \rept |
416 | 9999: | |
417 | .if \inc == 1 | |
247055aa | 418 | \instr\cond\()b\()\t \reg, [\ptr], #\inc |
8b592783 | 419 | .elseif \inc == 4 |
247055aa | 420 | \instr\cond\()\t \reg, [\ptr], #\inc |
8b592783 CM |
421 | .else |
422 | .error "Unsupported inc macro argument" | |
423 | .endif | |
424 | ||
4260415f | 425 | .pushsection __ex_table,"a" |
8b592783 CM |
426 | .align 3 |
427 | .long 9999b, \abort | |
4260415f | 428 | .popsection |
8b592783 CM |
429 | .endr |
430 | .endm | |
431 | ||
432 | #endif /* CONFIG_THUMB2_KERNEL */ | |
433 | ||
434 | .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f | |
435 | usracc str, \reg, \ptr, \inc, \cond, \rept, \abort | |
436 | .endm | |
437 | ||
438 | .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f | |
439 | usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort | |
440 | .endm | |
8f51965e DM |
441 | |
442 | /* Utility macro for declaring string literals */ | |
443 | .macro string name:req, string | |
444 | .type \name , #object | |
445 | \name: | |
446 | .asciz "\string" | |
447 | .size \name , . - \name | |
448 | .endm | |
449 | ||
8404663f RK |
450 | .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req |
451 | #ifndef CONFIG_CPU_USE_DOMAINS | |
452 | adds \tmp, \addr, #\size - 1 | |
453 | sbcccs \tmp, \tmp, \limit | |
454 | bcs \bad | |
455 | #endif | |
456 | .endm | |
457 | ||
2190fed6 | 458 | .macro uaccess_disable, tmp, isb=1 |
a5e090ac RK |
459 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
460 | /* | |
461 | * Whenever we re-enter userspace, the domains should always be | |
462 | * set appropriately. | |
463 | */ | |
464 | mov \tmp, #DACR_UACCESS_DISABLE | |
465 | mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register | |
466 | .if \isb | |
467 | instr_sync | |
468 | .endif | |
469 | #endif | |
2190fed6 RK |
470 | .endm |
471 | ||
472 | .macro uaccess_enable, tmp, isb=1 | |
a5e090ac RK |
473 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
474 | /* | |
475 | * Whenever we re-enter userspace, the domains should always be | |
476 | * set appropriately. | |
477 | */ | |
478 | mov \tmp, #DACR_UACCESS_ENABLE | |
479 | mcr p15, 0, \tmp, c3, c0, 0 | |
480 | .if \isb | |
481 | instr_sync | |
482 | .endif | |
483 | #endif | |
2190fed6 RK |
484 | .endm |
485 | ||
486 | .macro uaccess_save, tmp | |
a5e090ac RK |
487 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
488 | mrc p15, 0, \tmp, c3, c0, 0 | |
e6a9dc61 | 489 | str \tmp, [sp, #SVC_DACR] |
a5e090ac | 490 | #endif |
2190fed6 RK |
491 | .endm |
492 | ||
493 | .macro uaccess_restore | |
a5e090ac | 494 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
e6a9dc61 | 495 | ldr r0, [sp, #SVC_DACR] |
a5e090ac RK |
496 | mcr p15, 0, r0, c3, c0, 0 |
497 | #endif | |
2190fed6 RK |
498 | .endm |
499 | ||
6ebbf2ce RK |
500 | .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo |
501 | .macro ret\c, reg | |
502 | #if __LINUX_ARM_ARCH__ < 6 | |
503 | mov\c pc, \reg | |
504 | #else | |
505 | .ifeqs "\reg", "lr" | |
506 | bx\c \reg | |
507 | .else | |
508 | mov\c pc, \reg | |
509 | .endif | |
510 | #endif | |
511 | .endm | |
512 | .endr | |
513 | ||
514 | .macro ret.w, reg | |
515 | ret \reg | |
516 | #ifdef CONFIG_THUMB2_KERNEL | |
517 | nop | |
518 | #endif | |
519 | .endm | |
520 | ||
8bafae20 RK |
521 | .macro bug, msg, line |
522 | #ifdef CONFIG_THUMB2_KERNEL | |
523 | 1: .inst 0xde02 | |
524 | #else | |
525 | 1: .inst 0xe7f001f2 | |
526 | #endif | |
527 | #ifdef CONFIG_DEBUG_BUGVERBOSE | |
528 | .pushsection .rodata.str, "aMS", %progbits, 1 | |
529 | 2: .asciz "\msg" | |
530 | .popsection | |
531 | .pushsection __bug_table, "aw" | |
532 | .align 2 | |
533 | .word 1b, 2b | |
534 | .hword \line | |
535 | .popsection | |
536 | #endif | |
537 | .endm | |
538 | ||
2bc58a6f | 539 | #endif /* __ASM_ASSEMBLER_H__ */ |