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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
4baa9922 | 3 | * arch/arm/include/asm/cache.h |
1da177e4 LT |
4 | */ |
5 | #ifndef __ASMARM_CACHE_H | |
6 | #define __ASMARM_CACHE_H | |
7 | ||
910a17e5 | 8 | #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT |
1da177e4 LT |
9 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
10 | ||
eb5f4ca9 MF |
11 | /* |
12 | * Memory returned by kmalloc() may be used for DMA, so we must make | |
13 | * sure that all such allocations are cache aligned. Otherwise, | |
14 | * unrelated code may cause parts of the buffer to be read into the | |
15 | * cache before the transfer is done, causing old data to be seen by | |
16 | * the CPU. | |
17 | */ | |
a6eb9fe1 | 18 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
eb5f4ca9 MF |
19 | |
20 | /* | |
21 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. | |
22 | */ | |
23 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
24 | #define ARCH_SLAB_MINALIGN 8 | |
25 | #endif | |
26 | ||
daf87416 RK |
27 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
28 | ||
1da177e4 | 29 | #endif |