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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/cacheflush.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef _ASMARM_CACHEFLUSH_H | |
11 | #define _ASMARM_CACHEFLUSH_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/mm.h> |
14 | ||
1da177e4 | 15 | #include <asm/glue.h> |
b8a9b66f | 16 | #include <asm/shmparam.h> |
376e1421 | 17 | #include <asm/cachetype.h> |
33f663ff | 18 | #include <asm/outercache.h> |
b8a9b66f RK |
19 | |
20 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) | |
1da177e4 LT |
21 | |
22 | /* | |
23 | * Cache Model | |
24 | * =========== | |
25 | */ | |
26 | #undef _CACHE | |
27 | #undef MULTI_CACHE | |
28 | ||
6cc7cbef | 29 | #if defined(CONFIG_CPU_CACHE_V3) |
1da177e4 LT |
30 | # ifdef _CACHE |
31 | # define MULTI_CACHE 1 | |
32 | # else | |
33 | # define _CACHE v3 | |
34 | # endif | |
35 | #endif | |
36 | ||
6cc7cbef | 37 | #if defined(CONFIG_CPU_CACHE_V4) |
1da177e4 LT |
38 | # ifdef _CACHE |
39 | # define MULTI_CACHE 1 | |
40 | # else | |
41 | # define _CACHE v4 | |
42 | # endif | |
43 | #endif | |
44 | ||
45 | #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ | |
1c8e170a AWG |
46 | defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ |
47 | defined(CONFIG_CPU_ARM1026) | |
1da177e4 LT |
48 | # define MULTI_CACHE 1 |
49 | #endif | |
50 | ||
28853ac8 PZ |
51 | #if defined(CONFIG_CPU_FA526) |
52 | # ifdef _CACHE | |
53 | # define MULTI_CACHE 1 | |
54 | # else | |
55 | # define _CACHE fa | |
56 | # endif | |
57 | #endif | |
58 | ||
1da177e4 LT |
59 | #if defined(CONFIG_CPU_ARM926T) |
60 | # ifdef _CACHE | |
61 | # define MULTI_CACHE 1 | |
62 | # else | |
63 | # define _CACHE arm926 | |
64 | # endif | |
65 | #endif | |
66 | ||
d60674eb HC |
67 | #if defined(CONFIG_CPU_ARM940T) |
68 | # ifdef _CACHE | |
69 | # define MULTI_CACHE 1 | |
70 | # else | |
71 | # define _CACHE arm940 | |
72 | # endif | |
73 | #endif | |
74 | ||
f37f46eb HC |
75 | #if defined(CONFIG_CPU_ARM946E) |
76 | # ifdef _CACHE | |
77 | # define MULTI_CACHE 1 | |
78 | # else | |
79 | # define _CACHE arm946 | |
80 | # endif | |
81 | #endif | |
82 | ||
6cc7cbef | 83 | #if defined(CONFIG_CPU_CACHE_V4WB) |
1da177e4 LT |
84 | # ifdef _CACHE |
85 | # define MULTI_CACHE 1 | |
86 | # else | |
87 | # define _CACHE v4wb | |
88 | # endif | |
89 | #endif | |
90 | ||
91 | #if defined(CONFIG_CPU_XSCALE) | |
92 | # ifdef _CACHE | |
93 | # define MULTI_CACHE 1 | |
94 | # else | |
95 | # define _CACHE xscale | |
96 | # endif | |
97 | #endif | |
98 | ||
23bdf86a LB |
99 | #if defined(CONFIG_CPU_XSC3) |
100 | # ifdef _CACHE | |
101 | # define MULTI_CACHE 1 | |
102 | # else | |
103 | # define _CACHE xsc3 | |
104 | # endif | |
105 | #endif | |
106 | ||
49cbe786 EM |
107 | #if defined(CONFIG_CPU_MOHAWK) |
108 | # ifdef _CACHE | |
109 | # define MULTI_CACHE 1 | |
110 | # else | |
111 | # define _CACHE mohawk | |
112 | # endif | |
113 | #endif | |
114 | ||
e50d6409 | 115 | #if defined(CONFIG_CPU_FEROCEON) |
836a8051 | 116 | # define MULTI_CACHE 1 |
e50d6409 AH |
117 | #endif |
118 | ||
1da177e4 LT |
119 | #if defined(CONFIG_CPU_V6) |
120 | //# ifdef _CACHE | |
121 | # define MULTI_CACHE 1 | |
122 | //# else | |
123 | //# define _CACHE v6 | |
124 | //# endif | |
125 | #endif | |
126 | ||
bbe88886 CM |
127 | #if defined(CONFIG_CPU_V7) |
128 | //# ifdef _CACHE | |
129 | # define MULTI_CACHE 1 | |
130 | //# else | |
131 | //# define _CACHE v7 | |
132 | //# endif | |
133 | #endif | |
134 | ||
1da177e4 LT |
135 | #if !defined(_CACHE) && !defined(MULTI_CACHE) |
136 | #error Unknown cache maintainence model | |
137 | #endif | |
138 | ||
139 | /* | |
c0177800 CM |
140 | * This flag is used to indicate that the page pointed to by a pte is clean |
141 | * and does not require cleaning before returning it to the user. | |
1da177e4 | 142 | */ |
c0177800 | 143 | #define PG_dcache_clean PG_arch_1 |
1da177e4 LT |
144 | |
145 | /* | |
146 | * MM Cache Management | |
147 | * =================== | |
148 | * | |
149 | * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files | |
150 | * implement these methods. | |
151 | * | |
152 | * Start addresses are inclusive and end addresses are exclusive; | |
153 | * start addresses should be rounded down, end addresses up. | |
154 | * | |
155 | * See Documentation/cachetlb.txt for more information. | |
156 | * Please note that the implementation of these, and the required | |
157 | * effects are cache-type (VIVT/VIPT/PIPT) specific. | |
158 | * | |
81d11955 TL |
159 | * flush_icache_all() |
160 | * | |
161 | * Unconditionally clean and invalidate the entire icache. | |
162 | * Currently only needed for cache-v6.S and cache-v7.S, see | |
163 | * __flush_icache_all for the generic implementation. | |
164 | * | |
2045124f | 165 | * flush_kern_all() |
1da177e4 LT |
166 | * |
167 | * Unconditionally clean and invalidate the entire cache. | |
168 | * | |
2045124f | 169 | * flush_user_all() |
1da177e4 LT |
170 | * |
171 | * Clean and invalidate all user space cache entries | |
172 | * before a change of page tables. | |
173 | * | |
2045124f | 174 | * flush_user_range(start, end, flags) |
1da177e4 LT |
175 | * |
176 | * Clean and invalidate a range of cache entries in the | |
177 | * specified address space before a change of page tables. | |
178 | * - start - user start address (inclusive, page aligned) | |
179 | * - end - user end address (exclusive, page aligned) | |
180 | * - flags - vma->vm_flags field | |
181 | * | |
182 | * coherent_kern_range(start, end) | |
183 | * | |
184 | * Ensure coherency between the Icache and the Dcache in the | |
185 | * region described by start, end. If you have non-snooping | |
186 | * Harvard caches, you need to implement this function. | |
187 | * - start - virtual start address | |
188 | * - end - virtual end address | |
189 | * | |
2045124f TL |
190 | * coherent_user_range(start, end) |
191 | * | |
192 | * Ensure coherency between the Icache and the Dcache in the | |
193 | * region described by start, end. If you have non-snooping | |
194 | * Harvard caches, you need to implement this function. | |
195 | * - start - virtual start address | |
196 | * - end - virtual end address | |
197 | * | |
198 | * flush_kern_dcache_area(kaddr, size) | |
199 | * | |
200 | * Ensure that the data held in page is written back. | |
201 | * - kaddr - page address | |
202 | * - size - region size | |
203 | * | |
1da177e4 LT |
204 | * DMA Cache Coherency |
205 | * =================== | |
206 | * | |
1da177e4 LT |
207 | * dma_flush_range(start, end) |
208 | * | |
209 | * Clean and invalidate the specified virtual address range. | |
210 | * - start - virtual start address | |
211 | * - end - virtual end address | |
212 | */ | |
213 | ||
214 | struct cpu_cache_fns { | |
81d11955 | 215 | void (*flush_icache_all)(void); |
1da177e4 LT |
216 | void (*flush_kern_all)(void); |
217 | void (*flush_user_all)(void); | |
218 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); | |
219 | ||
220 | void (*coherent_kern_range)(unsigned long, unsigned long); | |
221 | void (*coherent_user_range)(unsigned long, unsigned long); | |
2c9b9c84 | 222 | void (*flush_kern_dcache_area)(void *, size_t); |
1da177e4 | 223 | |
a9c9147e RK |
224 | void (*dma_map_area)(const void *, size_t, int); |
225 | void (*dma_unmap_area)(const void *, size_t, int); | |
1da177e4 | 226 | |
7ae5a761 | 227 | void (*dma_flush_range)(const void *, const void *); |
1da177e4 LT |
228 | }; |
229 | ||
230 | /* | |
231 | * Select the calling method | |
232 | */ | |
233 | #ifdef MULTI_CACHE | |
234 | ||
235 | extern struct cpu_cache_fns cpu_cache; | |
236 | ||
81d11955 | 237 | #define __cpuc_flush_icache_all cpu_cache.flush_icache_all |
1da177e4 LT |
238 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all |
239 | #define __cpuc_flush_user_all cpu_cache.flush_user_all | |
240 | #define __cpuc_flush_user_range cpu_cache.flush_user_range | |
241 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range | |
242 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range | |
2c9b9c84 | 243 | #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area |
1da177e4 LT |
244 | |
245 | /* | |
246 | * These are private to the dma-mapping API. Do not use directly. | |
247 | * Their sole purpose is to ensure that data held in the cache | |
248 | * is visible to DMA, or data written by DMA to system memory is | |
249 | * visible to the CPU. | |
250 | */ | |
a9c9147e RK |
251 | #define dmac_map_area cpu_cache.dma_map_area |
252 | #define dmac_unmap_area cpu_cache.dma_unmap_area | |
1da177e4 LT |
253 | #define dmac_flush_range cpu_cache.dma_flush_range |
254 | ||
255 | #else | |
256 | ||
81d11955 | 257 | #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) |
1da177e4 LT |
258 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) |
259 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) | |
260 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) | |
261 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) | |
262 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) | |
2c9b9c84 | 263 | #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) |
1da177e4 | 264 | |
81d11955 | 265 | extern void __cpuc_flush_icache_all(void); |
1da177e4 LT |
266 | extern void __cpuc_flush_kern_all(void); |
267 | extern void __cpuc_flush_user_all(void); | |
268 | extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); | |
269 | extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); | |
270 | extern void __cpuc_coherent_user_range(unsigned long, unsigned long); | |
2c9b9c84 | 271 | extern void __cpuc_flush_dcache_area(void *, size_t); |
1da177e4 LT |
272 | |
273 | /* | |
274 | * These are private to the dma-mapping API. Do not use directly. | |
275 | * Their sole purpose is to ensure that data held in the cache | |
276 | * is visible to DMA, or data written by DMA to system memory is | |
277 | * visible to the CPU. | |
278 | */ | |
a9c9147e RK |
279 | #define dmac_map_area __glue(_CACHE,_dma_map_area) |
280 | #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) | |
1da177e4 LT |
281 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) |
282 | ||
a9c9147e RK |
283 | extern void dmac_map_area(const void *, size_t, int); |
284 | extern void dmac_unmap_area(const void *, size_t, int); | |
7ae5a761 | 285 | extern void dmac_flush_range(const void *, const void *); |
1da177e4 LT |
286 | |
287 | #endif | |
288 | ||
1da177e4 LT |
289 | /* |
290 | * Copy user data from/to a page which is mapped into a different | |
291 | * processes address space. Really, we want to allow our "user | |
292 | * space" model to handle this. | |
293 | */ | |
2ef7f3db RK |
294 | extern void copy_to_user_page(struct vm_area_struct *, struct page *, |
295 | unsigned long, void *, const void *, unsigned long); | |
1da177e4 LT |
296 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
297 | do { \ | |
1da177e4 LT |
298 | memcpy(dst, src, len); \ |
299 | } while (0) | |
300 | ||
301 | /* | |
302 | * Convert calls to our calling convention. | |
303 | */ | |
81d11955 TL |
304 | |
305 | /* Invalidate I-cache */ | |
306 | #define __flush_icache_all_generic() \ | |
307 | asm("mcr p15, 0, %0, c7, c5, 0" \ | |
308 | : : "r" (0)); | |
309 | ||
310 | /* Invalidate I-cache inner shareable */ | |
311 | #define __flush_icache_all_v7_smp() \ | |
312 | asm("mcr p15, 0, %0, c7, c1, 0" \ | |
313 | : : "r" (0)); | |
314 | ||
315 | /* | |
316 | * Optimized __flush_icache_all for the common cases. Note that UP ARMv7 | |
317 | * will fall through to use __flush_icache_all_generic. | |
318 | */ | |
319 | #if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) || \ | |
320 | defined(CONFIG_SMP_ON_UP) | |
321 | #define __flush_icache_preferred __cpuc_flush_icache_all | |
322 | #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) | |
323 | #define __flush_icache_preferred __flush_icache_all_v7_smp | |
324 | #elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920) | |
325 | #define __flush_icache_preferred __cpuc_flush_icache_all | |
326 | #else | |
327 | #define __flush_icache_preferred __flush_icache_all_generic | |
328 | #endif | |
329 | ||
330 | static inline void __flush_icache_all(void) | |
331 | { | |
332 | __flush_icache_preferred(); | |
333 | } | |
334 | ||
1da177e4 | 335 | #define flush_cache_all() __cpuc_flush_kern_all() |
2f0b1926 RK |
336 | |
337 | static inline void vivt_flush_cache_mm(struct mm_struct *mm) | |
1da177e4 | 338 | { |
56f8ba83 | 339 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) |
1da177e4 LT |
340 | __cpuc_flush_user_all(); |
341 | } | |
342 | ||
343 | static inline void | |
2f0b1926 | 344 | vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
1da177e4 | 345 | { |
56f8ba83 | 346 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) |
1da177e4 LT |
347 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), |
348 | vma->vm_flags); | |
349 | } | |
350 | ||
351 | static inline void | |
2f0b1926 | 352 | vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
1da177e4 | 353 | { |
56f8ba83 | 354 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
1da177e4 LT |
355 | unsigned long addr = user_addr & PAGE_MASK; |
356 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); | |
357 | } | |
358 | } | |
a188ad2b | 359 | |
2f0b1926 RK |
360 | #ifndef CONFIG_CPU_CACHE_VIPT |
361 | #define flush_cache_mm(mm) \ | |
362 | vivt_flush_cache_mm(mm) | |
363 | #define flush_cache_range(vma,start,end) \ | |
364 | vivt_flush_cache_range(vma,start,end) | |
365 | #define flush_cache_page(vma,addr,pfn) \ | |
366 | vivt_flush_cache_page(vma,addr,pfn) | |
d7b6b358 RK |
367 | #else |
368 | extern void flush_cache_mm(struct mm_struct *mm); | |
369 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
370 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); | |
371 | #endif | |
1da177e4 | 372 | |
ec8c0446 RB |
373 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
374 | ||
1da177e4 LT |
375 | /* |
376 | * flush_cache_user_range is used when we want to ensure that the | |
377 | * Harvard caches are synchronised for the user space address range. | |
378 | * This is used for the ARM private sys_cacheflush system call. | |
379 | */ | |
380 | #define flush_cache_user_range(vma,start,end) \ | |
381 | __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) | |
382 | ||
383 | /* | |
384 | * Perform necessary cache operations to ensure that data previously | |
385 | * stored within this range of addresses can be executed by the CPU. | |
386 | */ | |
387 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) | |
388 | ||
389 | /* | |
390 | * Perform necessary cache operations to ensure that the TLB will | |
391 | * see data written in the specified area. | |
392 | */ | |
393 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) | |
394 | ||
395 | /* | |
396 | * flush_dcache_page is used when the kernel has written to the page | |
397 | * cache page at virtual address page->virtual. | |
398 | * | |
399 | * If this page isn't mapped (ie, page_mapping == NULL), or it might | |
400 | * have userspace mappings, then we _must_ always clean + invalidate | |
401 | * the dcache entries associated with the kernel mapping. | |
402 | * | |
403 | * Otherwise we can defer the operation, and clean the cache when we are | |
404 | * about to change to user space. This is the same method as used on SPARC64. | |
405 | * See update_mmu_cache for the user space part. | |
406 | */ | |
2d4dc890 | 407 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
1da177e4 LT |
408 | extern void flush_dcache_page(struct page *); |
409 | ||
252a9aff JB |
410 | static inline void flush_kernel_vmap_range(void *addr, int size) |
411 | { | |
412 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) | |
413 | __cpuc_flush_dcache_area(addr, (size_t)size); | |
414 | } | |
415 | static inline void invalidate_kernel_vmap_range(void *addr, int size) | |
416 | { | |
417 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) | |
418 | __cpuc_flush_dcache_area(addr, (size_t)size); | |
419 | } | |
826cbdaf | 420 | |
6020dff0 RK |
421 | #define ARCH_HAS_FLUSH_ANON_PAGE |
422 | static inline void flush_anon_page(struct vm_area_struct *vma, | |
423 | struct page *page, unsigned long vmaddr) | |
424 | { | |
425 | extern void __flush_anon_page(struct vm_area_struct *vma, | |
426 | struct page *, unsigned long); | |
427 | if (PageAnon(page)) | |
428 | __flush_anon_page(vma, page, vmaddr); | |
429 | } | |
430 | ||
73be1591 NP |
431 | #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE |
432 | static inline void flush_kernel_dcache_page(struct page *page) | |
433 | { | |
73be1591 NP |
434 | } |
435 | ||
1da177e4 | 436 | #define flush_dcache_mmap_lock(mapping) \ |
19fd6231 | 437 | spin_lock_irq(&(mapping)->tree_lock) |
1da177e4 | 438 | #define flush_dcache_mmap_unlock(mapping) \ |
19fd6231 | 439 | spin_unlock_irq(&(mapping)->tree_lock) |
1da177e4 LT |
440 | |
441 | #define flush_icache_user_range(vma,page,addr,len) \ | |
442 | flush_dcache_page(page) | |
443 | ||
444 | /* | |
445 | * We don't appear to need to do anything here. In fact, if we did, we'd | |
446 | * duplicate cache flushing elsewhere performed by flush_dcache_page(). | |
447 | */ | |
448 | #define flush_icache_page(vma,page) do { } while (0) | |
449 | ||
376e1421 CM |
450 | /* |
451 | * flush_cache_vmap() is used when creating mappings (eg, via vmap, | |
452 | * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT | |
453 | * caches, since the direct-mappings of these pages may contain cached | |
454 | * data, we need to do a full cache flush to ensure that writebacks | |
455 | * don't corrupt data placed into these pages via the new mappings. | |
456 | */ | |
457 | static inline void flush_cache_vmap(unsigned long start, unsigned long end) | |
458 | { | |
459 | if (!cache_is_vipt_nonaliasing()) | |
460 | flush_cache_all(); | |
461 | else | |
462 | /* | |
463 | * set_pte_at() called from vmap_pte_range() does not | |
464 | * have a DSB after cleaning the cache line. | |
465 | */ | |
466 | dsb(); | |
467 | } | |
468 | ||
469 | static inline void flush_cache_vunmap(unsigned long start, unsigned long end) | |
470 | { | |
471 | if (!cache_is_vipt_nonaliasing()) | |
472 | flush_cache_all(); | |
473 | } | |
474 | ||
1da177e4 | 475 | #endif |