]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/cacheflush.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef _ASMARM_CACHEFLUSH_H | |
11 | #define _ASMARM_CACHEFLUSH_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/mm.h> |
14 | ||
753790e7 | 15 | #include <asm/glue-cache.h> |
b8a9b66f | 16 | #include <asm/shmparam.h> |
376e1421 | 17 | #include <asm/cachetype.h> |
33f663ff | 18 | #include <asm/outercache.h> |
b8a9b66f RK |
19 | |
20 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) | |
1da177e4 | 21 | |
1da177e4 | 22 | /* |
c0177800 CM |
23 | * This flag is used to indicate that the page pointed to by a pte is clean |
24 | * and does not require cleaning before returning it to the user. | |
1da177e4 | 25 | */ |
c0177800 | 26 | #define PG_dcache_clean PG_arch_1 |
1da177e4 LT |
27 | |
28 | /* | |
29 | * MM Cache Management | |
30 | * =================== | |
31 | * | |
32 | * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files | |
33 | * implement these methods. | |
34 | * | |
35 | * Start addresses are inclusive and end addresses are exclusive; | |
36 | * start addresses should be rounded down, end addresses up. | |
37 | * | |
38 | * See Documentation/cachetlb.txt for more information. | |
39 | * Please note that the implementation of these, and the required | |
40 | * effects are cache-type (VIVT/VIPT/PIPT) specific. | |
41 | * | |
81d11955 TL |
42 | * flush_icache_all() |
43 | * | |
44 | * Unconditionally clean and invalidate the entire icache. | |
45 | * Currently only needed for cache-v6.S and cache-v7.S, see | |
46 | * __flush_icache_all for the generic implementation. | |
47 | * | |
2045124f | 48 | * flush_kern_all() |
1da177e4 LT |
49 | * |
50 | * Unconditionally clean and invalidate the entire cache. | |
51 | * | |
031bd879 LP |
52 | * flush_kern_louis() |
53 | * | |
54 | * Flush data cache levels up to the level of unification | |
55 | * inner shareable and invalidate the I-cache. | |
56 | * Only needed from v7 onwards, falls back to flush_cache_all() | |
57 | * for all other processor versions. | |
58 | * | |
2045124f | 59 | * flush_user_all() |
1da177e4 LT |
60 | * |
61 | * Clean and invalidate all user space cache entries | |
62 | * before a change of page tables. | |
63 | * | |
2045124f | 64 | * flush_user_range(start, end, flags) |
1da177e4 LT |
65 | * |
66 | * Clean and invalidate a range of cache entries in the | |
67 | * specified address space before a change of page tables. | |
68 | * - start - user start address (inclusive, page aligned) | |
69 | * - end - user end address (exclusive, page aligned) | |
70 | * - flags - vma->vm_flags field | |
71 | * | |
72 | * coherent_kern_range(start, end) | |
73 | * | |
74 | * Ensure coherency between the Icache and the Dcache in the | |
75 | * region described by start, end. If you have non-snooping | |
76 | * Harvard caches, you need to implement this function. | |
77 | * - start - virtual start address | |
78 | * - end - virtual end address | |
79 | * | |
2045124f TL |
80 | * coherent_user_range(start, end) |
81 | * | |
82 | * Ensure coherency between the Icache and the Dcache in the | |
83 | * region described by start, end. If you have non-snooping | |
84 | * Harvard caches, you need to implement this function. | |
85 | * - start - virtual start address | |
86 | * - end - virtual end address | |
87 | * | |
88 | * flush_kern_dcache_area(kaddr, size) | |
89 | * | |
90 | * Ensure that the data held in page is written back. | |
91 | * - kaddr - page address | |
92 | * - size - region size | |
93 | * | |
1da177e4 LT |
94 | * DMA Cache Coherency |
95 | * =================== | |
96 | * | |
1da177e4 LT |
97 | * dma_flush_range(start, end) |
98 | * | |
99 | * Clean and invalidate the specified virtual address range. | |
100 | * - start - virtual start address | |
101 | * - end - virtual end address | |
102 | */ | |
103 | ||
104 | struct cpu_cache_fns { | |
81d11955 | 105 | void (*flush_icache_all)(void); |
1da177e4 | 106 | void (*flush_kern_all)(void); |
031bd879 | 107 | void (*flush_kern_louis)(void); |
1da177e4 LT |
108 | void (*flush_user_all)(void); |
109 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); | |
110 | ||
111 | void (*coherent_kern_range)(unsigned long, unsigned long); | |
c5102f59 | 112 | int (*coherent_user_range)(unsigned long, unsigned long); |
2c9b9c84 | 113 | void (*flush_kern_dcache_area)(void *, size_t); |
1da177e4 | 114 | |
a9c9147e RK |
115 | void (*dma_map_area)(const void *, size_t, int); |
116 | void (*dma_unmap_area)(const void *, size_t, int); | |
1da177e4 | 117 | |
7ae5a761 | 118 | void (*dma_flush_range)(const void *, const void *); |
8acdf505 | 119 | } __no_randomize_layout; |
1da177e4 LT |
120 | |
121 | /* | |
122 | * Select the calling method | |
123 | */ | |
124 | #ifdef MULTI_CACHE | |
125 | ||
126 | extern struct cpu_cache_fns cpu_cache; | |
127 | ||
81d11955 | 128 | #define __cpuc_flush_icache_all cpu_cache.flush_icache_all |
1da177e4 | 129 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all |
031bd879 | 130 | #define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis |
1da177e4 LT |
131 | #define __cpuc_flush_user_all cpu_cache.flush_user_all |
132 | #define __cpuc_flush_user_range cpu_cache.flush_user_range | |
133 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range | |
134 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range | |
2c9b9c84 | 135 | #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area |
1da177e4 LT |
136 | |
137 | /* | |
138 | * These are private to the dma-mapping API. Do not use directly. | |
139 | * Their sole purpose is to ensure that data held in the cache | |
140 | * is visible to DMA, or data written by DMA to system memory is | |
141 | * visible to the CPU. | |
142 | */ | |
1da177e4 LT |
143 | #define dmac_flush_range cpu_cache.dma_flush_range |
144 | ||
145 | #else | |
146 | ||
81d11955 | 147 | extern void __cpuc_flush_icache_all(void); |
1da177e4 | 148 | extern void __cpuc_flush_kern_all(void); |
031bd879 | 149 | extern void __cpuc_flush_kern_louis(void); |
1da177e4 LT |
150 | extern void __cpuc_flush_user_all(void); |
151 | extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); | |
152 | extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); | |
c5102f59 | 153 | extern int __cpuc_coherent_user_range(unsigned long, unsigned long); |
2c9b9c84 | 154 | extern void __cpuc_flush_dcache_area(void *, size_t); |
1da177e4 LT |
155 | |
156 | /* | |
157 | * These are private to the dma-mapping API. Do not use directly. | |
158 | * Their sole purpose is to ensure that data held in the cache | |
159 | * is visible to DMA, or data written by DMA to system memory is | |
160 | * visible to the CPU. | |
161 | */ | |
7ae5a761 | 162 | extern void dmac_flush_range(const void *, const void *); |
1da177e4 LT |
163 | |
164 | #endif | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Copy user data from/to a page which is mapped into a different | |
168 | * processes address space. Really, we want to allow our "user | |
169 | * space" model to handle this. | |
170 | */ | |
2ef7f3db RK |
171 | extern void copy_to_user_page(struct vm_area_struct *, struct page *, |
172 | unsigned long, void *, const void *, unsigned long); | |
1da177e4 LT |
173 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
174 | do { \ | |
1da177e4 LT |
175 | memcpy(dst, src, len); \ |
176 | } while (0) | |
177 | ||
178 | /* | |
179 | * Convert calls to our calling convention. | |
180 | */ | |
81d11955 TL |
181 | |
182 | /* Invalidate I-cache */ | |
183 | #define __flush_icache_all_generic() \ | |
184 | asm("mcr p15, 0, %0, c7, c5, 0" \ | |
185 | : : "r" (0)); | |
186 | ||
187 | /* Invalidate I-cache inner shareable */ | |
188 | #define __flush_icache_all_v7_smp() \ | |
189 | asm("mcr p15, 0, %0, c7, c1, 0" \ | |
190 | : : "r" (0)); | |
191 | ||
192 | /* | |
193 | * Optimized __flush_icache_all for the common cases. Note that UP ARMv7 | |
194 | * will fall through to use __flush_icache_all_generic. | |
195 | */ | |
e399b1a4 RK |
196 | #if (defined(CONFIG_CPU_V7) && \ |
197 | (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \ | |
81d11955 TL |
198 | defined(CONFIG_SMP_ON_UP) |
199 | #define __flush_icache_preferred __cpuc_flush_icache_all | |
200 | #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) | |
201 | #define __flush_icache_preferred __flush_icache_all_v7_smp | |
202 | #elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920) | |
203 | #define __flush_icache_preferred __cpuc_flush_icache_all | |
204 | #else | |
205 | #define __flush_icache_preferred __flush_icache_all_generic | |
206 | #endif | |
207 | ||
208 | static inline void __flush_icache_all(void) | |
209 | { | |
210 | __flush_icache_preferred(); | |
9581960a | 211 | dsb(ishst); |
81d11955 TL |
212 | } |
213 | ||
031bd879 LP |
214 | /* |
215 | * Flush caches up to Level of Unification Inner Shareable | |
216 | */ | |
217 | #define flush_cache_louis() __cpuc_flush_kern_louis() | |
218 | ||
1da177e4 | 219 | #define flush_cache_all() __cpuc_flush_kern_all() |
2f0b1926 RK |
220 | |
221 | static inline void vivt_flush_cache_mm(struct mm_struct *mm) | |
1da177e4 | 222 | { |
56f8ba83 | 223 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) |
1da177e4 LT |
224 | __cpuc_flush_user_all(); |
225 | } | |
226 | ||
227 | static inline void | |
2f0b1926 | 228 | vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
1da177e4 | 229 | { |
b74253f7 WD |
230 | struct mm_struct *mm = vma->vm_mm; |
231 | ||
232 | if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) | |
1da177e4 LT |
233 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), |
234 | vma->vm_flags); | |
235 | } | |
236 | ||
237 | static inline void | |
2f0b1926 | 238 | vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
1da177e4 | 239 | { |
b74253f7 WD |
240 | struct mm_struct *mm = vma->vm_mm; |
241 | ||
242 | if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) { | |
1da177e4 LT |
243 | unsigned long addr = user_addr & PAGE_MASK; |
244 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); | |
245 | } | |
246 | } | |
a188ad2b | 247 | |
2f0b1926 RK |
248 | #ifndef CONFIG_CPU_CACHE_VIPT |
249 | #define flush_cache_mm(mm) \ | |
250 | vivt_flush_cache_mm(mm) | |
251 | #define flush_cache_range(vma,start,end) \ | |
252 | vivt_flush_cache_range(vma,start,end) | |
253 | #define flush_cache_page(vma,addr,pfn) \ | |
254 | vivt_flush_cache_page(vma,addr,pfn) | |
d7b6b358 RK |
255 | #else |
256 | extern void flush_cache_mm(struct mm_struct *mm); | |
257 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
258 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); | |
259 | #endif | |
1da177e4 | 260 | |
ec8c0446 RB |
261 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
262 | ||
1da177e4 LT |
263 | /* |
264 | * flush_cache_user_range is used when we want to ensure that the | |
265 | * Harvard caches are synchronised for the user space address range. | |
266 | * This is used for the ARM private sys_cacheflush system call. | |
267 | */ | |
d9524dc3 | 268 | #define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e) |
1da177e4 LT |
269 | |
270 | /* | |
271 | * Perform necessary cache operations to ensure that data previously | |
272 | * stored within this range of addresses can be executed by the CPU. | |
273 | */ | |
274 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) | |
275 | ||
276 | /* | |
277 | * Perform necessary cache operations to ensure that the TLB will | |
278 | * see data written in the specified area. | |
279 | */ | |
280 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) | |
281 | ||
282 | /* | |
283 | * flush_dcache_page is used when the kernel has written to the page | |
284 | * cache page at virtual address page->virtual. | |
285 | * | |
286 | * If this page isn't mapped (ie, page_mapping == NULL), or it might | |
287 | * have userspace mappings, then we _must_ always clean + invalidate | |
288 | * the dcache entries associated with the kernel mapping. | |
289 | * | |
290 | * Otherwise we can defer the operation, and clean the cache when we are | |
291 | * about to change to user space. This is the same method as used on SPARC64. | |
292 | * See update_mmu_cache for the user space part. | |
293 | */ | |
2d4dc890 | 294 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
1da177e4 LT |
295 | extern void flush_dcache_page(struct page *); |
296 | ||
252a9aff JB |
297 | static inline void flush_kernel_vmap_range(void *addr, int size) |
298 | { | |
299 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) | |
300 | __cpuc_flush_dcache_area(addr, (size_t)size); | |
301 | } | |
302 | static inline void invalidate_kernel_vmap_range(void *addr, int size) | |
303 | { | |
304 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) | |
305 | __cpuc_flush_dcache_area(addr, (size_t)size); | |
306 | } | |
826cbdaf | 307 | |
6020dff0 RK |
308 | #define ARCH_HAS_FLUSH_ANON_PAGE |
309 | static inline void flush_anon_page(struct vm_area_struct *vma, | |
310 | struct page *page, unsigned long vmaddr) | |
311 | { | |
312 | extern void __flush_anon_page(struct vm_area_struct *vma, | |
313 | struct page *, unsigned long); | |
314 | if (PageAnon(page)) | |
315 | __flush_anon_page(vma, page, vmaddr); | |
316 | } | |
317 | ||
73be1591 | 318 | #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE |
1bc39742 | 319 | extern void flush_kernel_dcache_page(struct page *); |
73be1591 | 320 | |
1da177e4 | 321 | #define flush_dcache_mmap_lock(mapping) \ |
19fd6231 | 322 | spin_lock_irq(&(mapping)->tree_lock) |
1da177e4 | 323 | #define flush_dcache_mmap_unlock(mapping) \ |
19fd6231 | 324 | spin_unlock_irq(&(mapping)->tree_lock) |
1da177e4 LT |
325 | |
326 | #define flush_icache_user_range(vma,page,addr,len) \ | |
327 | flush_dcache_page(page) | |
328 | ||
329 | /* | |
330 | * We don't appear to need to do anything here. In fact, if we did, we'd | |
331 | * duplicate cache flushing elsewhere performed by flush_dcache_page(). | |
332 | */ | |
333 | #define flush_icache_page(vma,page) do { } while (0) | |
334 | ||
376e1421 CM |
335 | /* |
336 | * flush_cache_vmap() is used when creating mappings (eg, via vmap, | |
337 | * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT | |
338 | * caches, since the direct-mappings of these pages may contain cached | |
339 | * data, we need to do a full cache flush to ensure that writebacks | |
340 | * don't corrupt data placed into these pages via the new mappings. | |
341 | */ | |
342 | static inline void flush_cache_vmap(unsigned long start, unsigned long end) | |
343 | { | |
344 | if (!cache_is_vipt_nonaliasing()) | |
345 | flush_cache_all(); | |
346 | else | |
347 | /* | |
348 | * set_pte_at() called from vmap_pte_range() does not | |
349 | * have a DSB after cleaning the cache line. | |
350 | */ | |
6af396a6 | 351 | dsb(ishst); |
376e1421 CM |
352 | } |
353 | ||
354 | static inline void flush_cache_vunmap(unsigned long start, unsigned long end) | |
355 | { | |
356 | if (!cache_is_vipt_nonaliasing()) | |
357 | flush_cache_all(); | |
358 | } | |
359 | ||
0c91e7e0 NP |
360 | /* |
361 | * Memory synchronization helpers for mixed cached vs non cached accesses. | |
362 | * | |
363 | * Some synchronization algorithms have to set states in memory with the | |
364 | * cache enabled or disabled depending on the code path. It is crucial | |
365 | * to always ensure proper cache maintenance to update main memory right | |
366 | * away in that case. | |
367 | * | |
368 | * Any cached write must be followed by a cache clean operation. | |
369 | * Any cached read must be preceded by a cache invalidate operation. | |
370 | * Yet, in the read case, a cache flush i.e. atomic clean+invalidate | |
371 | * operation is needed to avoid discarding possible concurrent writes to the | |
372 | * accessed memory. | |
373 | * | |
374 | * Also, in order to prevent a cached writer from interfering with an | |
375 | * adjacent non-cached writer, each state variable must be located to | |
376 | * a separate cache line. | |
377 | */ | |
378 | ||
379 | /* | |
380 | * This needs to be >= the max cache writeback size of all | |
381 | * supported platforms included in the current kernel configuration. | |
382 | * This is used to align state variables to their own cache lines. | |
383 | */ | |
384 | #define __CACHE_WRITEBACK_ORDER 6 /* guessed from existing platforms */ | |
385 | #define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER) | |
386 | ||
387 | /* | |
388 | * There is no __cpuc_clean_dcache_area but we use it anyway for | |
389 | * code intent clarity, and alias it to __cpuc_flush_dcache_area. | |
390 | */ | |
391 | #define __cpuc_clean_dcache_area __cpuc_flush_dcache_area | |
392 | ||
393 | /* | |
394 | * Ensure preceding writes to *p by this CPU are visible to | |
395 | * subsequent reads by other CPUs: | |
396 | */ | |
397 | static inline void __sync_cache_range_w(volatile void *p, size_t size) | |
398 | { | |
399 | char *_p = (char *)p; | |
400 | ||
401 | __cpuc_clean_dcache_area(_p, size); | |
402 | outer_clean_range(__pa(_p), __pa(_p + size)); | |
403 | } | |
404 | ||
405 | /* | |
406 | * Ensure preceding writes to *p by other CPUs are visible to | |
407 | * subsequent reads by this CPU. We must be careful not to | |
408 | * discard data simultaneously written by another CPU, hence the | |
409 | * usage of flush rather than invalidate operations. | |
410 | */ | |
411 | static inline void __sync_cache_range_r(volatile void *p, size_t size) | |
412 | { | |
413 | char *_p = (char *)p; | |
414 | ||
415 | #ifdef CONFIG_OUTER_CACHE | |
416 | if (outer_cache.flush_range) { | |
417 | /* | |
418 | * Ensure dirty data migrated from other CPUs into our cache | |
419 | * are cleaned out safely before the outer cache is cleaned: | |
420 | */ | |
421 | __cpuc_clean_dcache_area(_p, size); | |
422 | ||
423 | /* Clean and invalidate stale data for *p from outer ... */ | |
424 | outer_flush_range(__pa(_p), __pa(_p + size)); | |
425 | } | |
426 | #endif | |
427 | ||
428 | /* ... and inner cache: */ | |
429 | __cpuc_flush_dcache_area(_p, size); | |
430 | } | |
431 | ||
432 | #define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr)) | |
433 | #define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr)) | |
434 | ||
39792c7c NP |
435 | /* |
436 | * Disabling cache access for one CPU in an ARMv7 SMP system is tricky. | |
437 | * To do so we must: | |
438 | * | |
439 | * - Clear the SCTLR.C bit to prevent further cache allocations | |
440 | * - Flush the desired level of cache | |
441 | * - Clear the ACTLR "SMP" bit to disable local coherency | |
442 | * | |
443 | * ... and so without any intervening memory access in between those steps, | |
444 | * not even to the stack. | |
445 | * | |
446 | * WARNING -- After this has been called: | |
447 | * | |
448 | * - No ldrex/strex (and similar) instructions must be used. | |
449 | * - The CPU is obviously no longer coherent with the other CPUs. | |
450 | * - This is unlikely to work as expected if Linux is running non-secure. | |
451 | * | |
452 | * Note: | |
453 | * | |
454 | * - This is known to apply to several ARMv7 processor implementations, | |
455 | * however some exceptions may exist. Caveat emptor. | |
456 | * | |
457 | * - The clobber list is dictated by the call to v7_flush_dcache_*. | |
458 | * fp is preserved to the stack explicitly prior disabling the cache | |
459 | * since adding it to the clobber list is incompatible with having | |
460 | * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering | |
461 | * trampoline are inserted by the linker and to keep sp 64-bit aligned. | |
462 | */ | |
463 | #define v7_exit_coherency_flush(level) \ | |
464 | asm volatile( \ | |
ebc77251 | 465 | ".arch armv7-a \n\t" \ |
39792c7c NP |
466 | "stmfd sp!, {fp, ip} \n\t" \ |
467 | "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ | |
468 | "bic r0, r0, #"__stringify(CR_C)" \n\t" \ | |
469 | "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ | |
470 | "isb \n\t" \ | |
471 | "bl v7_flush_dcache_"__stringify(level)" \n\t" \ | |
39792c7c NP |
472 | "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \ |
473 | "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ | |
474 | "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \ | |
475 | "isb \n\t" \ | |
476 | "dsb \n\t" \ | |
477 | "ldmfd sp!, {fp, ip}" \ | |
478 | : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ | |
479 | "r9","r10","lr","memory" ) | |
480 | ||
72e6ae28 VK |
481 | void flush_uprobe_xol_access(struct page *page, unsigned long uaddr, |
482 | void *kaddr, unsigned long len); | |
80d6b0c2 | 483 | |
1da177e4 | 484 | #endif |