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0ba8b9b2 RK |
1 | #ifndef __ASM_ARM_CPUTYPE_H |
2 | #define __ASM_ARM_CPUTYPE_H | |
3 | ||
4 | #include <linux/stringify.h> | |
e9569c15 | 5 | #include <linux/kernel.h> |
0ba8b9b2 RK |
6 | |
7 | #define CPUID_ID 0 | |
8 | #define CPUID_CACHETYPE 1 | |
9 | #define CPUID_TCM 2 | |
10 | #define CPUID_TLBTYPE 3 | |
aca7e592 | 11 | #define CPUID_MPUIR 4 |
c9018aab | 12 | #define CPUID_MPIDR 5 |
92871b94 | 13 | #define CPUID_REVIDR 6 |
0ba8b9b2 | 14 | |
6fae9cda UKK |
15 | #ifdef CONFIG_CPU_V7M |
16 | #define CPUID_EXT_PFR0 0x40 | |
17 | #define CPUID_EXT_PFR1 0x44 | |
18 | #define CPUID_EXT_DFR0 0x48 | |
19 | #define CPUID_EXT_AFR0 0x4c | |
20 | #define CPUID_EXT_MMFR0 0x50 | |
21 | #define CPUID_EXT_MMFR1 0x54 | |
22 | #define CPUID_EXT_MMFR2 0x58 | |
23 | #define CPUID_EXT_MMFR3 0x5c | |
24 | #define CPUID_EXT_ISAR0 0x60 | |
25 | #define CPUID_EXT_ISAR1 0x64 | |
26 | #define CPUID_EXT_ISAR2 0x68 | |
27 | #define CPUID_EXT_ISAR3 0x6c | |
28 | #define CPUID_EXT_ISAR4 0x70 | |
29 | #define CPUID_EXT_ISAR5 0x74 | |
30 | #else | |
faa7bc51 CM |
31 | #define CPUID_EXT_PFR0 "c1, 0" |
32 | #define CPUID_EXT_PFR1 "c1, 1" | |
33 | #define CPUID_EXT_DFR0 "c1, 2" | |
34 | #define CPUID_EXT_AFR0 "c1, 3" | |
35 | #define CPUID_EXT_MMFR0 "c1, 4" | |
36 | #define CPUID_EXT_MMFR1 "c1, 5" | |
37 | #define CPUID_EXT_MMFR2 "c1, 6" | |
38 | #define CPUID_EXT_MMFR3 "c1, 7" | |
39 | #define CPUID_EXT_ISAR0 "c2, 0" | |
40 | #define CPUID_EXT_ISAR1 "c2, 1" | |
41 | #define CPUID_EXT_ISAR2 "c2, 2" | |
42 | #define CPUID_EXT_ISAR3 "c2, 3" | |
43 | #define CPUID_EXT_ISAR4 "c2, 4" | |
44 | #define CPUID_EXT_ISAR5 "c2, 5" | |
6fae9cda | 45 | #endif |
faa7bc51 | 46 | |
dca463da LP |
47 | #define MPIDR_SMP_BITMASK (0x3 << 30) |
48 | #define MPIDR_SMP_VALUE (0x2 << 30) | |
49 | ||
50 | #define MPIDR_MT_BITMASK (0x1 << 24) | |
51 | ||
52 | #define MPIDR_HWID_BITMASK 0xFFFFFF | |
53 | ||
18d7f152 LP |
54 | #define MPIDR_INVALID (~MPIDR_HWID_BITMASK) |
55 | ||
dca463da LP |
56 | #define MPIDR_LEVEL_BITS 8 |
57 | #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) | |
163352eb | 58 | #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) |
dca463da LP |
59 | |
60 | #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ | |
61 | ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) | |
62 | ||
73a09d21 | 63 | #define ARM_CPU_IMP_ARM 0x41 |
83809b90 | 64 | #define ARM_CPU_IMP_DEC 0x44 |
73a09d21 RK |
65 | #define ARM_CPU_IMP_INTEL 0x69 |
66 | ||
af040ffc RK |
67 | /* ARM implemented processors */ |
68 | #define ARM_CPU_PART_ARM1136 0x4100b360 | |
69 | #define ARM_CPU_PART_ARM1156 0x4100b560 | |
70 | #define ARM_CPU_PART_ARM1176 0x4100b760 | |
71 | #define ARM_CPU_PART_ARM11MPCORE 0x4100b020 | |
72 | #define ARM_CPU_PART_CORTEX_A8 0x4100c080 | |
73 | #define ARM_CPU_PART_CORTEX_A9 0x4100c090 | |
74 | #define ARM_CPU_PART_CORTEX_A5 0x4100c050 | |
75 | #define ARM_CPU_PART_CORTEX_A7 0x4100c070 | |
76 | #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 | |
77 | #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 | |
78 | #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 | |
eba1c718 | 79 | #define ARM_CPU_PART_MASK 0xff00fff0 |
73a09d21 | 80 | |
83809b90 RK |
81 | /* DEC implemented cores */ |
82 | #define ARM_CPU_PART_SA1100 0x4400a110 | |
83 | ||
84 | /* Intel implemented cores */ | |
85 | #define ARM_CPU_PART_SA1110 0x6900b110 | |
86 | #define ARM_CPU_REV_SA1110_A0 0 | |
87 | #define ARM_CPU_REV_SA1110_B0 4 | |
88 | #define ARM_CPU_REV_SA1110_B1 5 | |
89 | #define ARM_CPU_REV_SA1110_B2 6 | |
90 | #define ARM_CPU_REV_SA1110_B4 8 | |
91 | ||
73a09d21 RK |
92 | #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 |
93 | #define ARM_CPU_XSCALE_ARCH_V1 0x2000 | |
94 | #define ARM_CPU_XSCALE_ARCH_V2 0x4000 | |
95 | #define ARM_CPU_XSCALE_ARCH_V3 0x6000 | |
96 | ||
ddc37832 MR |
97 | /* Qualcomm implemented cores */ |
98 | #define ARM_CPU_PART_SCORPION 0x510002d0 | |
99 | ||
2bbd7e9b RK |
100 | extern unsigned int processor_id; |
101 | ||
0ba8b9b2 RK |
102 | #ifdef CONFIG_CPU_CP15 |
103 | #define read_cpuid(reg) \ | |
104 | ({ \ | |
105 | unsigned int __val; \ | |
106 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ | |
107 | : "=r" (__val) \ | |
108 | : \ | |
109 | : "cc"); \ | |
110 | __val; \ | |
111 | }) | |
6ebd4d03 | 112 | |
067e710b PW |
113 | /* |
114 | * The memory clobber prevents gcc 4.5 from reordering the mrc before | |
115 | * any is_smp() tests, which can cause undefined instruction aborts on | |
116 | * ARM1136 r0 due to the missing extended CP15 registers. | |
117 | */ | |
faa7bc51 CM |
118 | #define read_cpuid_ext(ext_reg) \ |
119 | ({ \ | |
120 | unsigned int __val; \ | |
121 | asm("mrc p15, 0, %0, c0, " ext_reg \ | |
122 | : "=r" (__val) \ | |
123 | : \ | |
067e710b | 124 | : "memory"); \ |
faa7bc51 CM |
125 | __val; \ |
126 | }) | |
0ba8b9b2 | 127 | |
6fae9cda UKK |
128 | #elif defined(CONFIG_CPU_V7M) |
129 | ||
130 | #include <asm/io.h> | |
131 | #include <asm/v7m.h> | |
132 | ||
133 | #define read_cpuid(reg) \ | |
134 | ({ \ | |
135 | WARN_ON_ONCE(1); \ | |
136 | 0; \ | |
137 | }) | |
138 | ||
139 | static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) | |
140 | { | |
141 | return readl(BASEADDR_V7M_SCB + offset); | |
142 | } | |
143 | ||
144 | #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */ | |
59530adc | 145 | |
6ebd4d03 UKK |
146 | /* |
147 | * read_cpuid and read_cpuid_ext should only ever be called on machines that | |
148 | * have cp15 so warn on other usages. | |
149 | */ | |
150 | #define read_cpuid(reg) \ | |
151 | ({ \ | |
152 | WARN_ON_ONCE(1); \ | |
153 | 0; \ | |
154 | }) | |
59530adc | 155 | |
6ebd4d03 | 156 | #define read_cpuid_ext(reg) read_cpuid(reg) |
59530adc | 157 | |
6ebd4d03 UKK |
158 | #endif /* ifdef CONFIG_CPU_CP15 / else */ |
159 | ||
160 | #ifdef CONFIG_CPU_CP15 | |
0ba8b9b2 RK |
161 | /* |
162 | * The CPU ID never changes at run time, so we might as well tell the | |
163 | * compiler that it's constant. Use this function to read the CPU ID | |
164 | * rather than directly reading processor_id or read_cpuid() directly. | |
165 | */ | |
166 | static inline unsigned int __attribute_const__ read_cpuid_id(void) | |
167 | { | |
168 | return read_cpuid(CPUID_ID); | |
169 | } | |
170 | ||
f5a5c89e JA |
171 | static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) |
172 | { | |
173 | return read_cpuid(CPUID_CACHETYPE); | |
174 | } | |
175 | ||
55bdd694 CM |
176 | #elif defined(CONFIG_CPU_V7M) |
177 | ||
55bdd694 CM |
178 | static inline unsigned int __attribute_const__ read_cpuid_id(void) |
179 | { | |
180 | return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); | |
181 | } | |
182 | ||
f5a5c89e JA |
183 | static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) |
184 | { | |
185 | return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); | |
186 | } | |
187 | ||
55bdd694 | 188 | #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ |
6ebd4d03 UKK |
189 | |
190 | static inline unsigned int __attribute_const__ read_cpuid_id(void) | |
191 | { | |
192 | return processor_id; | |
193 | } | |
194 | ||
195 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
196 | ||
59530adc CD |
197 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) |
198 | { | |
199 | return (read_cpuid_id() & 0xFF000000) >> 24; | |
200 | } | |
201 | ||
83809b90 RK |
202 | static inline unsigned int __attribute_const__ read_cpuid_revision(void) |
203 | { | |
204 | return read_cpuid_id() & 0x0000000f; | |
205 | } | |
206 | ||
af040ffc RK |
207 | /* |
208 | * The CPU part number is meaningless without referring to the CPU | |
209 | * implementer: implementers are free to define their own part numbers | |
210 | * which are permitted to clash with other implementer part numbers. | |
211 | */ | |
212 | static inline unsigned int __attribute_const__ read_cpuid_part(void) | |
213 | { | |
eba1c718 | 214 | return read_cpuid_id() & ARM_CPU_PART_MASK; |
af040ffc RK |
215 | } |
216 | ||
217 | static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void) | |
59530adc CD |
218 | { |
219 | return read_cpuid_id() & 0xFFF0; | |
220 | } | |
221 | ||
222 | static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) | |
223 | { | |
af040ffc | 224 | return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK; |
59530adc CD |
225 | } |
226 | ||
bc581770 LW |
227 | static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) |
228 | { | |
229 | return read_cpuid(CPUID_TCM); | |
230 | } | |
231 | ||
c9018aab VG |
232 | static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) |
233 | { | |
234 | return read_cpuid(CPUID_MPIDR); | |
235 | } | |
236 | ||
83809b90 RK |
237 | /* StrongARM-11x0 CPUs */ |
238 | #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100) | |
239 | #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110) | |
240 | ||
0ba8b9b2 RK |
241 | /* |
242 | * Intel's XScale3 core supports some v6 features (supersections, L2) | |
243 | * but advertises itself as v5 as it does not support the v6 ISA. For | |
244 | * this reason, we need a way to explicitly test for this type of CPU. | |
245 | */ | |
246 | #ifndef CONFIG_CPU_XSC3 | |
247 | #define cpu_is_xsc3() 0 | |
248 | #else | |
249 | static inline int cpu_is_xsc3(void) | |
250 | { | |
337c1db6 HZ |
251 | unsigned int id; |
252 | id = read_cpuid_id() & 0xffffe000; | |
253 | /* It covers both Intel ID and Marvell ID */ | |
254 | if ((id == 0x69056000) || (id == 0x56056000)) | |
0ba8b9b2 RK |
255 | return 1; |
256 | ||
257 | return 0; | |
258 | } | |
259 | #endif | |
260 | ||
d33c43ac AB |
261 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \ |
262 | !defined(CONFIG_CPU_MOHAWK) | |
263 | #define cpu_is_xscale_family() 0 | |
0ba8b9b2 | 264 | #else |
d33c43ac AB |
265 | static inline int cpu_is_xscale_family(void) |
266 | { | |
267 | unsigned int id; | |
268 | id = read_cpuid_id() & 0xffffe000; | |
269 | ||
270 | switch (id) { | |
271 | case 0x69052000: /* Intel XScale 1 */ | |
272 | case 0x69054000: /* Intel XScale 2 */ | |
273 | case 0x69056000: /* Intel XScale 3 */ | |
274 | case 0x56056000: /* Marvell XScale 3 */ | |
275 | case 0x56158000: /* Marvell Mohawk */ | |
276 | return 1; | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
0ba8b9b2 RK |
281 | #endif |
282 | ||
fdb487f5 | 283 | /* |
cd171170 SH |
284 | * Marvell's PJ4 and PJ4B cores are based on V7 version, |
285 | * but require a specical sequence for enabling coprocessors. | |
286 | * For this reason, we need a way to distinguish them. | |
fdb487f5 | 287 | */ |
cd171170 | 288 | #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) |
fdb487f5 CXL |
289 | static inline int cpu_is_pj4(void) |
290 | { | |
291 | unsigned int id; | |
292 | ||
293 | id = read_cpuid_id(); | |
cd171170 | 294 | if ((id & 0xff0fff00) == 0x560f5800) |
fdb487f5 CXL |
295 | return 1; |
296 | ||
297 | return 0; | |
298 | } | |
cd171170 SH |
299 | #else |
300 | #define cpu_is_pj4() 0 | |
fdb487f5 | 301 | #endif |
b8c9592b AB |
302 | |
303 | static inline int __attribute_const__ cpuid_feature_extract_field(u32 features, | |
304 | int field) | |
305 | { | |
306 | int feature = (features >> field) & 15; | |
307 | ||
308 | /* feature registers are signed values */ | |
ac36a881 | 309 | if (feature > 7) |
b8c9592b AB |
310 | feature -= 16; |
311 | ||
312 | return feature; | |
313 | } | |
314 | ||
315 | #define cpuid_feature_extract(reg, field) \ | |
316 | cpuid_feature_extract_field(read_cpuid_ext(reg), field) | |
317 | ||
0ba8b9b2 | 318 | #endif |