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382266ad | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/hardware/cache-l2x0.h |
382266ad CM |
3 | * |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef __ASM_ARM_HARDWARE_L2X0_H | |
21 | #define __ASM_ARM_HARDWARE_L2X0_H | |
22 | ||
e7c86c7b OJ |
23 | #include <linux/errno.h> |
24 | ||
382266ad CM |
25 | #define L2X0_CACHE_ID 0x000 |
26 | #define L2X0_CACHE_TYPE 0x004 | |
27 | #define L2X0_CTRL 0x100 | |
28 | #define L2X0_AUX_CTRL 0x104 | |
1a5a954c RK |
29 | #define L310_TAG_LATENCY_CTRL 0x108 |
30 | #define L310_DATA_LATENCY_CTRL 0x10C | |
382266ad CM |
31 | #define L2X0_EVENT_CNT_CTRL 0x200 |
32 | #define L2X0_EVENT_CNT1_CFG 0x204 | |
33 | #define L2X0_EVENT_CNT0_CFG 0x208 | |
34 | #define L2X0_EVENT_CNT1_VAL 0x20C | |
35 | #define L2X0_EVENT_CNT0_VAL 0x210 | |
36 | #define L2X0_INTR_MASK 0x214 | |
37 | #define L2X0_MASKED_INTR_STAT 0x218 | |
38 | #define L2X0_RAW_INTR_STAT 0x21C | |
39 | #define L2X0_INTR_CLEAR 0x220 | |
40 | #define L2X0_CACHE_SYNC 0x730 | |
885028e4 | 41 | #define L2X0_DUMMY_REG 0x740 |
382266ad CM |
42 | #define L2X0_INV_LINE_PA 0x770 |
43 | #define L2X0_INV_WAY 0x77C | |
44 | #define L2X0_CLEAN_LINE_PA 0x7B0 | |
45 | #define L2X0_CLEAN_LINE_IDX 0x7B8 | |
46 | #define L2X0_CLEAN_WAY 0x7BC | |
47 | #define L2X0_CLEAN_INV_LINE_PA 0x7F0 | |
48 | #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 | |
49 | #define L2X0_CLEAN_INV_WAY 0x7FC | |
bac7e6ec LW |
50 | /* |
51 | * The lockdown registers repeat 8 times for L310, the L210 has only one | |
52 | * D and one I lockdown register at 0x0900 and 0x0904. | |
53 | */ | |
54 | #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 | |
55 | #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 | |
56 | #define L2X0_LOCKDOWN_STRIDE 0x08 | |
1a5a954c RK |
57 | #define L310_ADDR_FILTER_START 0xC00 |
58 | #define L310_ADDR_FILTER_END 0xC04 | |
382266ad CM |
59 | #define L2X0_TEST_OPERATION 0xF00 |
60 | #define L2X0_LINE_DATA 0xF10 | |
61 | #define L2X0_LINE_TAG 0xF30 | |
62 | #define L2X0_DEBUG_CTRL 0xF40 | |
1a5a954c RK |
63 | #define L310_PREFETCH_CTRL 0xF60 |
64 | #define L310_POWER_CTRL 0xF80 | |
65 | #define L310_DYNAMIC_CLK_GATING_EN (1 << 1) | |
66 | #define L310_STNDBY_MODE_EN (1 << 0) | |
382266ad | 67 | |
7db27e86 SS |
68 | /* Registers shifts and masks */ |
69 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) | |
70 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) | |
14b882cf | 71 | #define L2X0_CACHE_ID_PART_L220 (2 << 6) |
7db27e86 | 72 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) |
91c2ebb9 | 73 | #define L2X0_CACHE_ID_RTL_MASK 0x3f |
14b882cf RK |
74 | #define L210_CACHE_ID_RTL_R0P2_02 0x00 |
75 | #define L210_CACHE_ID_RTL_R0P1 0x01 | |
76 | #define L210_CACHE_ID_RTL_R0P2_01 0x02 | |
77 | #define L210_CACHE_ID_RTL_R0P3 0x03 | |
78 | #define L210_CACHE_ID_RTL_R0P4 0x0b | |
79 | #define L210_CACHE_ID_RTL_R0P5 0x0f | |
80 | #define L220_CACHE_ID_RTL_R1P7_01REL0 0x06 | |
81 | #define L310_CACHE_ID_RTL_R0P0 0x00 | |
82 | #define L310_CACHE_ID_RTL_R1P0 0x02 | |
83 | #define L310_CACHE_ID_RTL_R2P0 0x04 | |
84 | #define L310_CACHE_ID_RTL_R3P0 0x05 | |
85 | #define L310_CACHE_ID_RTL_R3P1 0x06 | |
86 | #define L310_CACHE_ID_RTL_R3P1_50REL0 0x07 | |
87 | #define L310_CACHE_ID_RTL_R3P2 0x08 | |
88 | #define L310_CACHE_ID_RTL_R3P3 0x09 | |
0aaa6f8f | 89 | |
b828f960 MR |
90 | #define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0) |
91 | ||
92 | #define L2X0_EVENT_CNT_CFG_SRC_SHIFT 2 | |
93 | #define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf | |
94 | #define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0 | |
95 | #define L2X0_EVENT_CNT_CFG_INT_DISABLED 0 | |
96 | #define L2X0_EVENT_CNT_CFG_INT_INCR 1 | |
97 | #define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2 | |
98 | ||
1a5a954c RK |
99 | /* L2C auxiliary control register - bits common to L2C-210/220/310 */ |
100 | #define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17 | |
101 | #define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17) | |
102 | #define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17) | |
103 | #define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) | |
104 | #define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) | |
105 | #define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) | |
106 | /* L2C-210/220 common bits */ | |
8c369264 | 107 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 |
1a5a954c | 108 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0) |
8c369264 | 109 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 |
1a5a954c | 110 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3) |
8c369264 | 111 | #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 |
1a5a954c | 112 | #define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6) |
8c369264 | 113 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 |
1a5a954c RK |
114 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) |
115 | #define L2X0_AUX_CTRL_ASSOC_SHIFT 13 | |
116 | #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) | |
117 | /* L2C-210 specific bits */ | |
118 | #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) | |
119 | #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) | |
120 | #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) | |
121 | /* L2C-220 specific bits */ | |
122 | #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) | |
123 | #define L220_AUX_CTRL_FWA_SHIFT 23 | |
124 | #define L220_AUX_CTRL_FWA_MASK (3 << 23) | |
125 | #define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) | |
126 | #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) | |
127 | /* L2C-310 specific bits */ | |
128 | #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ | |
129 | #define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */ | |
130 | #define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */ | |
131 | #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) | |
132 | #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) | |
133 | #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ | |
134 | #define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) | |
135 | #define L310_AUX_CTRL_NS_INT_CTRL BIT(27) | |
136 | #define L310_AUX_CTRL_DATA_PREFETCH BIT(28) | |
137 | #define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) | |
138 | #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ | |
7db27e86 | 139 | |
1a5a954c RK |
140 | #define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) |
141 | #define L310_LATENCY_CTRL_RD(n) ((n) << 4) | |
142 | #define L310_LATENCY_CTRL_WR(n) ((n) << 8) | |
8c369264 | 143 | |
1a5a954c | 144 | #define L310_ADDR_FILTER_EN 1 |
8c369264 | 145 | |
8ef418c7 RK |
146 | #define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f |
147 | #define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23) | |
148 | #define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24) | |
149 | #define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27) | |
150 | #define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) | |
151 | #define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) | |
152 | #define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30) | |
153 | ||
b8db6b88 GC |
154 | #define L2X0_CTRL_EN 1 |
155 | ||
156 | #define L2X0_WAY_SIZE_SHIFT 3 | |
157 | ||
382266ad | 158 | #ifndef __ASSEMBLY__ |
3e175ca4 | 159 | extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); |
fae2b89a | 160 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) |
3e175ca4 | 161 | extern int l2x0_of_init(u32 aux_val, u32 aux_mask); |
fae2b89a | 162 | #else |
3e175ca4 | 163 | static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) |
fae2b89a RH |
164 | { |
165 | return -ENODEV; | |
166 | } | |
167 | #endif | |
91c2ebb9 | 168 | |
b828f960 MR |
169 | #ifdef CONFIG_CACHE_L2X0_PMU |
170 | void l2x0_pmu_register(void __iomem *base, u32 part); | |
171 | void l2x0_pmu_suspend(void); | |
172 | void l2x0_pmu_resume(void); | |
173 | #else | |
174 | static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} | |
175 | static inline void l2x0_pmu_suspend(void) {} | |
176 | static inline void l2x0_pmu_resume(void) {} | |
177 | #endif | |
178 | ||
91c2ebb9 BS |
179 | struct l2x0_regs { |
180 | unsigned long phy_base; | |
181 | unsigned long aux_ctrl; | |
182 | /* | |
183 | * Whether the following registers need to be saved/restored | |
184 | * depends on platform | |
185 | */ | |
186 | unsigned long tag_latency; | |
187 | unsigned long data_latency; | |
188 | unsigned long filter_start; | |
189 | unsigned long filter_end; | |
190 | unsigned long prefetch_ctrl; | |
191 | unsigned long pwr_ctrl; | |
c3545236 | 192 | unsigned long ctrl; |
e68f31f4 | 193 | unsigned long aux2_ctrl; |
91c2ebb9 BS |
194 | }; |
195 | ||
196 | extern struct l2x0_regs l2x0_saved_regs; | |
197 | ||
fae2b89a | 198 | #endif /* __ASSEMBLY__ */ |
382266ad CM |
199 | |
200 | #endif |