[mirror_ubuntu-hirsute-kernel.git] / arch / arm / include / asm / hardware / iop3xx.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/include/asm/hardware/iop3xx.h
 *
 * Intel IOP32X and IOP33X register definitions
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 * Copyright (C) 2004 Intel Corp.
 */

#ifndef __IOP3XX_H
#define __IOP3XX_H

/*
 * IOP3XX GPIO handling
 */
#define IOP3XX_GPIO_LINE(x)	(x)

#ifndef __ASSEMBLY__
extern int init_atu;
extern int iop3xx_get_init_atu(void);
#endif


/*
 * IOP3XX processor registers
 */
#define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
#define IOP3XX_PERIPHERAL_VIRT_BASE	0xfedfe000
#define IOP3XX_PERIPHERAL_SIZE		0x00002000
#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
					IOP3XX_PERIPHERAL_SIZE - 1)
#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
					IOP3XX_PERIPHERAL_SIZE - 1)
#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
					(IOP3XX_PERIPHERAL_PHYS_BASE\
					- IOP3XX_PERIPHERAL_VIRT_BASE))
#define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))

/* Address Translation Unit  */
#define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
#define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
#define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
#define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
#define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
#define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
#define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
#define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
#define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
#define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
#define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
#define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
#define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
#define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
#define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
#define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
#define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
#define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
#define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
#define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
#define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
#define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
#define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
#define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
#define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
#define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
#define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
#define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
#define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
#define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
#define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
#define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
#define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
#define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
#define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
#define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
#define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
#define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
#define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
#define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
#define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
#define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
#define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
#define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
#define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
#define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
#define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
#define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
#define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
#define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
#define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
#define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
#define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
#define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
#define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
#define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP3XX_PCSR_IN_Q_BUSY	(1 << 14)
#define IOP3XX_ATUCR_OUT_EN	(1 << 1)

#define IOP3XX_INIT_ATU_DEFAULT 0
#define IOP3XX_INIT_ATU_DISABLE -1
#define IOP3XX_INIT_ATU_ENABLE	 1

/* Messaging Unit  */
#define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
#define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
#define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
#define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
#define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
#define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
#define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
#define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
#define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
#define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
#define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
#define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
#define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
#define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
#define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
#define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
#define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
#define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
#define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
#define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
#define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)

/* DMA Controller  */
#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
					(0x400 + (chan << 6)))
#define IOP3XX_DMA_UPPER_PA(chan)  (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)

/* Peripheral bus interface  */
#define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
#define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
#define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
#define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
#define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
#define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
#define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
#define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
#define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
#define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
#define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
#define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
#define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
#define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
#define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
#define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
#define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)

/* Peripheral performance monitoring unit  */
#define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
#define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
#define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
#define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
/* PERCR0 DOESN'T EXIST - index from 1! */
#define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)

/* Timers  */
#define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
#define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
#define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
#define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
#define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
#define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
#define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
#define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
#define IOP_TMR_EN	    0x02
#define IOP_TMR_RELOAD	    0x04
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1  0x00

/* Watchdog timer definitions */
#define IOP_WDTCR_EN_ARM        0x1e1e1e1e
#define IOP_WDTCR_EN            0xe1e1e1e1
/* iop3xx does not support stopping the watchdog, so we just re-arm */
#define IOP_WDTCR_DIS_ARM	(IOP_WDTCR_EN_ARM)
#define IOP_WDTCR_DIS		(IOP_WDTCR_EN)

/* Application accelerator unit  */
#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)

/* I2C bus interface unit  */
#define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
#define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
#define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
#define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
#define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
#define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
#define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
#define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
#define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
#define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)


/*
 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
 */
#define IOP3XX_PCI_LOWER_MEM_PA	0x80000000
#define IOP3XX_PCI_MEM_WINDOW_SIZE	0x08000000

#define IOP3XX_PCI_LOWER_IO_PA		0x90000000
#define IOP3XX_PCI_LOWER_IO_BA		0x00000000

#ifndef __ASSEMBLY__

#include <linux/types.h>
#include <linux/reboot.h>

void iop3xx_map_io(void);
void iop_init_cp6_handler(void);
void iop_init_time(unsigned long tickrate);
void iop3xx_restart(enum reboot_mode, const char *);

static inline u32 read_tmr0(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
	return val;
}

static inline void write_tmr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
}

static inline void write_tmr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
}

static inline u32 read_tcr0(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
	return val;
}

static inline void write_tcr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
}

static inline u32 read_tcr1(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
	return val;
}

static inline void write_tcr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
}

static inline void write_trr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
}

static inline void write_trr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
}

static inline void write_tisr(u32 val)
{
	asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
}

static inline u32 read_wdtcr(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
	return val;
}
static inline void write_wdtcr(u32 val)
{
	asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
}

extern unsigned long get_iop_tick_rate(void);

/* only iop13xx has these registers, we define these to present a
 * common register interface for the iop_wdt driver.
 */
#define IOP_RCSR_WDT	(0)
static inline u32 read_rcsr(void)
{
	return 0;
}
static inline void write_wdtsr(u32 val)
{
	do { } while (0);
}

extern struct platform_device iop3xx_dma_0_channel;
extern struct platform_device iop3xx_dma_1_channel;
extern struct platform_device iop3xx_aau_channel;
extern struct platform_device iop3xx_i2c0_device;
extern struct platform_device iop3xx_i2c1_device;

#endif


#endif
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
7ae1f7ec	2	/*
4baa9922	3	* arch/arm/include/asm/hardware/iop3xx.h
7ae1f7ec LB	4	*
	5	* Intel IOP32X and IOP33X register definitions
	6	*
	7	* Author: Rory Bolt <rorybolt@pacbell.net>
	8	* Copyright (C) 2002 Rory Bolt
	9	* Copyright (C) 2004 Intel Corp.
7ae1f7ec LB	10	*/
	11
	12	#ifndef __IOP3XX_H
	13	#define __IOP3XX_H
	14
72edd84a LB	15	/*
	16	* IOP3XX GPIO handling
	17	*/
72edd84a LB	18	#define IOP3XX_GPIO_LINE(x) (x)
	19
	20	#ifndef __ASSEMBLY__
e90ddd81	21	extern int init_atu;
c34002c1	22	extern int iop3xx_get_init_atu(void);
72edd84a LB	23	#endif
	24
	25
7ae1f7ec LB	26	/*
	27	* IOP3XX processor registers
	28	*/
	29	#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
f5d6a144	30	#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
7ae1f7ec	31	#define IOP3XX_PERIPHERAL_SIZE 0x00002000
6df26700 DW	32	#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
	33	IOP3XX_PERIPHERAL_SIZE - 1)
	34	#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
	35	IOP3XX_PERIPHERAL_SIZE - 1)
ad902cb9	36	#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
6df26700 DW	37	(IOP3XX_PERIPHERAL_PHYS_BASE\
6df26700 DW	38	- IOP3XX_PERIPHERAL_VIRT_BASE))
7ae1f7ec LB	39	#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
7ae1f7ec LB	40
0cb015f9 LB	41	/* Address Translation Unit */
	42	#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
	43	#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
	44	#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
	45	#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
	46	#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
	47	#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
	48	#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
	49	#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
	50	#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
	51	#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
	52	#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
	53	#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
	54	#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
	55	#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
	56	#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
	57	#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
	58	#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
	59	#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
	60	#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
	61	#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
	62	#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
	63	#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
	64	#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
	65	#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
	66	#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
	67	#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
	68	#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
	69	#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
	70	#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
	71	#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
	72	#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
	73	#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
	74	#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
	75	#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
	76	#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
	77	#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
	78	#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
	79	#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
	80	#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
	81	#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
	82	#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
	83	#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
	84	#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
	85	#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
	86	#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
	87	#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
	88	#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
	89	#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
	90	#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
	91	#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
	92	#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
	93	#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
	94	#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
	95	#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
	96	#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
	97	#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
e90ddd81 DW	98	#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
	99	#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
	100	#define IOP3XX_ATUCR_OUT_EN (1 << 1)
	101
	102	#define IOP3XX_INIT_ATU_DEFAULT 0
	103	#define IOP3XX_INIT_ATU_DISABLE -1
	104	#define IOP3XX_INIT_ATU_ENABLE 1
	105
475549fa LB	106	/* Messaging Unit */
	107	#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
	108	#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
	109	#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
	110	#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
	111	#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
	112	#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
	113	#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
	114	#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
	115	#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
	116	#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
	117	#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
	118	#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
	119	#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
	120	#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
	121	#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
	122	#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
	123	#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
	124	#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
	125	#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
	126	#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
	127	#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
	128
	129	/* DMA Controller */
2492c845 DW	130	#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
	131	(0x400 + (chan << 6)))
	132	#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
475549fa LB	133
	134	/* Peripheral bus interface */
	135	#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
	136	#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
	137	#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
	138	#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
	139	#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
	140	#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
	141	#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
	142	#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
	143	#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
	144	#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
	145	#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
	146	#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
	147	#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
	148	#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
	149	#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
	150	#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
	151	#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
	152
	153	/* Peripheral performance monitoring unit */
	154	#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
	155	#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
	156	#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
	157	#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
	158	/* PERCR0 DOESN'T EXIST - index from 1! */
	159	#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
	160
48388b2a LB	161	/* Timers */
	162	#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
	163	#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
	164	#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
	165	#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
	166	#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
	167	#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
	168	#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
	169	#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
3668b45d DW	170	#define IOP_TMR_EN 0x02
	171	#define IOP_TMR_RELOAD 0x04
	172	#define IOP_TMR_PRIVILEGED 0x08
	173	#define IOP_TMR_RATIO_1_1 0x00
48388b2a	174
70c14ff0 DW	175	/* Watchdog timer definitions */
	176	#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
	177	#define IOP_WDTCR_EN 0xe1e1e1e1
	178	/* iop3xx does not support stopping the watchdog, so we just re-arm */
	179	#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
	180	#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
	181
475549fa	182	/* Application accelerator unit */
2492c845 DW	183	#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
2492c845 DW	184	#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
475549fa	185
e25d64f1 LB	186	/* I2C bus interface unit */
	187	#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
	188	#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
	189	#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
	190	#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
	191	#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
	192	#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
	193	#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
	194	#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
	195	#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
	196	#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
	197
7ae1f7ec LB	198
	199	/*
	200	* IOP3XX I/O and Mem space regions for PCI autoconfiguration
	201	*/
e90ddd81	202	#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
5b9eda33	203	#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
7ae1f7ec	204
7ae1f7ec	205	#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
dd9bf780	206	#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
7ae1f7ec LB	207
7ae1f7ec LB	208	#ifndef __ASSEMBLY__
15e9b9b9 DH	209
15e9b9b9 DH	210	#include <linux/types.h>
7b6d864b	211	#include <linux/reboot.h>
15e9b9b9	212
7ae1f7ec	213	void iop3xx_map_io(void);
588ef769	214	void iop_init_cp6_handler(void);
3668b45d	215	void iop_init_time(unsigned long tickrate);
7b6d864b	216	void iop3xx_restart(enum reboot_mode, const char *);
3668b45d	217
469d3044 MP	218	static inline u32 read_tmr0(void)
	219	{
	220	u32 val;
	221	asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
	222	return val;
	223	}
	224
3668b45d DW	225	static inline void write_tmr0(u32 val)
	226	{
	227	asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
	228	}
	229
	230	static inline void write_tmr1(u32 val)
	231	{
	232	asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
	233	}
	234
	235	static inline u32 read_tcr0(void)
	236	{
	237	u32 val;
	238	asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
	239	return val;
	240	}
	241
469d3044 MP	242	static inline void write_tcr0(u32 val)
	243	{
	244	asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
	245	}
	246
3668b45d DW	247	static inline u32 read_tcr1(void)
	248	{
	249	u32 val;
	250	asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
	251	return val;
	252	}
	253
a91549a8 MP	254	static inline void write_tcr1(u32 val)
	255	{
	256	asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
	257	}
	258
3668b45d DW	259	static inline void write_trr0(u32 val)
	260	{
	261	asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
	262	}
	263
	264	static inline void write_trr1(u32 val)
	265	{
	266	asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
	267	}
	268
	269	static inline void write_tisr(u32 val)
	270	{
	271	asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
	272	}
e25d64f1	273
70c14ff0 DW	274	static inline u32 read_wdtcr(void)
	275	{
	276	u32 val;
	277	asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
	278	return val;
	279	}
	280	static inline void write_wdtcr(u32 val)
	281	{
	282	asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
	283	}
	284
	285	extern unsigned long get_iop_tick_rate(void);
	286
	287	/* only iop13xx has these registers, we define these to present a
	288	* common register interface for the iop_wdt driver.
	289	*/
	290	#define IOP_RCSR_WDT (0)
	291	static inline u32 read_rcsr(void)
	292	{
	293	return 0;
	294	}
	295	static inline void write_wdtsr(u32 val)
	296	{
	297	do { } while (0);
	298	}
	299
2492c845 DW	300	extern struct platform_device iop3xx_dma_0_channel;
	301	extern struct platform_device iop3xx_dma_1_channel;
	302	extern struct platform_device iop3xx_aau_channel;
e25d64f1 LB	303	extern struct platform_device iop3xx_i2c0_device;
e25d64f1 LB	304	extern struct platform_device iop3xx_i2c1_device;
0b29de4a	305
7ae1f7ec LB	306	#endif
	307
	308
	309	#endif