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a61127c2 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
c2110923 DW |
2 | /* |
3 | * Copyright © 2006, Intel Corporation. | |
c2110923 DW |
4 | */ |
5 | #ifndef IOP_ADMA_H | |
6 | #define IOP_ADMA_H | |
7 | #include <linux/types.h> | |
8 | #include <linux/dmaengine.h> | |
9 | #include <linux/interrupt.h> | |
10 | ||
11 | #define IOP_ADMA_SLOT_SIZE 32 | |
12 | #define IOP_ADMA_THRESHOLD 4 | |
65e50381 DW |
13 | #ifdef DEBUG |
14 | #define IOP_PARANOIA 1 | |
15 | #else | |
16 | #define IOP_PARANOIA 0 | |
17 | #endif | |
18 | #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) | |
c2110923 DW |
19 | |
20 | /** | |
21 | * struct iop_adma_device - internal representation of an ADMA device | |
22 | * @pdev: Platform device | |
23 | * @id: HW ADMA Device selector | |
24 | * @dma_desc_pool: base of DMA descriptor region (DMA address) | |
25 | * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) | |
26 | * @common: embedded struct dma_device | |
27 | */ | |
28 | struct iop_adma_device { | |
29 | struct platform_device *pdev; | |
30 | int id; | |
31 | dma_addr_t dma_desc_pool; | |
32 | void *dma_desc_pool_virt; | |
33 | struct dma_device common; | |
34 | }; | |
35 | ||
36 | /** | |
37 | * struct iop_adma_chan - internal representation of an ADMA device | |
38 | * @pending: allows batching of hardware operations | |
c2110923 DW |
39 | * @lock: serializes enqueue/dequeue operations to the slot pool |
40 | * @mmr_base: memory mapped register base | |
41 | * @chain: device chain view of the descriptors | |
42 | * @device: parent device | |
43 | * @common: common dmaengine channel object members | |
44 | * @last_used: place holder for allocation to continue from where it left off | |
45 | * @all_slots: complete domain of slots usable by the channel | |
c2110923 DW |
46 | * @slots_allocated: records the actual size of the descriptor slot pool |
47 | * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs | |
48 | */ | |
49 | struct iop_adma_chan { | |
50 | int pending; | |
c2110923 DW |
51 | spinlock_t lock; /* protects the descriptor slot pool */ |
52 | void __iomem *mmr_base; | |
53 | struct list_head chain; | |
54 | struct iop_adma_device *device; | |
55 | struct dma_chan common; | |
56 | struct iop_adma_desc_slot *last_used; | |
57 | struct list_head all_slots; | |
c2110923 DW |
58 | int slots_allocated; |
59 | struct tasklet_struct irq_tasklet; | |
60 | }; | |
61 | ||
62 | /** | |
63 | * struct iop_adma_desc_slot - IOP-ADMA software descriptor | |
64 | * @slot_node: node on the iop_adma_chan.all_slots list | |
65 | * @chain_node: node on the op_adma_chan.chain list | |
66 | * @hw_desc: virtual address of the hardware descriptor chain | |
67 | * @phys: hardware address of the hardware descriptor chain | |
68 | * @group_head: first operation in a transaction | |
69 | * @slot_cnt: total slots used in an transaction (group of operations) | |
70 | * @slots_per_op: number of slots per operation | |
71 | * @idx: pool index | |
308136d1 | 72 | * @tx_list: list of descriptors that are associated with one operation |
c2110923 DW |
73 | * @async_tx: support for the async_tx api |
74 | * @group_list: list of slots that make up a multi-descriptor transaction | |
75 | * for example transfer lengths larger than the supported hw max | |
76 | * @xor_check_result: result of zero sum | |
77 | * @crc32_result: result crc calculation | |
78 | */ | |
79 | struct iop_adma_desc_slot { | |
80 | struct list_head slot_node; | |
81 | struct list_head chain_node; | |
82 | void *hw_desc; | |
83 | struct iop_adma_desc_slot *group_head; | |
84 | u16 slot_cnt; | |
85 | u16 slots_per_op; | |
86 | u16 idx; | |
308136d1 | 87 | struct list_head tx_list; |
c2110923 DW |
88 | struct dma_async_tx_descriptor async_tx; |
89 | union { | |
90 | u32 *xor_check_result; | |
91 | u32 *crc32_result; | |
7bf649ae | 92 | u32 *pq_check_result; |
c2110923 DW |
93 | }; |
94 | }; | |
95 | ||
96 | struct iop_adma_platform_data { | |
97 | int hw_id; | |
98 | dma_cap_mask_t cap_mask; | |
99 | size_t pool_size; | |
100 | }; | |
101 | ||
102 | #define to_iop_sw_desc(addr_hw_desc) \ | |
103 | container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) | |
104 | #define iop_hw_desc_slot_idx(hw_desc, idx) \ | |
105 | ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) | |
106 | #endif |