[mirror_ubuntu-artful-kernel.git] / arch / arm / include / asm / kvm_arm.h

/*
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#ifndef __ARM_KVM_ARM_H__
#define __ARM_KVM_ARM_H__

#include <linux/types.h>

/* Hyp Configuration Register (HCR) bits */
#define HCR_TGE		(1 << 27)
#define HCR_TVM		(1 << 26)
#define HCR_TTLB	(1 << 25)
#define HCR_TPU		(1 << 24)
#define HCR_TPC		(1 << 23)
#define HCR_TSW		(1 << 22)
#define HCR_TAC		(1 << 21)
#define HCR_TIDCP	(1 << 20)
#define HCR_TSC		(1 << 19)
#define HCR_TID3	(1 << 18)
#define HCR_TID2	(1 << 17)
#define HCR_TID1	(1 << 16)
#define HCR_TID0	(1 << 15)
#define HCR_TWE		(1 << 14)
#define HCR_TWI		(1 << 13)
#define HCR_DC		(1 << 12)
#define HCR_BSU		(3 << 10)
#define HCR_BSU_IS	(1 << 10)
#define HCR_FB		(1 << 9)
#define HCR_VA		(1 << 8)
#define HCR_VI		(1 << 7)
#define HCR_VF		(1 << 6)
#define HCR_AMO		(1 << 5)
#define HCR_IMO		(1 << 4)
#define HCR_FMO		(1 << 3)
#define HCR_PTW		(1 << 2)
#define HCR_SWIO	(1 << 1)
#define HCR_VM		1

/*
 * The bits we set in HCR:
 * TAC:		Trap ACTLR
 * TSC:		Trap SMC
 * TSW:		Trap cache operations by set/way
 * TWI:		Trap WFI
 * TIDCP:	Trap L2CTLR/L2ECTLR
 * BSU_IS:	Upgrade barriers to the inner shareable domain
 * FB:		Force broadcast of all maintainance operations
 * AMO:		Override CPSR.A and enable signaling with VA
 * IMO:		Override CPSR.I and enable signaling with VI
 * FMO:		Override CPSR.F and enable signaling with VF
 * SWIO:	Turn set/way invalidates into set/way clean+invalidate
 */
#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
			HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
			HCR_SWIO | HCR_TIDCP)
#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)

/* Hyp System Control Register (HSCTLR) bits */
#define HSCTLR_TE	(1 << 30)
#define HSCTLR_EE	(1 << 25)
#define HSCTLR_FI	(1 << 21)
#define HSCTLR_WXN	(1 << 19)
#define HSCTLR_I	(1 << 12)
#define HSCTLR_C	(1 << 2)
#define HSCTLR_A	(1 << 1)
#define HSCTLR_M	1
#define HSCTLR_MASK	(HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
			 HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)

/* TTBCR and HTCR Registers bits */
#define TTBCR_EAE	(1 << 31)
#define TTBCR_IMP	(1 << 30)
#define TTBCR_SH1	(3 << 28)
#define TTBCR_ORGN1	(3 << 26)
#define TTBCR_IRGN1	(3 << 24)
#define TTBCR_EPD1	(1 << 23)
#define TTBCR_A1	(1 << 22)
#define TTBCR_T1SZ	(3 << 16)
#define TTBCR_SH0	(3 << 12)
#define TTBCR_ORGN0	(3 << 10)
#define TTBCR_IRGN0	(3 << 8)
#define TTBCR_EPD0	(1 << 7)
#define TTBCR_T0SZ	3
#define HTCR_MASK	(TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)

/* Hyp Debug Configuration Register bits */
#define HDCR_TDRA	(1 << 11)
#define HDCR_TDOSA	(1 << 10)
#define HDCR_TDA	(1 << 9)
#define HDCR_TDE	(1 << 8)
#define HDCR_HPME	(1 << 7)
#define HDCR_TPM	(1 << 6)
#define HDCR_TPMCR	(1 << 5)
#define HDCR_HPMN_MASK	(0x1F)

/*
 * The architecture supports 40-bit IPA as input to the 2nd stage translations
 * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
 * space.
 */
#define KVM_PHYS_SHIFT	(40)
#define KVM_PHYS_SIZE	(1ULL << KVM_PHYS_SHIFT)
#define KVM_PHYS_MASK	(KVM_PHYS_SIZE - 1ULL)
#define PTRS_PER_S2_PGD	(1ULL << (KVM_PHYS_SHIFT - 30))
#define S2_PGD_ORDER	get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
#define S2_PGD_SIZE	(1 << S2_PGD_ORDER)

/* Virtualization Translation Control Register (VTCR) bits */
#define VTCR_SH0	(3 << 12)
#define VTCR_ORGN0	(3 << 10)
#define VTCR_IRGN0	(3 << 8)
#define VTCR_SL0	(3 << 6)
#define VTCR_S		(1 << 4)
#define VTCR_T0SZ	(0xf)
#define VTCR_MASK	(VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
			 VTCR_S | VTCR_T0SZ)
#define VTCR_HTCR_SH	(VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
#define VTCR_SL_L2	(0 << 6)	/* Starting-level: 2 */
#define VTCR_SL_L1	(1 << 6)	/* Starting-level: 1 */
#define KVM_VTCR_SL0	VTCR_SL_L1
/* stage-2 input address range defined as 2^(32-T0SZ) */
#define KVM_T0SZ	(32 - KVM_PHYS_SHIFT)
#define KVM_VTCR_T0SZ	(KVM_T0SZ & VTCR_T0SZ)
#define KVM_VTCR_S	((KVM_VTCR_T0SZ << 1) & VTCR_S)

/* Virtualization Translation Table Base Register (VTTBR) bits */
#if KVM_VTCR_SL0 == VTCR_SL_L2	/* see ARM DDI 0406C: B4-1720 */
#define VTTBR_X		(14 - KVM_T0SZ)
#else
#define VTTBR_X		(5 - KVM_T0SZ)
#endif


#endif /* __ARM_KVM_ARM_H__ */
Commit	Line	Data
749cf76c CD	1	/*
	2	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	3	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License, version 2, as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	17	*/
	18
	19	#ifndef __ARM_KVM_ARM_H__
	20	#define __ARM_KVM_ARM_H__
	21
	22	#include <linux/types.h>
	23
342cd0ab CD	24	/* Hyp Configuration Register (HCR) bits */
	25	#define HCR_TGE (1 << 27)
	26	#define HCR_TVM (1 << 26)
	27	#define HCR_TTLB (1 << 25)
	28	#define HCR_TPU (1 << 24)
	29	#define HCR_TPC (1 << 23)
	30	#define HCR_TSW (1 << 22)
	31	#define HCR_TAC (1 << 21)
	32	#define HCR_TIDCP (1 << 20)
	33	#define HCR_TSC (1 << 19)
	34	#define HCR_TID3 (1 << 18)
	35	#define HCR_TID2 (1 << 17)
	36	#define HCR_TID1 (1 << 16)
	37	#define HCR_TID0 (1 << 15)
	38	#define HCR_TWE (1 << 14)
	39	#define HCR_TWI (1 << 13)
	40	#define HCR_DC (1 << 12)
	41	#define HCR_BSU (3 << 10)
	42	#define HCR_BSU_IS (1 << 10)
	43	#define HCR_FB (1 << 9)
	44	#define HCR_VA (1 << 8)
	45	#define HCR_VI (1 << 7)
	46	#define HCR_VF (1 << 6)
	47	#define HCR_AMO (1 << 5)
	48	#define HCR_IMO (1 << 4)
	49	#define HCR_FMO (1 << 3)
	50	#define HCR_PTW (1 << 2)
	51	#define HCR_SWIO (1 << 1)
	52	#define HCR_VM 1
	53
	54	/*
	55	* The bits we set in HCR:
	56	* TAC: Trap ACTLR
	57	* TSC: Trap SMC
	58	* TSW: Trap cache operations by set/way
	59	* TWI: Trap WFI
	60	* TIDCP: Trap L2CTLR/L2ECTLR
	61	* BSU_IS: Upgrade barriers to the inner shareable domain
	62	* FB: Force broadcast of all maintainance operations
	63	* AMO: Override CPSR.A and enable signaling with VA
	64	* IMO: Override CPSR.I and enable signaling with VI
	65	* FMO: Override CPSR.F and enable signaling with VF
	66	* SWIO: Turn set/way invalidates into set/way clean+invalidate
	67	*/
	68	#define HCR_GUEST_MASK (HCR_TSC \| HCR_TSW \| HCR_TWI \| HCR_VM \| HCR_BSU_IS \| \
	69	HCR_FB \| HCR_TAC \| HCR_AMO \| HCR_IMO \| HCR_FMO \| \
	70	HCR_SWIO \| HCR_TIDCP)
86ce8535	71	#define HCR_VIRT_EXCP_MASK (HCR_VA \| HCR_VI \| HCR_VF)
342cd0ab CD	72
	73	/* Hyp System Control Register (HSCTLR) bits */
	74	#define HSCTLR_TE (1 << 30)
	75	#define HSCTLR_EE (1 << 25)
	76	#define HSCTLR_FI (1 << 21)
	77	#define HSCTLR_WXN (1 << 19)
	78	#define HSCTLR_I (1 << 12)
	79	#define HSCTLR_C (1 << 2)
	80	#define HSCTLR_A (1 << 1)
	81	#define HSCTLR_M 1
	82	#define HSCTLR_MASK (HSCTLR_M \| HSCTLR_A \| HSCTLR_C \| HSCTLR_I \| \
	83	HSCTLR_WXN \| HSCTLR_FI \| HSCTLR_EE \| HSCTLR_TE)
	84
	85	/* TTBCR and HTCR Registers bits */
	86	#define TTBCR_EAE (1 << 31)
	87	#define TTBCR_IMP (1 << 30)
	88	#define TTBCR_SH1 (3 << 28)
	89	#define TTBCR_ORGN1 (3 << 26)
	90	#define TTBCR_IRGN1 (3 << 24)
	91	#define TTBCR_EPD1 (1 << 23)
	92	#define TTBCR_A1 (1 << 22)
	93	#define TTBCR_T1SZ (3 << 16)
	94	#define TTBCR_SH0 (3 << 12)
	95	#define TTBCR_ORGN0 (3 << 10)
	96	#define TTBCR_IRGN0 (3 << 8)
	97	#define TTBCR_EPD0 (1 << 7)
	98	#define TTBCR_T0SZ 3
	99	#define HTCR_MASK (TTBCR_T0SZ \| TTBCR_IRGN0 \| TTBCR_ORGN0 \| TTBCR_SH0)
	100
	101	/* Hyp Debug Configuration Register bits */
	102	#define HDCR_TDRA (1 << 11)
	103	#define HDCR_TDOSA (1 << 10)
	104	#define HDCR_TDA (1 << 9)
	105	#define HDCR_TDE (1 << 8)
	106	#define HDCR_HPME (1 << 7)
	107	#define HDCR_TPM (1 << 6)
	108	#define HDCR_TPMCR (1 << 5)
	109	#define HDCR_HPMN_MASK (0x1F)
	110
	111	/*
	112	* The architecture supports 40-bit IPA as input to the 2nd stage translations
	113	* and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
	114	* space.
	115	*/
	116	#define KVM_PHYS_SHIFT (40)
	117	#define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT)
	118	#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL)
	119	#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
	120	#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
	121	#define S2_PGD_SIZE (1 << S2_PGD_ORDER)
	122
	123	/* Virtualization Translation Control Register (VTCR) bits */
	124	#define VTCR_SH0 (3 << 12)
	125	#define VTCR_ORGN0 (3 << 10)
	126	#define VTCR_IRGN0 (3 << 8)
	127	#define VTCR_SL0 (3 << 6)
	128	#define VTCR_S (1 << 4)
	129	#define VTCR_T0SZ (0xf)
	130	#define VTCR_MASK (VTCR_SH0 \| VTCR_ORGN0 \| VTCR_IRGN0 \| VTCR_SL0 \| \
	131	VTCR_S \| VTCR_T0SZ)
	132	#define VTCR_HTCR_SH (VTCR_SH0 \| VTCR_ORGN0 \| VTCR_IRGN0)
	133	#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */
	134	#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */
	135	#define KVM_VTCR_SL0 VTCR_SL_L1
136	/* stage-2 input address range defined as 2^(32-T0SZ) */
137	#define KVM_T0SZ (32 - KVM_PHYS_SHIFT)
138	#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ)
139	#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S)
140
141	/* Virtualization Translation Table Base Register (VTTBR) bits */
142	#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */
143	#define VTTBR_X (14 - KVM_T0SZ)
144	#else
145	#define VTTBR_X (5 - KVM_T0SZ)
146	#endif
147
148
749cf76c	149	#endif /* __ARM_KVM_ARM_H__ */