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342cd0ab CD |
1 | /* |
2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
3 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __ARM_KVM_MMU_H__ | |
20 | #define __ARM_KVM_MMU_H__ | |
21 | ||
5a677ce0 MZ |
22 | #include <asm/memory.h> |
23 | #include <asm/page.h> | |
c62ee2b2 | 24 | |
06e8c3b0 MZ |
25 | /* |
26 | * We directly use the kernel VA for the HYP, as we can directly share | |
27 | * the mapping (HTTBR "covers" TTBR1). | |
28 | */ | |
6c41a413 | 29 | #define kern_hyp_va(kva) (kva) |
06e8c3b0 | 30 | |
38f791a4 CD |
31 | /* |
32 | * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels. | |
33 | */ | |
34 | #define KVM_MMU_CACHE_MIN_PAGES 2 | |
35 | ||
5a677ce0 MZ |
36 | #ifndef __ASSEMBLY__ |
37 | ||
363ef89f | 38 | #include <linux/highmem.h> |
5a677ce0 MZ |
39 | #include <asm/cacheflush.h> |
40 | #include <asm/pgalloc.h> | |
b1ae9a30 | 41 | #include <asm/stage2_pgtable.h> |
5a677ce0 | 42 | |
c8dddecd | 43 | int create_hyp_mappings(void *from, void *to, pgprot_t prot); |
342cd0ab | 44 | int create_hyp_io_mappings(void *from, void *to, phys_addr_t); |
4f728276 | 45 | void free_hyp_pgds(void); |
342cd0ab | 46 | |
957db105 | 47 | void stage2_unmap_vm(struct kvm *kvm); |
d5d8184d CD |
48 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
49 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
50 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 51 | phys_addr_t pa, unsigned long size, bool writable); |
d5d8184d CD |
52 | |
53 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
54 | ||
55 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
56 | ||
342cd0ab | 57 | phys_addr_t kvm_mmu_get_httbr(void); |
5a677ce0 | 58 | phys_addr_t kvm_get_idmap_vector(void); |
342cd0ab CD |
59 | int kvm_mmu_init(void); |
60 | void kvm_clear_hyp_idmap(void); | |
94f8e641 | 61 | |
ad361f09 CD |
62 | static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd) |
63 | { | |
64 | *pmd = new_pmd; | |
dcadda14 | 65 | dsb(ishst); |
ad361f09 CD |
66 | } |
67 | ||
c62ee2b2 MZ |
68 | static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) |
69 | { | |
0963e5d0 | 70 | *pte = new_pte; |
dcadda14 | 71 | dsb(ishst); |
c62ee2b2 MZ |
72 | } |
73 | ||
06485053 | 74 | static inline pte_t kvm_s2pte_mkwrite(pte_t pte) |
c62ee2b2 | 75 | { |
06485053 CM |
76 | pte_val(pte) |= L_PTE_S2_RDWR; |
77 | return pte; | |
c62ee2b2 MZ |
78 | } |
79 | ||
06485053 | 80 | static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd) |
ad361f09 | 81 | { |
06485053 CM |
82 | pmd_val(pmd) |= L_PMD_S2_RDWR; |
83 | return pmd; | |
ad361f09 CD |
84 | } |
85 | ||
c6473555 MS |
86 | static inline void kvm_set_s2pte_readonly(pte_t *pte) |
87 | { | |
88 | pte_val(*pte) = (pte_val(*pte) & ~L_PTE_S2_RDWR) | L_PTE_S2_RDONLY; | |
89 | } | |
90 | ||
91 | static inline bool kvm_s2pte_readonly(pte_t *pte) | |
92 | { | |
93 | return (pte_val(*pte) & L_PTE_S2_RDWR) == L_PTE_S2_RDONLY; | |
94 | } | |
95 | ||
96 | static inline void kvm_set_s2pmd_readonly(pmd_t *pmd) | |
97 | { | |
98 | pmd_val(*pmd) = (pmd_val(*pmd) & ~L_PMD_S2_RDWR) | L_PMD_S2_RDONLY; | |
99 | } | |
100 | ||
101 | static inline bool kvm_s2pmd_readonly(pmd_t *pmd) | |
102 | { | |
103 | return (pmd_val(*pmd) & L_PMD_S2_RDWR) == L_PMD_S2_RDONLY; | |
104 | } | |
105 | ||
4f853a71 CD |
106 | static inline bool kvm_page_empty(void *ptr) |
107 | { | |
108 | struct page *ptr_page = virt_to_page(ptr); | |
109 | return page_count(ptr_page) == 1; | |
110 | } | |
111 | ||
38f791a4 CD |
112 | #define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) |
113 | #define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) | |
b1d030a7 | 114 | #define kvm_pud_table_empty(kvm, pudp) false |
4f853a71 | 115 | |
b1d030a7 SP |
116 | #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) |
117 | #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp) | |
118 | #define hyp_pud_table_empty(pudp) false | |
4f853a71 | 119 | |
c62ee2b2 MZ |
120 | struct kvm; |
121 | ||
15979300 MZ |
122 | #define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) |
123 | ||
124 | static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) | |
125 | { | |
fb32a52a | 126 | return (vcpu_cp15(vcpu, c1_SCTLR) & 0b101) == 0b101; |
15979300 MZ |
127 | } |
128 | ||
ba049e93 DW |
129 | static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, |
130 | kvm_pfn_t pfn, | |
13b7756c | 131 | unsigned long size) |
c62ee2b2 MZ |
132 | { |
133 | /* | |
134 | * If we are going to insert an instruction page and the icache is | |
135 | * either VIPT or PIPT, there is a potential problem where the host | |
136 | * (or another VM) may have used the same page as this guest, and we | |
137 | * read incorrect data from the icache. If we're using a PIPT cache, | |
138 | * we can invalidate just that page, but if we are using a VIPT cache | |
139 | * we need to invalidate the entire icache - damn shame - as written | |
140 | * in the ARM ARM (DDI 0406C.b - Page B3-1393). | |
141 | * | |
142 | * VIVT caches are tagged using both the ASID and the VMID and doesn't | |
143 | * need any kind of flushing (DDI 0406C.b - Page B3-1392). | |
0d3e4d4f MZ |
144 | * |
145 | * We need to do this through a kernel mapping (using the | |
146 | * user-space mapping has proved to be the wrong | |
147 | * solution). For that, we need to kmap one page at a time, | |
148 | * and iterate over the range. | |
c62ee2b2 | 149 | */ |
0d3e4d4f | 150 | |
a050dfb2 | 151 | VM_BUG_ON(size & ~PAGE_MASK); |
0d3e4d4f | 152 | |
0d3e4d4f MZ |
153 | while (size) { |
154 | void *va = kmap_atomic_pfn(pfn); | |
155 | ||
8f36ebaf | 156 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); |
0d3e4d4f MZ |
157 | |
158 | if (icache_is_pipt()) | |
159 | __cpuc_coherent_user_range((unsigned long)va, | |
160 | (unsigned long)va + PAGE_SIZE); | |
161 | ||
162 | size -= PAGE_SIZE; | |
163 | pfn++; | |
164 | ||
165 | kunmap_atomic(va); | |
166 | } | |
167 | ||
0d3e4d4f | 168 | if (!icache_is_pipt() && !icache_is_vivt_asid_tagged()) { |
c62ee2b2 MZ |
169 | /* any kind of VIPT cache */ |
170 | __flush_icache_all(); | |
171 | } | |
172 | } | |
173 | ||
363ef89f MZ |
174 | static inline void __kvm_flush_dcache_pte(pte_t pte) |
175 | { | |
176 | void *va = kmap_atomic(pte_page(pte)); | |
177 | ||
178 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); | |
179 | ||
180 | kunmap_atomic(va); | |
181 | } | |
182 | ||
183 | static inline void __kvm_flush_dcache_pmd(pmd_t pmd) | |
184 | { | |
185 | unsigned long size = PMD_SIZE; | |
ba049e93 | 186 | kvm_pfn_t pfn = pmd_pfn(pmd); |
363ef89f MZ |
187 | |
188 | while (size) { | |
189 | void *va = kmap_atomic_pfn(pfn); | |
190 | ||
191 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); | |
192 | ||
193 | pfn++; | |
194 | size -= PAGE_SIZE; | |
195 | ||
196 | kunmap_atomic(va); | |
197 | } | |
198 | } | |
199 | ||
200 | static inline void __kvm_flush_dcache_pud(pud_t pud) | |
201 | { | |
202 | } | |
203 | ||
4fda342c | 204 | #define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x)) |
5a677ce0 | 205 | |
3c1e7165 MZ |
206 | void kvm_set_way_flush(struct kvm_vcpu *vcpu); |
207 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); | |
9d218a1f | 208 | |
e4c5a685 AB |
209 | static inline bool __kvm_cpu_uses_extended_idmap(void) |
210 | { | |
211 | return false; | |
212 | } | |
213 | ||
214 | static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, | |
215 | pgd_t *hyp_pgd, | |
216 | pgd_t *merged_hyp_pgd, | |
217 | unsigned long hyp_idmap_start) { } | |
218 | ||
20475f78 VM |
219 | static inline unsigned int kvm_get_vmid_bits(void) |
220 | { | |
221 | return 8; | |
222 | } | |
223 | ||
b9c628f6 AP |
224 | /* |
225 | * We are not in the kvm->srcu critical section most of the time, so we take | |
226 | * the SRCU read lock here. Since we copy the data from the user page, we | |
227 | * can immediately drop the lock again. | |
228 | */ | |
229 | static inline int kvm_read_guest_lock(struct kvm *kvm, | |
230 | gpa_t gpa, void *data, unsigned long len) | |
231 | { | |
232 | int srcu_idx = srcu_read_lock(&kvm->srcu); | |
233 | int ret = kvm_read_guest(kvm, gpa, data, len); | |
234 | ||
235 | srcu_read_unlock(&kvm->srcu, srcu_idx); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
bc3eb3e9 MZ |
240 | static inline void *kvm_get_hyp_vector(void) |
241 | { | |
242 | return kvm_ksym_ref(__kvm_hyp_vector); | |
243 | } | |
244 | ||
245 | static inline int kvm_map_vectors(void) | |
246 | { | |
247 | return 0; | |
248 | } | |
249 | ||
5a677ce0 MZ |
250 | #endif /* !__ASSEMBLY__ */ |
251 | ||
342cd0ab | 252 | #endif /* __ARM_KVM_MMU_H__ */ |