[mirror_ubuntu-artful-kernel.git] / arch / arm / include / asm / tlbflush.h

/*
 *  arch/arm/include/asm/tlbflush.h
 *
 *  Copyright (C) 1999-2003 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H

#ifdef CONFIG_MMU

#include <asm/glue.h>

#define TLB_V3_PAGE	(1 << 0)
#define TLB_V4_U_PAGE	(1 << 1)
#define TLB_V4_D_PAGE	(1 << 2)
#define TLB_V4_I_PAGE	(1 << 3)
#define TLB_V6_U_PAGE	(1 << 4)
#define TLB_V6_D_PAGE	(1 << 5)
#define TLB_V6_I_PAGE	(1 << 6)

#define TLB_V3_FULL	(1 << 8)
#define TLB_V4_U_FULL	(1 << 9)
#define TLB_V4_D_FULL	(1 << 10)
#define TLB_V4_I_FULL	(1 << 11)
#define TLB_V6_U_FULL	(1 << 12)
#define TLB_V6_D_FULL	(1 << 13)
#define TLB_V6_I_FULL	(1 << 14)

#define TLB_V6_U_ASID	(1 << 16)
#define TLB_V6_D_ASID	(1 << 17)
#define TLB_V6_I_ASID	(1 << 18)

#define TLB_V6_BP	(1 << 19)

/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
#define TLB_V7_UIS_PAGE	(1 << 20)
#define TLB_V7_UIS_FULL (1 << 21)
#define TLB_V7_UIS_ASID (1 << 22)
#define TLB_V7_UIS_BP	(1 << 23)

#define TLB_BARRIER	(1 << 28)
#define TLB_L2CLEAN_FR	(1 << 29)		/* Feroceon */
#define TLB_DCLEAN	(1 << 30)
#define TLB_WB		(1 << 31)

/*
 *	MMU TLB Model
 *	=============
 *
 *	We have the following to choose from:
 *	  v3    - ARMv3
 *	  v4    - ARMv4 without write buffer
 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
 *	  fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
 *	  fa    - Faraday (v4 with write buffer with UTLB)
 *	  v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
 *	  v7wbi - identical to v6wbi
 */
#undef _TLB
#undef MULTI_TLB

#ifdef CONFIG_SMP_ON_UP
#define MULTI_TLB 1
#endif

#define v4_tlb_flags	(TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_V4WT
# define v4_possible_flags	v4_tlb_flags
# define v4_always_flags	v4_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4
# endif
#else
# define v4_possible_flags	0
# define v4_always_flags	(-1UL)
#endif

#define fa_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_FA
# define fa_possible_flags	fa_tlb_flags
# define fa_always_flags	fa_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB fa
# endif
#else
# define fa_possible_flags	0
# define fa_always_flags	(-1UL)
#endif

#define v4wbi_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WBI
# define v4wbi_possible_flags	v4wbi_tlb_flags
# define v4wbi_always_flags	v4wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define v4wbi_possible_flags	0
# define v4wbi_always_flags	(-1UL)
#endif

#define fr_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_FEROCEON
# define fr_possible_flags	fr_tlb_flags
# define fr_always_flags	fr_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define fr_possible_flags	0
# define fr_always_flags	(-1UL)
#endif

#define v4wb_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WB
# define v4wb_possible_flags	v4wb_tlb_flags
# define v4wb_always_flags	v4wb_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wb
# endif
#else
# define v4wb_possible_flags	0
# define v4wb_always_flags	(-1UL)
#endif

#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V6_I_FULL | TLB_V6_D_FULL | \
			 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
			 TLB_V6_I_ASID | TLB_V6_D_ASID | \
			 TLB_V6_BP)

#ifdef CONFIG_CPU_TLB_V6
# define v6wbi_possible_flags	v6wbi_tlb_flags
# define v6wbi_always_flags	v6wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v6wbi
# endif
#else
# define v6wbi_possible_flags	0
# define v6wbi_always_flags	(-1UL)
#endif

#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
				 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
				 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
				 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
				 TLB_V6_U_ASID | TLB_V6_BP)

#ifdef CONFIG_CPU_TLB_V7

# ifdef CONFIG_SMP_ON_UP
#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
# elif defined(CONFIG_SMP)
#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
# else
#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
#  define v7wbi_always_flags	v7wbi_tlb_flags_up
# endif
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v7wbi
# endif
#else
# define v7wbi_possible_flags	0
# define v7wbi_always_flags	(-1UL)
#endif

#ifndef _TLB
#error Unknown TLB model
#endif

#ifndef __ASSEMBLY__

#include <linux/sched.h>

struct cpu_tlb_fns {
	void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
	void (*flush_kern_range)(unsigned long, unsigned long);
	unsigned long tlb_flags;
};

/*
 * Select the calling method
 */
#ifdef MULTI_TLB

#define __cpu_flush_user_tlb_range	cpu_tlb.flush_user_range
#define __cpu_flush_kern_tlb_range	cpu_tlb.flush_kern_range

#else

#define __cpu_flush_user_tlb_range	__glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_kern_tlb_range	__glue(_TLB,_flush_kern_tlb_range)

extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);

#endif

extern struct cpu_tlb_fns cpu_tlb;

#define __cpu_tlb_flags			cpu_tlb.tlb_flags

/*
 *	TLB Management
 *	==============
 *
 *	The arch/arm/mm/tlb-*.S files implement these methods.
 *
 *	The TLB specific code is expected to perform whatever tests it
 *	needs to determine if it should invalidate the TLB for each
 *	call.  Start addresses are inclusive and end addresses are
 *	exclusive; it is safe to round these addresses down.
 *
 *	flush_tlb_all()
 *
 *		Invalidate the entire TLB.
 *
 *	flush_tlb_mm(mm)
 *
 *		Invalidate all TLB entries in a particular address
 *		space.
 *		- mm	- mm_struct describing address space
 *
 *	flush_tlb_range(mm,start,end)
 *
 *		Invalidate a range of TLB entries in the specified
 *		address space.
 *		- mm	- mm_struct describing address space
 *		- start - start address (may not be aligned)
 *		- end	- end address (exclusive, may not be aligned)
 *
 *	flush_tlb_page(vaddr,vma)
 *
 *		Invalidate the specified page in the specified address range.
 *		- vaddr - virtual address (may not be aligned)
 *		- vma	- vma_struct describing address range
 *
 *	flush_kern_tlb_page(kaddr)
 *
 *		Invalidate the TLB entry for the specified page.  The address
 *		will be in the kernels virtual memory space.  Current uses
 *		only require the D-TLB to be invalidated.
 *		- kaddr - Kernel virtual memory address
 */

/*
 * We optimise the code below by:
 *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 *  - if we're going to need __cpu_tlb_flags, access it once and only once
 *
 * This allows us to build optimal assembly for the single-CPU type case,
 * and as close to optimal given the compiler constrants for multi-CPU
 * case.  We could do better for the multi-CPU case if the compiler
 * implemented the "%?" method, but this has been discontinued due to too
 * many people getting it wrong.
 */
#define possible_tlb_flags	(v4_possible_flags | \
				 v4wbi_possible_flags | \
				 fr_possible_flags | \
				 v4wb_possible_flags | \
				 fa_possible_flags | \
				 v6wbi_possible_flags | \
				 v7wbi_possible_flags)

#define always_tlb_flags	(v4_always_flags & \
				 v4wbi_always_flags & \
				 fr_always_flags & \
				 v4wb_always_flags & \
				 fa_always_flags & \
				 v6wbi_always_flags & \
				 v7wbi_always_flags)

#define tlb_flag(f)	((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))

#define __tlb_op(f, insnarg, arg)					\
	do {								\
		if (always_tlb_flags & (f))				\
			asm("mcr " insnarg				\
			    : : "r" (arg) : "cc");			\
		else if (possible_tlb_flags & (f))			\
			asm("tst %1, %2\n\t"				\
			    "mcrne " insnarg				\
			    : : "r" (arg), "r" (__tlb_flag), "Ir" (f)	\
			    : "cc");					\
	} while (0)

#define tlb_op(f, regs, arg)	__tlb_op(f, "p15, 0, %0, " regs, arg)
#define tlb_l2_op(f, regs, arg)	__tlb_op(f, "p15, 1, %0, " regs, arg)

static inline void local_flush_tlb_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

static inline void local_flush_tlb_mm(struct mm_struct *mm)
{
	const int zero = 0;
	const int asid = ASID(mm);
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
			tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
		}
		put_cpu();
	}

	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
#ifdef CONFIG_ARM_ERRATA_720789
	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
#else
	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void
local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);

	if (tlb_flag(TLB_WB))
		dsb();

	if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
	    cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
		tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
		if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}

	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
#ifdef CONFIG_ARM_ERRATA_720789
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
#else
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	kaddr &= PAGE_MASK;

	if (tlb_flag(TLB_WB))
		dsb();

	tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

static inline void local_flush_bp_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_V7_UIS_BP))
		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
	else if (tlb_flag(TLB_V6_BP))
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));

	if (tlb_flag(TLB_BARRIER))
		isb();
}

#ifdef CONFIG_ARM_ERRATA_798181
static inline void dummy_flush_tlb_a15_erratum(void)
{
	/*
	 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
	 */
	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	dsb();
}
#else
static inline void dummy_flush_tlb_a15_erratum(void)
{
}
#endif

/*
 *	flush_pmd_entry
 *
 *	Flush a PMD entry (word aligned, or double-word aligned) to
 *	RAM if the TLB for the CPU we are running on requires this.
 *	This is typically used when we are creating PMD entries.
 *
 *	clean_pmd_entry
 *
 *	Clean (but don't drain the write buffer) if the CPU requires
 *	these operations.  This is typically used when we are removing
 *	PMD entries.
 */
static inline void flush_pmd_entry(void *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);

	if (tlb_flag(TLB_WB))
		dsb();
}

static inline void clean_pmd_entry(void *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
}

#undef tlb_op
#undef tlb_flag
#undef always_tlb_flags
#undef possible_tlb_flags

/*
 * Convert calls to our calling convention.
 */
#define local_flush_tlb_range(vma,start,end)	__cpu_flush_user_tlb_range(start,end,vma)
#define local_flush_tlb_kernel_range(s,e)	__cpu_flush_kern_tlb_range(s,e)

#ifndef CONFIG_SMP
#define flush_tlb_all		local_flush_tlb_all
#define flush_tlb_mm		local_flush_tlb_mm
#define flush_tlb_page		local_flush_tlb_page
#define flush_tlb_kernel_page	local_flush_tlb_kernel_page
#define flush_tlb_range		local_flush_tlb_range
#define flush_tlb_kernel_range	local_flush_tlb_kernel_range
#define flush_bp_all		local_flush_bp_all
#else
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
extern void flush_tlb_kernel_page(unsigned long kaddr);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
extern void flush_bp_all(void);
#endif

/*
 * If PG_dcache_clean is not set for the page, we need to ensure that any
 * cache entries for the kernels virtual memory range are written
 * back to the page. On ARMv6 and later, the cache coherency is handled via
 * the set_pte_at() function.
 */
#if __LINUX_ARM_ARCH__ < 6
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
	pte_t *ptep);
#else
static inline void update_mmu_cache(struct vm_area_struct *vma,
				    unsigned long addr, pte_t *ptep)
{
}
#endif

#endif

#endif /* CONFIG_MMU */

#endif
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/tlbflush.h
1da177e4 LT	3	*
	4	* Copyright (C) 1999-2003 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_TLBFLUSH_H
	11	#define _ASMARM_TLBFLUSH_H
	12
58e9c47f	13	#ifdef CONFIG_MMU
0157903e	14
1da177e4 LT	15	#include <asm/glue.h>
	16
	17	#define TLB_V3_PAGE (1 << 0)
	18	#define TLB_V4_U_PAGE (1 << 1)
	19	#define TLB_V4_D_PAGE (1 << 2)
	20	#define TLB_V4_I_PAGE (1 << 3)
	21	#define TLB_V6_U_PAGE (1 << 4)
	22	#define TLB_V6_D_PAGE (1 << 5)
	23	#define TLB_V6_I_PAGE (1 << 6)
	24
	25	#define TLB_V3_FULL (1 << 8)
	26	#define TLB_V4_U_FULL (1 << 9)
	27	#define TLB_V4_D_FULL (1 << 10)
	28	#define TLB_V4_I_FULL (1 << 11)
	29	#define TLB_V6_U_FULL (1 << 12)
	30	#define TLB_V6_D_FULL (1 << 13)
	31	#define TLB_V6_I_FULL (1 << 14)
	32
	33	#define TLB_V6_U_ASID (1 << 16)
	34	#define TLB_V6_D_ASID (1 << 17)
	35	#define TLB_V6_I_ASID (1 << 18)
	36
862c588f WD	37	#define TLB_V6_BP (1 << 19)
862c588f WD	38
faa7bc51	39	/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
862c588f WD	40	#define TLB_V7_UIS_PAGE (1 << 20)
	41	#define TLB_V7_UIS_FULL (1 << 21)
	42	#define TLB_V7_UIS_ASID (1 << 22)
	43	#define TLB_V7_UIS_BP (1 << 23)
faa7bc51	44
4348810a	45	#define TLB_BARRIER (1 << 28)
99c6dc11	46	#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
1da177e4 LT	47	#define TLB_DCLEAN (1 << 30)
	48	#define TLB_WB (1 << 31)
	49
	50	/*
	51	* MMU TLB Model
	52	* =============
	53	*
	54	* We have the following to choose from:
	55	* v3 - ARMv3
	56	* v4 - ARMv4 without write buffer
	57	* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
	58	* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
99c6dc11	59	* fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
4348810a	60	* fa - Faraday (v4 with write buffer with UTLB)
1da177e4	61	* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
61db7fb1	62	* v7wbi - identical to v6wbi
1da177e4 LT	63	*/
	64	#undef _TLB
	65	#undef MULTI_TLB
	66
f00ec48f RK	67	#ifdef CONFIG_SMP_ON_UP
	68	#define MULTI_TLB 1
	69	#endif
	70
1da177e4 LT	71	#define v4_tlb_flags (TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	72
	73	#ifdef CONFIG_CPU_TLB_V4WT
	74	# define v4_possible_flags v4_tlb_flags
	75	# define v4_always_flags v4_tlb_flags
	76	# ifdef _TLB
	77	# define MULTI_TLB 1
	78	# else
	79	# define _TLB v4
	80	# endif
	81	#else
	82	# define v4_possible_flags 0
	83	# define v4_always_flags (-1UL)
	84	#endif
	85
4348810a	86	#define fa_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
28853ac8 PZ	87	TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	88
	89	#ifdef CONFIG_CPU_TLB_FA
	90	# define fa_possible_flags fa_tlb_flags
	91	# define fa_always_flags fa_tlb_flags
	92	# ifdef _TLB
	93	# define MULTI_TLB 1
	94	# else
	95	# define _TLB fa
	96	# endif
	97	#else
	98	# define fa_possible_flags 0
	99	# define fa_always_flags (-1UL)
	100	#endif
	101
1da177e4 LT	102	#define v4wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	103	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	104	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	105
	106	#ifdef CONFIG_CPU_TLB_V4WBI
	107	# define v4wbi_possible_flags v4wbi_tlb_flags
	108	# define v4wbi_always_flags v4wbi_tlb_flags
	109	# ifdef _TLB
	110	# define MULTI_TLB 1
	111	# else
	112	# define _TLB v4wbi
	113	# endif
	114	#else
	115	# define v4wbi_possible_flags 0
	116	# define v4wbi_always_flags (-1UL)
	117	#endif
	118
99c6dc11 LB	119	#define fr_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_L2CLEAN_FR \| \
	120	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	121	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	122
	123	#ifdef CONFIG_CPU_TLB_FEROCEON
	124	# define fr_possible_flags fr_tlb_flags
	125	# define fr_always_flags fr_tlb_flags
	126	# ifdef _TLB
	127	# define MULTI_TLB 1
	128	# else
	129	# define _TLB v4wbi
	130	# endif
	131	#else
	132	# define fr_possible_flags 0
	133	# define fr_always_flags (-1UL)
	134	#endif
	135
1da177e4 LT	136	#define v4wb_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	137	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	138	TLB_V4_D_PAGE)
	139
	140	#ifdef CONFIG_CPU_TLB_V4WB
	141	# define v4wb_possible_flags v4wb_tlb_flags
	142	# define v4wb_always_flags v4wb_tlb_flags
	143	# ifdef _TLB
	144	# define MULTI_TLB 1
	145	# else
	146	# define _TLB v4wb
	147	# endif
	148	#else
	149	# define v4wb_possible_flags 0
	150	# define v4wb_always_flags (-1UL)
	151	#endif
	152
4348810a	153	#define v6wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
1da177e4 LT	154	TLB_V6_I_FULL \| TLB_V6_D_FULL \| \
1da177e4 LT	155	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \| \
862c588f WD	156	TLB_V6_I_ASID \| TLB_V6_D_ASID \| \
862c588f WD	157	TLB_V6_BP)
1da177e4 LT	158
	159	#ifdef CONFIG_CPU_TLB_V6
	160	# define v6wbi_possible_flags v6wbi_tlb_flags
	161	# define v6wbi_always_flags v6wbi_tlb_flags
	162	# ifdef _TLB
	163	# define MULTI_TLB 1
	164	# else
	165	# define _TLB v6wbi
	166	# endif
	167	#else
	168	# define v6wbi_possible_flags 0
	169	# define v6wbi_always_flags (-1UL)
	170	#endif
	171
4348810a	172	#define v7wbi_tlb_flags_smp (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
862c588f WD	173	TLB_V7_UIS_FULL \| TLB_V7_UIS_PAGE \| \
862c588f WD	174	TLB_V7_UIS_ASID \| TLB_V7_UIS_BP)
4348810a	175	#define v7wbi_tlb_flags_up (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
862c588f WD	176	TLB_V6_U_FULL \| TLB_V6_U_PAGE \| \
862c588f WD	177	TLB_V6_U_ASID \| TLB_V6_BP)
faa7bc51	178
2ccdd1e7	179	#ifdef CONFIG_CPU_TLB_V7
f00ec48f RK	180
	181	# ifdef CONFIG_SMP_ON_UP
	182	# define v7wbi_possible_flags (v7wbi_tlb_flags_smp \| v7wbi_tlb_flags_up)
	183	# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
	184	# elif defined(CONFIG_SMP)
	185	# define v7wbi_possible_flags v7wbi_tlb_flags_smp
	186	# define v7wbi_always_flags v7wbi_tlb_flags_smp
	187	# else
	188	# define v7wbi_possible_flags v7wbi_tlb_flags_up
	189	# define v7wbi_always_flags v7wbi_tlb_flags_up
	190	# endif
2ccdd1e7 CM	191	# ifdef _TLB
	192	# define MULTI_TLB 1
	193	# else
	194	# define _TLB v7wbi
	195	# endif
	196	#else
	197	# define v7wbi_possible_flags 0
	198	# define v7wbi_always_flags (-1UL)
	199	#endif
	200
1da177e4 LT	201	#ifndef _TLB
	202	#error Unknown TLB model
	203	#endif
	204
	205	#ifndef __ASSEMBLY__
	206
e8edc6e0 AD	207	#include <linux/sched.h>
e8edc6e0 AD	208
1da177e4 LT	209	struct cpu_tlb_fns {
	210	void (flush_user_range)(unsigned long, unsigned long, struct vm_area_struct );
	211	void (*flush_kern_range)(unsigned long, unsigned long);
	212	unsigned long tlb_flags;
	213	};
	214
	215	/*
	216	* Select the calling method
	217	*/
	218	#ifdef MULTI_TLB
	219
	220	#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
	221	#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
	222
	223	#else
	224
	225	#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
	226	#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
	227
	228	extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
	229	extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
	230
	231	#endif
	232
	233	extern struct cpu_tlb_fns cpu_tlb;
	234
	235	#define __cpu_tlb_flags cpu_tlb.tlb_flags
	236
	237	/*
	238	* TLB Management
	239	* ==============
	240	*
	241	* The arch/arm/mm/tlb-*.S files implement these methods.
	242	*
	243	* The TLB specific code is expected to perform whatever tests it
	244	* needs to determine if it should invalidate the TLB for each
	245	* call. Start addresses are inclusive and end addresses are
	246	* exclusive; it is safe to round these addresses down.
	247	*
	248	* flush_tlb_all()
	249	*
	250	* Invalidate the entire TLB.
	251	*
	252	* flush_tlb_mm(mm)
	253	*
	254	* Invalidate all TLB entries in a particular address
	255	* space.
	256	* - mm - mm_struct describing address space
	257	*
	258	* flush_tlb_range(mm,start,end)
	259	*
	260	* Invalidate a range of TLB entries in the specified
	261	* address space.
	262	* - mm - mm_struct describing address space
	263	* - start - start address (may not be aligned)
	264	* - end - end address (exclusive, may not be aligned)
	265	*
	266	* flush_tlb_page(vaddr,vma)
	267	*
	268	* Invalidate the specified page in the specified address range.
	269	* - vaddr - virtual address (may not be aligned)
	270	* - vma - vma_struct describing address range
	271	*
	272	* flush_kern_tlb_page(kaddr)
273	*
274	* Invalidate the TLB entry for the specified page. The address
275	* will be in the kernels virtual memory space. Current uses
276	* only require the D-TLB to be invalidated.
277	* - kaddr - Kernel virtual memory address
278	*/
279
280	/*
281	* We optimise the code below by:
282	* - building a set of TLB flags that might be set in __cpu_tlb_flags
283	* - building a set of TLB flags that will always be set in __cpu_tlb_flags
284	* - if we're going to need __cpu_tlb_flags, access it once and only once
285	*
286	* This allows us to build optimal assembly for the single-CPU type case,
287	* and as close to optimal given the compiler constrants for multi-CPU
288	* case. We could do better for the multi-CPU case if the compiler
289	* implemented the "%?" method, but this has been discontinued due to too
290	* many people getting it wrong.
291	*/
357c9c1f	292	#define possible_tlb_flags (v4_possible_flags \| \
1da177e4	293	v4wbi_possible_flags \| \
99c6dc11	294	fr_possible_flags \| \
1da177e4	295	v4wb_possible_flags \| \
28853ac8	296	fa_possible_flags \| \
61db7fb1 PW	297	v6wbi_possible_flags \| \
61db7fb1 PW	298	v7wbi_possible_flags)
1da177e4	299
357c9c1f	300	#define always_tlb_flags (v4_always_flags & \
1da177e4	301	v4wbi_always_flags & \
99c6dc11	302	fr_always_flags & \
1da177e4	303	v4wb_always_flags & \
28853ac8	304	fa_always_flags & \
61db7fb1 PW	305	v6wbi_always_flags & \
61db7fb1 PW	306	v7wbi_always_flags)
1da177e4 LT	307
	308	#define tlb_flag(f) ((always_tlb_flags & (f)) \|\| (__tlb_flag & possible_tlb_flags & (f)))
	309
87067a93 RK	310	#define __tlb_op(f, insnarg, arg) \
	311	do { \
	312	if (always_tlb_flags & (f)) \
	313	asm("mcr " insnarg \
	314	: : "r" (arg) : "cc"); \
	315	else if (possible_tlb_flags & (f)) \
	316	asm("tst %1, %2\n\t" \
	317	"mcrne " insnarg \
	318	: : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
	319	: "cc"); \
	320	} while (0)
	321
	322	#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
	323	#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
	324
603fff54	325	static inline void local_flush_tlb_all(void)
1da177e4 LT	326	{
	327	const int zero = 0;
	328	const unsigned int __tlb_flag = __cpu_tlb_flags;
	329
	330	if (tlb_flag(TLB_WB))
e6a5d66f	331	dsb();
1da177e4	332
87067a93 RK	333	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
	334	tlb_op(TLB_V4_U_FULL \| TLB_V6_U_FULL, "c8, c7, 0", zero);
	335	tlb_op(TLB_V4_D_FULL \| TLB_V6_D_FULL, "c8, c6, 0", zero);
	336	tlb_op(TLB_V4_I_FULL \| TLB_V6_I_FULL, "c8, c5, 0", zero);
	337	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
e6a5d66f	338
4348810a	339	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	340	dsb();
	341	isb();
	342	}
1da177e4 LT	343	}
1da177e4 LT	344
603fff54	345	static inline void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	346	{
	347	const int zero = 0;
	348	const int asid = ASID(mm);
	349	const unsigned int __tlb_flag = __cpu_tlb_flags;
	350
	351	if (tlb_flag(TLB_WB))
e6a5d66f	352	dsb();
1da177e4	353
87067a93 RK	354	if (possible_tlb_flags & (TLB_V3_FULL\|TLB_V4_U_FULL\|TLB_V4_D_FULL\|TLB_V4_I_FULL)) {
	355	if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
	356	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
	357	tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
	358	tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
	359	tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
	360	}
	361	put_cpu();
1da177e4	362	}
87067a93 RK	363
	364	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
	365	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
	366	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
cdf357f1	367	#ifdef CONFIG_ARM_ERRATA_720789
87067a93	368	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
cdf357f1	369	#else
87067a93	370	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
cdf357f1	371	#endif
e6a5d66f	372
4348810a	373	if (tlb_flag(TLB_BARRIER))
b8349b56	374	dsb();
1da177e4 LT	375	}
	376
	377	static inline void
603fff54	378	local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
1da177e4 LT	379	{
	380	const int zero = 0;
	381	const unsigned int __tlb_flag = __cpu_tlb_flags;
	382
	383	uaddr = (uaddr & PAGE_MASK) \| ASID(vma->vm_mm);
	384
	385	if (tlb_flag(TLB_WB))
e6a5d66f	386	dsb();
1da177e4	387
87067a93 RK	388	if (possible_tlb_flags & (TLB_V3_PAGE\|TLB_V4_U_PAGE\|TLB_V4_D_PAGE\|TLB_V4_I_PAGE\|TLB_V4_I_FULL) &&
	389	cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
	390	tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
	391	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
	392	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
	393	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
1da177e4	394	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	395	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	396	}
1da177e4 LT	397
87067a93 RK	398	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
	399	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
	400	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
cdf357f1	401	#ifdef CONFIG_ARM_ERRATA_720789
87067a93	402	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
cdf357f1	403	#else
87067a93	404	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
cdf357f1	405	#endif
e6a5d66f	406
4348810a	407	if (tlb_flag(TLB_BARRIER))
b8349b56	408	dsb();
1da177e4 LT	409	}
1da177e4 LT	410
603fff54	411	static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
1da177e4 LT	412	{
	413	const int zero = 0;
	414	const unsigned int __tlb_flag = __cpu_tlb_flags;
	415
	416	kaddr &= PAGE_MASK;
	417
	418	if (tlb_flag(TLB_WB))
e6a5d66f	419	dsb();
1da177e4	420
87067a93 RK	421	tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
	422	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
	423	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
	424	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
1da177e4	425	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	426	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4	427
87067a93 RK	428	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
	429	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
	430	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
	431	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
6a0e2430	432
4348810a	433	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	434	dsb();
	435	isb();
	436	}
1da177e4 LT	437	}
1da177e4 LT	438
862c588f WD	439	static inline void local_flush_bp_all(void)
	440	{
	441	const int zero = 0;
	442	const unsigned int __tlb_flag = __cpu_tlb_flags;
	443
	444	if (tlb_flag(TLB_V7_UIS_BP))
	445	asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
	446	else if (tlb_flag(TLB_V6_BP))
	447	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
	448
	449	if (tlb_flag(TLB_BARRIER))
	450	isb();
	451	}
	452
93dc6887 CM	453	#ifdef CONFIG_ARM_ERRATA_798181
	454	static inline void dummy_flush_tlb_a15_erratum(void)
	455	{
	456	/*
	457	* Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
	458	*/
	459	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	460	dsb();
	461	}
	462	#else
	463	static inline void dummy_flush_tlb_a15_erratum(void)
	464	{
	465	}
	466	#endif
	467
1da177e4 LT	468	/*
	469	* flush_pmd_entry
	470	*
	471	* Flush a PMD entry (word aligned, or double-word aligned) to
	472	* RAM if the TLB for the CPU we are running on requires this.
	473	* This is typically used when we are creating PMD entries.
	474	*
	475	* clean_pmd_entry
	476	*
	477	* Clean (but don't drain the write buffer) if the CPU requires
	478	* these operations. This is typically used when we are removing
	479	* PMD entries.
	480	*/
442e70c0	481	static inline void flush_pmd_entry(void *pmd)
1da177e4	482	{
1da177e4 LT	483	const unsigned int __tlb_flag = __cpu_tlb_flags;
1da177e4 LT	484
87067a93 RK	485	tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
87067a93 RK	486	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
99c6dc11	487
1da177e4	488	if (tlb_flag(TLB_WB))
e6a5d66f	489	dsb();
1da177e4 LT	490	}
1da177e4 LT	491
442e70c0	492	static inline void clean_pmd_entry(void *pmd)
1da177e4 LT	493	{
	494	const unsigned int __tlb_flag = __cpu_tlb_flags;
	495
87067a93 RK	496	tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
87067a93 RK	497	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
1da177e4 LT	498	}
1da177e4 LT	499
87067a93	500	#undef tlb_op
1da177e4 LT	501	#undef tlb_flag
	502	#undef always_tlb_flags
	503	#undef possible_tlb_flags
	504
	505	/*
	506	* Convert calls to our calling convention.
	507	*/
603fff54 RK	508	#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
	509	#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
	510
	511	#ifndef CONFIG_SMP
	512	#define flush_tlb_all local_flush_tlb_all
	513	#define flush_tlb_mm local_flush_tlb_mm
	514	#define flush_tlb_page local_flush_tlb_page
	515	#define flush_tlb_kernel_page local_flush_tlb_kernel_page
	516	#define flush_tlb_range local_flush_tlb_range
	517	#define flush_tlb_kernel_range local_flush_tlb_kernel_range
862c588f	518	#define flush_bp_all local_flush_bp_all
603fff54 RK	519	#else
	520	extern void flush_tlb_all(void);
	521	extern void flush_tlb_mm(struct mm_struct *mm);
	522	extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
	523	extern void flush_tlb_kernel_page(unsigned long kaddr);
	524	extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	525	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
862c588f	526	extern void flush_bp_all(void);
603fff54	527	#endif
1da177e4 LT	528
1da177e4 LT	529	/*
c0177800	530	* If PG_dcache_clean is not set for the page, we need to ensure that any
1da177e4	531	* cache entries for the kernels virtual memory range are written
6012191a CM	532	* back to the page. On ARMv6 and later, the cache coherency is handled via
6012191a CM	533	* the set_pte_at() function.
1da177e4	534	*/
6012191a	535	#if __LINUX_ARM_ARCH__ < 6
4b3073e1 RK	536	extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
4b3073e1 RK	537	pte_t *ptep);
6012191a CM	538	#else
	539	static inline void update_mmu_cache(struct vm_area_struct *vma,
	540	unsigned long addr, pte_t *ptep)
	541	{
	542	}
	543	#endif
1da177e4	544
1da177e4 LT	545	#endif
1da177e4 LT	546
0157903e HC	547	#endif /* CONFIG_MMU */
0157903e HC	548
1da177e4	549	#endif